KR20180082297A - Contact plugs and methods forming same - Google Patents

Abstract

The present invention relates to a contact plug and a method forming the same. The method includes a transistor forming step which includes the steps of: forming a dummy gate stack over a semiconductor region; and forming an inter-layer dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes the steps of: removing the dummy gate stack to form a trench in the first ILD; forming a low-k gate spacer in the trench; forming a replacement gate dielectric extended into the trench; forming a metal layer to fill the trench; and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer and form a gate dielectric and a metal gate, respectively. And then, a source region and a drain region are formed on opposite sides of the metal gate. The present invention saves costs for etching-back and forming a hard mask.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a contact plug,

[Priority claim and cross reference]

This application claims the benefit of U.S. Provisional Patent Application No. 10/1994, filed on January 9, 2017, which is hereby incorporated by reference and is entitled " Contact Plugs and Methods Forming Same ". 62 / 443,885.

In recent transistor development, metal is used to form contact plugs and metal gates. A contact plug is used to connect to the source and drain regions and the gate of the transistor. The source / drain contact plug is typically connected to a source / drain silicide region that is formed by depositing a metal layer and then performing an anneal to react the silicon and metal layers in the source / drain regions. A gate contact plug is used to connect to the metal gate.

The formation of the metal gate may include forming a dummy gate stack, removing the dummy gate stack to form an opening, filling the opening with a metal material, and removing the excess metal material to form a metal gate And then performing planarization to form the planar surface. The metal gate is then recessed to form a recess and the recess is filled with a dielectric hard mask. When the gate contact plug is formed, the hard mask is removed so that the gate contact plug can contact the metal gate.

BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present invention are best understood from the following detailed description with reference to the accompanying drawings. It is mentioned that various features are not shown proportionally according to standard practice in this industry. Indeed, the dimensions of the various features may optionally be increased or decreased for clarity of discussion.
Figures 1-21 are a perspective view and a cross-sectional view of an intermediate stage in the formation of a transistor according to some embodiments.
22 shows a process for forming a transistor and a contact plug according to some embodiments.

The following description provides a number of different embodiments or embodiments for implementing the different features of the present invention. To simplify the present invention, specific embodiments of components and arrangements are disclosed below. Of course, this is illustrative only and not intended to be limiting. For example, in the ensuing description, the formation of the first feature on or above the second feature may include an embodiment in which the first and second features are formed and in direct contact, and wherein the first and second features are in direct contact But may include embodiments in which additional features may be formed between the first and second features. Furthermore, the present invention may be repeated with reference numerals and / or characters in various embodiments. Such repetition is for the sake of simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

It will also be appreciated that space-related terms such as "under," "under," "under," "above," "above," and the like, ) Can be used for convenience of explanation. Spatial terms are intended to encompass different orientations of the device in use or operation with respect to the orientations shown in the figures. The device may be oriented differently (rotated 90 degrees or other orientations), so that the spatial related descriptors used herein can be similarly interpreted.

A transistor according to various exemplary embodiments and a method of forming the same are provided. An intermediate stage of transistor formation according to some embodiments is illustrated. Several variations of some embodiments are discussed. Throughout the various drawings and the illustrative embodiments, like reference numerals are used to denote like elements. In the illustrated exemplary embodiments, the formation of FinFETs (Fin Field-Effect Transistors) is used as an example to illustrate the concepts of the present disclosure. Planar transistors may also adopt the concept of this disclosure.

Figures 1-21 show cross-sectional and perspective views of an intermediate stage in the formation of a FinFET in accordance with some embodiments of the present disclosure. The steps shown in Figs. 1-21 are also roughly reflected in the process flow shown in Fig.

Figure 1 shows a perspective view of an initial structure. The initial structure includes a wafer 10 further comprising a substrate 20. The substrate 20 may be a semiconductor substrate, and the semiconductor substrate may be a silicon substrate, a silicon germanium substrate, or a substrate formed of another semiconductor material. The substrate 20 may be doped with p-type or n-type impurities. Isolation regions 22 such as shallow trench isolation (STI) regions may be formed to extend from the top surface of the substrate 20 to the substrate 20, The major surface is 10A. A portion of the substrate 20 between adjacent STI regions 22 is referred to as a semiconductor strip 24. The upper surface of the semiconductor strip 24 and the upper surface of the STI region 22 may be at substantially the same level as each other.

The STI region 22 may comprise a liner oxide (not shown), which may be a thermal oxide formed through thermal oxidation of the surface layer of the substrate 20. The liner oxide may be a deposited silicon oxide layer formed using, for example, ALD (Atomic Layer Deposition), HDPCVD (High-Density Plasma Chemical Vapor Deposition), or CVD (Chemical Vapor Deposition). The STI regions 22 may comprise a dielectric material over the liner oxide and the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin-on, or the like.

Referring to Figure 2, the STI regions 22 are formed such that the upper portions of the semiconductor strips 24 are closer to the top surfaces of the STI regions 22 to form the projecting fins 24 ' And is recessed so as to protrude higher. The etching can be performed using a dry etching process in which HF ₃ and NH ₃ are used as the etching gases. Plasma can be generated during the etching process. Argon may also be included. According to alternative embodiments of the present disclosure, recessing of the STI regions 22 is performed using a wet etch process. The etch chemistry may include, for example, HF.

Referring to FIG. 3, a dummy gate stack 30 is formed on top surfaces and sidewalls of (projected) pins 24 '. Although one dummy gate stack 30 has been illustrated for clarity, a plurality of dummy gate stacks may be formed that intersect the same semiconductor pin (s) 24 'and are parallel to one another. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 above the dummy gate dielectric 32. The dummy gate electrode 34 may be formed using polysilicon, for example, and other materials may be used. The dummy gate stack 30 may comprise one (or more) hardmask layer 36 on the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon carbide-nitride, or the like. The dummy gate stack 30 may cross over one or more of the protruding pins 24 'and / or the STI regions 22. The dummy gate stack 30 may have a longitudinal direction perpendicular to the longitudinal directions of the projecting pins 24 '.

Gate spacers 38 are then formed on the sidewalls of the dummy gate stack 30. According to some embodiments of the present disclosure, the gate spacers 38 are formed of a dielectric material such as silicon nitride, silicon carbide-nitride (SiCN), or the like, and may have a single layer structure or a multilayer structure including a plurality of dielectric layers Lt; / RTI >

The etching step for etching portions of the dummy gate stack 30 in which the structure shown in FIG. 4 is made and the protruding fins 24 'not covered by the gate spacers 38 (hereinafter referred to as source / Is performed. The recessing may be anisotropic, so that some of the fins 24 'immediately below the dummy gate stack 30 and gate spacers 38 are not protected and etched. In some embodiments, the upper surfaces of the recessed semiconductor strips 24 may be lower than the upper surfaces 22A of the STI regions 22. Thus, recesses 40 are formed between the STI regions 22. The recesses 40 are disposed on opposite sides of the dummy gate stack 30.

The epitaxial regions (source / drain regions) 42 are then formed by selectively growing a semiconductor material in the recesses 40 that make up the structure in FIG. 5A. According to some exemplary embodiments, the epitaxial regions 42 comprise silicon germanium or silicon. Depending on whether the obtained FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities may be doped in-situ in the proceeding of epitaxy. For example, when the FinFET obtained is a p-type FinFET, SiGeB (silicon germanium boron) can be grown. Conversely, when the obtained FinFET is an n-type FinFET, SiP (silicon phosphorous) or SiCP (silicon carbon phosphorous) can be grown. According to alternative embodiments of the present disclosure, epitaxial growth of a III-V compound semiconductor such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, Regions 42 are formed. After the epitaxy regions 42 completely fill the recesses 40, the epitaxy regions 42 begin to expand horizontally and facets can be formed.

After the epitaxial step, p-type impurities or n-type impurities may be further implanted into the epitaxial regions 42 to form the source and drain regions, According to alternative embodiments of the present disclosure, when the epitaxial regions 42 during epitaxy are doped in-situ with a p-type impurity or an n-type impurity, the implantation step is omitted. The epitaxy source / drain region 42 includes bottom portions 42A formed in the STI regions 22 and top portions 42B formed over the top surfaces of the STI regions 22. The epitaxial source / The lower portions 42A in which the sidewalls are formed along the shape of the recesses 40 define a substantially vertical edge substantially perpendicular to the major surfaces of the substrate 20 (such as the bottom surface 20B) And may have (substantially) straight edges which may be straight lines.

6A shows a perspective view of a structure in which an ILD (Inter-Layer Dielectric) 46 is formed. According to some embodiments of the present disclosure, a buffer oxide layer (not shown) and a contact etch stop layer (CESL) 47 are formed on the source and drain regions 42 prior to the formation of the ILD 46. The buffer oxide layer may be formed of silicon oxide, and the CESL 47 may be formed of silicon nitride, silicon carbide-nitride, or the like. The buffer oxide layer and the CESL 47 may be formed using a conformal deposition method such as ALD. The ILD 46 may comprise a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or other deposition methods. The ILD 46 may be formed of an oxide such as TEOS (Tetra Ethyl Ortho Silicate), PECVD (Plasma Enhanced CVD) oxide (SiO ₂ ), Phospho-Silicate Glass (PSG), Borosilicate Glass (BSG), Boron-Doped Phospho -Silicate Glass) or the like. A planarization step such as CMP (Chemical Mechanical Polish) or mechanical polishing may be performed to equalize the level of the upper surfaces of ILD 46, dummy gate stack 30, and gate spacers 38 to one another.

A cross-sectional view of the structure shown in Fig. 6A is shown in Fig. 6B, which is taken from a vertical plane containing line A-A in Fig. 6A. In the cross-sectional view, two of the plurality of dummy gate stacks 30 are shown and the source / drain regions 42 formed between adjacent dummy gate stacks 30 are shown. More dummy gate stacks 30 and source / drain regions 42 may be formed in the alternate layout.

The dummy gate stacks 30 including the hard mask layers 36, the dummy gate electrodes 34 and the dummy gate dielectrics 32 are then deposited on the metal gates and / Lt; RTI ID = 0.0 > alternative gate < / RTI > The sectional views shown in Figs. 7 to 10 and subsequent Figs. 11 to 21 are obtained from the same vertical plane including the line A-A in Fig. 6A. 7 to 21, the level 22A of the upper surfaces of the STI regions 22 is shown, and the semiconductor pins 24 'are above the level 22A.

When replacing the gate stacks, the hardmask layers 36, dummy gate electrodes 34, and dummy gate dielectrics 32, as shown in FIGS. 6A and 6B, are formed in the first Thereby resulting in trenches / openings 48 as shown in FIG. Each step is shown as step 202 in the process flow shown in FIG. The top surfaces and sidewalls of the protruding semiconductor fins 24 'are exposed to the trenches 48.

Figure 8 illustrates the formation of gate spacers 50 in accordance with some embodiments. Each step is shown as step 204 in the process flow shown in FIG. According to alternative embodiments, gate spacers 50 are not formed. One or more blanket gate spacer layers are formed using a deposition method, such as ALD or CVD, to form the gate spacers 50. The blanket gate spacer layer is conformal. According to some embodiments of the present disclosure, the gate spacer layer may comprise silicon nitride (e.g., silicon nitride), which may be the same or different from the materials of the gate spacers 38 and one of the materials of the CESL 47 and the ILD 46 SiN), SiC, SiON, silicon oxy-carbon nitride, silicon oxynitride, or other dielectric materials. The gate spacers 50 separate the subsequently formed metal gates from the source / drain regions 42, reducing the likelihood of leakage therebetween and electrical shorting.

In some embodiments, the gate spacers 50 are formed of a low k dielectric material that may have a dielectric constant (k value) of less than about 3.0. By way of illustration, the k value of silicon oxide (SiO ₂ ), which is about 3.9, is used to distinguish the low k values from the high k values. Thus, a value of k lower than 3.8 is called the low k value, and the individual dielectric material is called the low k dielectric material. Conversely, k values higher than 3.9 are referred to as high k values, and individual dielectric materials are referred to as high k dielectric materials. For example, the gate spacers 50 may be formed of SiON or SiOCN that is formed porous to have a desired low k value. The formation of the low k dielectric spacers 50 preferably reduces the parasitic capacitance between the subsequently formed metal gates and the source / drain regions 42. For example, during the deposition of the blanket dielectric layer, a porogen can be added and an anneal is performed subsequent to the deposition to drive the void inducing material to create voids. The k value of SiOCN can also be adjusted by adjusting the percentage of elements (such as carbon) in the SiOCN. The blanket gate spacer layer is etched by anisotropic etching to remove the horizontal portions and the remaining vertical portions form the gate spacers 50.

Each gate spacer 50 may be formed of a single layer having a homogeneous dielectric material, or may be formed of a plurality of dielectric layers formed of different dielectric materials. For example, the gate spacer 50 may include a sub-spacer 50A and a sub-spacer 50B. The forming process includes depositing an conformal dielectric layer and performing an anisotropic etch to form the sub-spacers 50A, followed by depositing another conformal dielectric layer and another anisotropic etch to form the sub-spacers 50B. And performing the steps of:

In embodiments where the gate spacers 50 include sub spacers, one of the sub spacers 50A and 50B is formed of a low k dielectric material such as SiON or SiOCN (with pores) , The other sub-layer may be formed of a low k dielectric material, silicon oxide (not low k or high k) or a high k dielectric material. Silicon oxide or high k dielectric materials have good insulating capabilities. Thus, the isolation capability is good and the parasitic capacitance is low by one of the sub-layers formed of low k dielectric materials and another sub-layer formed of silicon oxide or high k dielectric material. According to some embodiments, the sub-spacers 50A and 50B are formed of the same material (such as SiON or SiOCN) but have different porosity. For example, the sub-spacers 50A may have a higher porosity than the sub-spacers 50B, or the sub-spacers 50B may have a higher porosity than the sub-spacers 50A.

Referring now to FIG. 9, a (alternate) gate dielectric layer 52 is formed that extends into the trenches 48 (FIG. 8). Each step is shown as step 206 in the process flow shown in FIG. According to some embodiments of the present disclosure, the gate dielectric layer 52 includes an IL (Interfacial Layer) 54 as its bottom portion. IL 54 is formed on the exposed surfaces of the projecting pins 24 '. The IL 54 may include an oxide layer, such as a silicon oxide layer, formed through thermal oxidation, a chemical oxidation process, or a deposition process of the protruding fins 24 '. The gate dielectric layer 52 may comprise a high k dielectric layer 56 formed over the IL 54. The high k dielectric layer 56 includes a high k dielectric material such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, silicon nitride, and the like. The dielectric constant (k value) of the high k dielectric material may be higher than 3.9 and higher than about 7.0. The high k dielectric layer 56 overlies the IL 54 and is in contact with the IL 54. The high k dielectric layer 56 is formed of an isotropic layer and extends over the sidewalls of the sidewalls and gate spacers 38/50 of the projecting fins 24 '. According to some embodiments of the present disclosure, the high k dielectric layer 56 is formed using ALD or CVD.

With further reference to FIG. 9, stacked layers 58 are deposited. Each step is shown as step 208 in the process flow shown in FIG. The sublayers in the stack layers 58 are not shown separately, but in fact the sublayers are distinguishable from one another. The film formation can be performed using a conformal film forming method such as ALD or CVD so that the thickness T1 of the vertical portions of the stack layers 58 and the thickness T2 of the horizontal portions are substantially equal to each other. Stack layers 58 extend to trenches 48 (FIG. 8) and include some portions over ILD 46.

Stack layers 58 may include a diffusion barrier layer and one (or more) work-function layer on the diffusion barrier layer. The diffusion barrier layer may be formed of TiN (titanium nitride) which may be doped (or undoped) with silicon. The work function layer determines the work function of the gate and comprises a plurality of layers formed of at least one layer or different materials. Depending on whether the individual FinFET is an n-type FinFET or a p-type FinFET, a material unique to the work function layer is selected. For example, when the FinFET is an n-type FinFET, the work function layer may comprise a TaN layer and a TiAl (titanium aluminum) layer on the TaN layer. When the FinFET is a p-type FinFET, the work function layer may comprise a TaN layer, a TiN layer on the TaN layer, and a TiAl layer on the TiN layer. After deposition of the work function layer (s), another barrier layer, which may be another TiN layer, is formed.

Subsequently, a metal material 60, which may be formed of, for example, tungsten or cobalt, is deposited. The metal material 60 completely fills the remaining trenches 48 (FIG. 8). In a subsequent step as shown in FIG. 10, a planarization step such as CMP or mechanical polishing is performed so that portions of layers 56, 58, and 60 on ILD 46 are removed. Each step is shown as step 210 in the process flow shown in FIG. Thus, metal gate electrodes 62 comprising the remaining portions of layers 58 and 60 are formed. The remaining portions of layers 52, 58, and 60 are hereinafter referred to as alternate gate stacks 64. At this time, the upper surfaces of the metal gate 62, spacers 38/52, CESL 47, and ILD 46 may be substantially coplanar, as shown in FIG. The thickness T3 of the ILD 46 and the CESL 47 may be in a range between about 15 nm and about 25 nm.

In Figure 10, the dotted lines 64/50 indicate that the gate spacers 50 and the alternate gate stacks 64 extend below the top surfaces of the illustrated semiconductor pins 24 ' Are shown aligned with the outer edges of the gate spacers 50 to indicate that they extend over the sidewalls of the gate spacers 50 '. The dotted lines indicate that these portions of gate spacers 50 and alternate gate stacks 64 are not in the plane shown. Also, although not shown, gate spacers 38 also extend to the sidewalls of the semiconductor fins 24 ', as shown in FIG.

Figs. 11-20 illustrate the formation of source / drain contact plugs and gate contact plugs. In the illustrated embodiment, three source / drain regions 42 are shown and the process shown shows only three source / drain contact plugs connected to the leftmost source / drain regions. In an actual process, there are also source / drain contact plugs that are configured to be connected to the center and rightmost source / drain regions 42. However, these source / drain contact plugs are formed in a different plane than shown and thus are not visible. Likewise, there may be a gate contact plug formed just above the left gate stack 64 that is in a different plane than shown and thus not shown.

Referring to Fig. 11, in accordance with some embodiments of the present disclosure, a dielectric mask 66 is formed. Between the planarization for forming the gate electrodes 62 and the formation of the dielectric mask 66, an etch-back for recessing the gate electrodes 62 is not performed. Dielectric layer 66 may be formed of a high k dielectric material having a k value higher than 3.9. According to some embodiments of the present disclosure, the dielectric mask 66 is formed of Al _x O _y , HfO ₂ , SiN, or SiOCN (without voids or substantially voids therein). The dielectric layer 66 may or may not be formed of the same material (such as SiOCN) as the gate spacers 50 that are more porous than the dielectric mask 660 to have a low k value. 66 may be in a range between about 2 nm and about 4 nm. The forming method may include PECVD, ALD, CVD, etc. Then, an ILD 68 is formed on the dielectric mask 66 ILD 68 has a k value that is higher than the k value of the low k dielectric material in gate spacers 50 and lower than the k value of contact spacers 82 (Figure 14) formed subsequently. The materials may be selected from the same candidate materials (and methods) for forming ILD 46 and ILD 68, and ILDs 46 and 68 may be formed of the same or different dielectric materials. a dielectric layer 68 may be formed using PECVD, may comprise silicon oxide (SiO ₂₎ A thickness (T4) of the dielectric layer 68 can be in the range of between about 700 Å and about 800 Å.

According to alternative embodiments of the present disclosure, a dielectric mask 66 is not formed and the ILD 68 is formed of lower alternate gate stacks 64, gate spacers 38/50, CESL 47, (46). Thus, the dielectric mask 66 is shown using dashed lines to indicate that it is selectively formed. Between the planarization for forming the gate electrodes 62 and the formation of the ILD 68, an etch-back for recessing the gate electrodes 62 is not performed.

A metal hard mask 70, which is then used as an etch mask in a subsequent etch, is formed over the ILD 68. The metal hard mask 70 may be formed of a metal nitride such as titanium nitride. A pad oxide layer 72, which may be formed of silicon oxide, is then formed over the hardmask layer 70. A photoresist 74, which forms an opening 76, is then applied and patterned.

The patterned photoresist 74 is then used to etch the lower pad oxide layer 72 and the metal hard mask 70 such that the openings 76 extend into the metal hard mask 70. The photoresist 74 is then removed, for example, in an ashing process. The ILD 68, the dielectric mask 66 (if present), the ILD 46, and the CESL 47 are then etched to form a source / drain contact opening 78, as shown in FIG. The remaining pad oxide layer 72 and the metal hard mask 70 are used as the etching mask. Each step is shown as step 212 in the process flow shown in FIG. During this etching process, the dielectric mask 66 (if formed) is not used as an etch stop layer. Thus, etching of ILD 68, dielectric mask 66, and ILD 46 with a single continuous etching process that uses an etching gas attacking both ILD 68, dielectric mask 66 and ILD 46 Can be performed. The CESL 47 may be used as an etch stop layer in the etching of the layers 68, 66, and 46. The etch process is then changed, e.g., using a different etch gas, and the exposed portions of the CESL 47 are etched to expose the underlying source / drain regions 42.

Referring to FIG. 13, a dielectric layer 80 is formed using a conformal deposition method, such as CVD or ALD, for example. The dielectric layer 80 may be a high k dielectric layer having a k value greater than 3.9 to have good isolation capabilities. Candidate materials include Al _x O _y , HfO ₂ , SiN, and SiOCN (with no voids or substantially no voids inside). The thickness of the dielectric layer 80 may be in the range between about 2 nm and about 4 nm.

Anisotropic etching is then performed so that the horizontal portions of the dielectric layer 80 are removed and the remaining vertical portions on the sidewalls of the opening 78 are removed from the contact spacers < RTI ID = 0.0 > 82 are formed. The structure thus obtained is shown in Fig. Each step is shown as step 214 in the process flow shown in FIG.

According to alternative embodiments of the present disclosure, instead of forming the contact spacers 82 in this stage, the contact spacers 82 may be formed simultaneously with the contact spacers 88 in the step shown in Fig. Thus, in Fig. 14, the contact spacers 82 are shown with dotted lines to indicate that they may or may not be formed at this time.

Referring to Fig. 15, a photoresist 84 is applied and patterned to form openings. The ILD 68 and the dielectric mask 66 are then etched to form a gate contact opening 86 extending below the opening and exposing the gate electrode 62. Each step is shown as step 216 in the process flow shown in FIG. The gate contact openings 86 can be sufficiently wide such that the gate spacers 38/50 are exposed. Gate contact openings 86 may be smaller than shown so that gate spacers 50/38 are not exposed. Then, the photoresist 84 is removed.

Then, according to some embodiments, (gate) contact spacers 88 are formed on the sidewalls of the openings 86, as shown in FIG. According to alternative embodiments, contact spacers 88 are not formed. The contact spacers 88 may not be formed when the contact spacers 82 have already been formed in the previous steps. If the contact spacers 82 are not formed in the previous steps, the contact spacers 82 and 88 are formed simultaneously in the step shown in Fig. A contact spacer 88 may be formed of a high-k dielectric material, which may be selected from the same group of candidate materials for forming contact spacers 82 (and corresponding dielectric layer 80). Thus, the contact spacers 88 are shown with dotted lines to indicate that they may or may not be formed, and the contact spacers 82 are shown in solid lines to indicate that they are formed. According to alternative embodiments, a contact opening 86 is formed before the formation of the contact opening 78, thereby forming a contact spacer 88, and the contact spacer 82 is selectively formed.

Referring to FIG. 17, a metal layer 90 (such as a titanium layer or a cobalt layer) is formed using PVD, for example. A barrier layer 92, which may be a metal nitride layer, such as a titanium nitride layer or a tantalum nitride layer, is then formed over the metal layer 90. Each step is shown as step 218 in the process flow shown in FIG. The barrier layer 92 may be formed using CVD. The layers 90 and 92 are all conformal and extend into the openings 78 and 86.

Annealing is then performed to form the source / drain silicide regions 94 as shown in FIG. Each step is shown as step 220 in the process flow shown in FIG. The annealing may be performed by RTA (Rapid Thermal Anneal), furnace anneal, or the like. Thus, the lower portion of the metal layer 90 reacts with the source / drain regions 42 to form the silicide regions 94. [ The sidewall portions of the metal layer 90 remain after the silicidation process. According to some embodiments of the present disclosure, the upper surface of the silicide region 94 contacts the lower surface of the barrier layer 92.

19, a metal material 96 is deposited over the barrier layer 92 to contact the barrier layer 92. Each step is shown as step 222 in the process flow shown in FIG. The metal material 96 may be selected from the same group of candidate materials of the metal-containing material 60 and may comprise tungsten or cobalt. A planarization step such as CMP or mechanical polishing is then performed so that portions of layers 90, 92, and 96 on ILD 68 are removed. The resulting structure including the source / drain contact plug 98 and the gate contact plug 102 is shown in FIG.

Figure 21 shows the source / drain contact plugs (vias) 108 in the etch stop layer 103, the dielectric layer 104, the gate contact plug (via) 106 and the etch stop layer 103 and dielectric layer 104 ). ≪ / RTI > The etch stop layer 103 may be formed of silicon carbide, silicon oxynitride, silicon carbon nitride, or the like, and may be formed using a deposition method such as CVD. The dielectric layer 104 may comprise a material selected from PSG, BSG, BPSG, Fuorine-doped Silicon Glass (FSG), TEOS oxide, or PECVD oxide (SiO ₂ ). The dielectric layer 104 may be formed using spin coating, FCVD, or a deposition method such as PECVD or LPCVD (Low Pressure Chemical Vapor Deposition).

Dielectric layer 104 and etch stop layer 103 are etched to form openings (occupied by plugs / vias 106 and 108). For example, the etching may be performed using RIE (Reactive Ion Etch). In a subsequent step, plugs / vias 106 and 108 are formed. According to some embodiments of the present disclosure, the plugs / vias 106 and 108 include a barrier layer 110 and a metal-containing material 112 on the barrier layer. According to some embodiments of the present disclosure, the formation of the plugs / vias 106 and 108 may include etching the layers 103 and 104 to form contact openings, etching the blanket barrier layer 90 and the blanket barrier < RTI ID = 0.0 > Forming a metal-containing material on the layer, and performing planarization to remove excess portions of the blanket barrier layer and the metal-containing material. The barrier layer 110 may be formed of a metal nitride such as titanium nitride or tantalum nitride. The material, structure, and formation methods of the metal-containing material 112 can be selected from the respective candidate materials, candidate structures, and candidate formation methods of the metal-containing material 60, Lt; / RTI >

In the structure obtained, the source regions in the source / drain regions 42 can be electrically interconnected, and the drain regions in the source / drain regions 42 are electrically connected to each other such that the resulting structure forms a FinFET 100 And gate electrodes 64 may be interconnected via contact plugs and upper plugs / vias, metal lines (not shown).

Embodiments of the present invention have several beneficial features. After formation of the metal gate electrode 62, the metal gate electrode is not etched back and a hard mask is not formed in the resulting recess. Thus, the cost for etching-back and forming the hard mask is saved. Since the etching back is not necessary, the height of the metal gate is also reduced. Thus, the aspect ratio of the opening for filling the metal gate is reduced, and the filling of the metal gate becomes easier. The formation of the high-k contact spacers 82/88 and the high-k dielectric mask 66 improves the isolation between the metal gate and the adjacent source / drain contact plugs. The formation of the low k gate spacers improves the isolation between the metal gate and the source / drain regions without causing an increase in parasitic capacitance.

According to some embodiments of the present disclosure, a method includes forming a transistor, wherein forming the transistor comprises: forming a source / drain region on a side of the dummy gate; Forming a first ILD covering the source / drain regions; Removing the dummy gate to form a trench in the first ILD; Forming a gate dielectric layer extending into the trench; Forming a metal material over the gate dielectric layer; And performing planarization to form gate dielectric and metal gate, respectively, by removing the gate dielectric layer and excess portions of the metal material. The method further includes forming a second ILD over the metal gate and a first ILD. When the second ILD is formed, the top surface of the metal gate is coplanar with the top surface of the first ILD. The method includes forming a source / drain contact plug electrically connected to a source / drain region and through both the first ILD and the second ILD; And forming a gate contact plug in contact with the metal gate over the metal gate.

According to some embodiments of the present disclosure, a method includes forming a transistor including forming a dummy gate stack over a semiconductor region and forming an ILD. The dummy gate stack is in the ILD, and the ILD covers the source / drain regions in the semiconductor region. The method includes removing a dummy gate stack to form a trench in the first ILD; Forming a low k gate spacer in the trench; Forming a replacement gate dielectric that extends into the trench; Forming a metal layer to fill the trench; And performing planarization to remove excess gate dielectric and excess portions of the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

According to some embodiments of the present disclosure, a device includes a first ILD, a first gate spacer in a first ILD, a gate dielectric in an opening disposed between opposing portions of the first gate spacer, and a metal gate . The top surface of the metal gate, the top end of the first gate spacer, and the top surface of the first ILD are in contact with the bottom surface of the same top dielectric layer. The device further includes a second ILD over the first ILD, a source / drain region adjacent the metal gate, and a source / drain contact plug electrically connected to the source / drain region over the source / drain region. The source / drain contact plugs pass through both the first ILD and the second ILD. The contact spacer surrounds the small / drain contact plug.

According to an embodiment of the present disclosure, there is provided a method of forming a transistor, comprising: forming a source / drain region on a side of a dummy gate; Forming a first ILD (Inter-Layer Dielectric) covering the source / drain regions; Removing the dummy gate to form a trench in the first ILD; Forming a gate dielectric layer extending into the trench; Forming a metal material over the gate dielectric layer; And performing planarization to form gate dielectric and metal gate, respectively, by removing the gate dielectric layer and excess portions of the metal material. Forming a second ILD over the first ILD and the metal gate such that when the second ILD is formed the upper surface of the metal gate and the upper surface of the first ILD are in contact with the lower surface of the same upper dielectric layer Gt; ILD < / RTI > Forming a source / drain contact plug electrically connected to the source / drain region and through both the first ILD and the second ILD; And forming a gate contact plug in contact with the metal gate over the metal gate.

The method according to an embodiment of the present disclosure further comprises forming gate spacers in the trench before the gate dielectric layer is formed.

In the method according to embodiments of the present disclosure, forming the gate spacers includes forming low k dielectric spacers.

In the method according to an embodiment of the present disclosure, the second ILD contacts the first ILD on the first ILD.

The method according to an embodiment of the present disclosure further comprises forming a dielectric mask in contact with the metal gate and the first ILD, the second ILD being in contact with the dielectric mask on the dielectric mask.

In the method according to an embodiment of the present disclosure, the step of forming the source / drain contact plug may include forming the source / drain contact plug using the same etchant to form the source / drain contact opening, Etching the first ILD; Depositing a metal layer having a portion extending into the source / drain contact opening; Depositing a metal nitride barrier layer over the metal layer; Performing an anneal to react the metal layer with the source / drain regions and to form a silicide region; And performing planarization to remove excess portions of the metal layer and the metal nitride barrier layer.

The method according to an embodiment of the present disclosure, wherein forming the source / drain contact plug comprises: etching the second ILD and the first ILD to form a source / drain contact opening; Forming contact spacers in the source / drain contact openings; And filling the source / drain contact openings with a metal material to form the source / drain contact plugs, the contact spacers surrounding the source / drain contact plugs.

In the method according to embodiments of the present disclosure, the step of forming the contact spacers comprises forming a high-k dielectric spacer.

In the method according to embodiments of the present disclosure, the step of forming the dielectric mask includes forming a high-k dielectric layer.

According to another aspect of the present disclosure, there is provided a method of forming a transistor, comprising: forming a dummy gate stack over a semiconductor region; Forming a first ILD, wherein the dummy gate stack is in the first ILD and the first ILD covers a source / drain region in the semiconductor region; Removing the dummy gate stack to form a trench in the first ILD; Forming a low k gate spacer in the trench; Forming a replacement gate dielectric that extends into the trench; Forming a metal layer to fill the trench; And removing the alternate gate dielectric and excess portions of the metal layer to perform planarization to form a gate dielectric and a metal gate, respectively; And forming a source region and a drain region, said source region and said drain region being on opposite sides of said metal gate.

The method according to another embodiment of the present disclosure further comprises forming additional gate spacers that are in contact with the sidewalls of the dummy gate stack before the dummy gate stack is removed and before the first ILD is formed, The low k gate spacer has a sidewall contacting the sidewall of the additional gate spacer.

In another embodiment of the present disclosure, the low k gate spacer comprises a porous dielectric material.

A method according to another embodiment of the present disclosure includes providing a high k dielectric mask in contact with the metal gate, the low k gate spacer, and the first ILD on the metal gate, the low k gate spacer, and the first ILD ; And forming a second ILD in contact with the high k dielectric mask on the high k dielectric mask.

In a method according to another embodiment of the present disclosure, the low k gate spacers and the high k dielectric mask are formed of the same dielectric, and the low k gate spacers are more porous than the high k dielectric mask.

A method according to another embodiment of the present disclosure further comprises forming a high-k contact spacer with a source / drain contact plug through the first ILD, wherein the high-k contact spacer comprises a source / drain contact plug Enclose.

According to still another embodiment of the present disclosure, there is provided a liquid crystal display comprising: a first ILD (Inter-Layer Dielectric); A first gate spacer in the first ILD; A gate dielectric in an opening disposed between opposing portions of the first gate spacer; A metal gate over the gate dielectric, the upper surface of the metal gate, the upper surface of the first gate spacer, and the upper surface of the first ILD being in contact with a lower surface of the same dielectric layer; A second ILD on the first ILD; A source / drain region adjacent said metal gate; A source / drain contact plug electrically connected to the source / drain region on the source / drain region and through both the first ILD and the second ILD; And a contact spacer surrounding the source / drain contact plug.

In a device according to another embodiment of the present disclosure, the contact spacers are formed of a high k dielectric material.

In a device according to another embodiment of the present disclosure, the second ILD contacts the first ILD, the device further comprises a gate contact plug in the second ILD, and the lower surface of the second ILD And is substantially flush with the lower surface of the gate contact plug.

A device according to yet another embodiment of the present disclosure further comprises a high k dielectric mask in contact with the first ILD and the second ILD between the first ILD and the second ILD, Also penetrates the high k dielectric mask.

A device according to yet another embodiment of the present disclosure further comprises a second gate spacer in contact with the gate dielectric and the first gate spacer between the gate dielectric and the first gate spacer and comprising a low k dielectric material .

The foregoing is a summary of features of several embodiments to enable those skilled in the art to better understand aspects of the disclosure. It should be appreciated by those of ordinary skill in the art that the present disclosure can readily be used as a basis for designing or modifying other processes and structures for performing the same purposes of the disclosed embodiments and / or achieving the same advantages . It should also be realized by those skilled in the art that various changes, substitutions, and alterations may be made without departing from the spirit and scope of the disclosure and without departing from the spirit and scope of the disclosure.

Claims (10)

In the method,
Forming a transistor,
Forming a source / drain region on a side of the dummy gate;
Forming a first ILD (Inter-Layer Dielectric) covering the source / drain regions;
Removing the dummy gate to form a trench in the first ILD;
Forming a gate dielectric layer extending into the trench;
Forming a metal material over the gate dielectric layer; And
Performing planarization to remove the gate dielectric layer and excess portions of the metal material to form a gate dielectric and a metal gate, respectively
Forming the transistor;
Forming a second ILD over the first ILD and the metal gate such that when the second ILD is formed the upper surface of the metal gate and the upper surface of the first ILD are in contact with the lower surface of the same upper dielectric layer Gt; ILD < / RTI >
Forming a source / drain contact plug electrically connected to the source / drain region and through both the first ILD and the second ILD; And
Forming a gate contact plug in contact with the metal gate over the metal gate
/ RTI > The method according to claim 1,
Further comprising forming gate spacers in the trench before the gate dielectric layer is formed. 3. The method of claim 2,
Wherein forming the gate spacers comprises forming low k dielectric spacers. The method according to claim 1,
Further comprising: forming a dielectric mask in contact with the metal gate and the first ILD, the second ILD contacting the dielectric mask on the dielectric mask. 5. The method of claim 4,
Wherein forming the source / drain contact plug comprises:
Etching the second ILD, the dielectric mask, and the first ILD using the same etchant to form a source / drain contact opening;
Depositing a metal layer having a portion extending into the source / drain contact opening;
Depositing a metal nitride barrier layer over the metal layer;
Performing an anneal to react the metal layer with the source / drain regions and to form a silicide region; And
Performing planarization to remove excess portions of the metal layer and the metal nitride barrier layer
≪ / RTI > 5. The method of claim 4,
Wherein forming the source / drain contact plug comprises:
Etching the second ILD and the first ILD to form a source / drain contact opening;
Forming contact spacers in the source / drain contact openings; And
Filling the source / drain contact opening with a metal material to form the source / drain contact plug
Lt; / RTI >
Wherein the contact spacers surround the source / drain contact plug. The method according to claim 6,
Wherein forming the contact spacers comprises forming high k dielectric spacers. 5. The method of claim 4,
Wherein forming the dielectric mask comprises forming a high-k dielectric layer. In the method,
Forming a transistor,
Forming a dummy gate stack over the semiconductor region;
Forming a first ILD, wherein the dummy gate stack is in the first ILD and the first ILD covers a source / drain region in the semiconductor region;
Removing the dummy gate stack to form a trench in the first ILD;
Forming a low k gate spacer in the trench;
Forming a replacement gate dielectric that extends into the trench;
Forming a metal layer to fill the trench; And
Performing planarization to remove the alternate gate dielectric and excess portions of the metal layer to form a gate dielectric and a metal gate, respectively
Forming the transistor; And
Forming a source region and a drain region, said source region and said drain region being on opposite sides of said metal gate;
/ RTI > In a device,
A first ILD (Inter-Layer Dielectric);
A first gate spacer in the first ILD;
A gate dielectric in an opening disposed between opposing portions of the first gate spacer;
A metal gate over the gate dielectric, the upper surface of the metal gate, the upper surface of the first gate spacer, and the upper surface of the first ILD being in contact with a lower surface of the same dielectric layer;
A second ILD on the first ILD;
A source / drain region adjacent said metal gate;
A source / drain contact plug electrically connected to the source / drain region on the source / drain region and through both the first ILD and the second ILD; And
A contact spacer surrounding the source / drain contact plug;
.

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