KR20180052902A - Apparatus for testing semiconductor devices - Google Patents

Abstract

Disclosed is a test apparatus to test electric characteristics of semiconductor devices. According to the present invention, the test apparatus comprises: an insert including a pocket in which a semiconductor device is received and having an opening part formed in a bottom part of the pocket; a test socket including a plurality of connection terminals to electrically connect the semiconductor device with the test apparatus; and an interposer including a plurality of align holes into which access terminals of the semiconductor device and the connection terminals are inserted to align the access terminals and the connection terminals, and arranged between the insert and the test socket. As such, unlike a conventional support film aligning only access terminals of a semiconductor device, the interposer aligns the access terminals together with the connection terminals of the test socket, thereby providing effects capable of also correctly aligning a semiconductor device with a fine pitch, and stably connecting between the access terminals and the connection terminals.

Description

[0001] Apparatus for testing semiconductor devices [

Embodiments of the present invention relate to a semiconductor device testing apparatus for testing semiconductor devices. More particularly, the present invention relates to a semiconductor device test apparatus for providing inspection signals to semiconductor devices to inspect electrical characteristics of the semiconductor devices.

Generally, semiconductor devices can be formed on a silicon wafer used as a semiconductor substrate by repeatedly performing a series of manufacturing processes, and the semiconductor devices thus formed can be manufactured into finished products through a dicing process, a bonding process, and a packaging process .

These semiconductor devices can be judged as good or defective through electrical characteristic inspection. A semiconductor device test apparatus including a test handler for handling semiconductor devices and a tester for testing semiconductor devices may be used for the electrical property test.

The test handler may include a test tray having a plurality of inserts, an interface module for electrically connecting the semiconductor elements and the tester, and a match plate for connecting the semiconductor elements and the interface module to each other.

The insert may include a pocket in which the semiconductor element is housed, and latches to prevent the semiconductor element from escaping. As an example, Korean Patent Registration No. 10-1535245 discloses an insert assembly comprising an insert body having an opening into which a semiconductor device is inserted, and a film-like support member attached to a lower portion of the insert body, . In particular, the support member may have a plurality of guide holes into which connection terminals of semiconductor elements are inserted.

The interface module may include a plurality of test sockets electrically connected to the semiconductor devices. The test socket has connection terminals such as pogo pins or probe pins for contact with external connection terminals of the semiconductor device, for example, solder balls.

The electrical characteristic inspection process is as follows. First, a semiconductor device is housed in an insert, and then a test socket is connected to a semiconductor device accommodated in the insert to electrically connect the semiconductor device and the tester. Next, an inspection signal is applied to the semiconductor element from the tester, and the semiconductor element outputs a signal corresponding to the inspection signal. The tester judges whether the output signal of the semiconductor element is a normal signal or an error signal and judges the semiconductor element as good or defective.

Particularly, in the inspection of the electrical characteristics of the semiconductor devices, if the alignment between the solder balls of the semiconductor device and the connection terminals of the test socket is not normally performed, the electrical connection between the semiconductor device and the tester is not stable, The property check is not performed properly.

In order to prevent such defects, a semiconductor device test apparatus has a support film for aligning solder balls and connection terminals. The support film has a plurality of guide holes into which the solder balls are inserted and is disposed between the insert and the test socket.

On the other hand, as the size of the solder balls of the semiconductor device gradually decreases and the interval between the solder balls gradually decreases, alignment between the solder balls of the semiconductor device and the connection terminals of the test socket becomes very difficult. This may cause defects that the solder balls of the semiconductor element are caught in the guide holes of the support film. It is difficult to correct alignment errors over a certain range, and the support film may be deformed by the physical force.

(001) Korea Patent No. 10-1350606 (2014.01.06)

It is an object of the present invention to provide a semiconductor device test apparatus capable of aligning a semiconductor device and a test socket together.

According to an aspect of the present invention, there is provided an apparatus for testing a semiconductor device, the apparatus comprising: an insert having pockets for receiving semiconductor elements therein and having openings formed in bottom portions of the pockets; And a plurality of alignment holes into which the connection terminals and the connection terminals are inserted to align the connection terminals of the semiconductor device with the connection terminals, And an interposer disposed between the test sockets.

According to embodiments of the present invention, the connection terminals may be provided in a one-to-one correspondence with the connection terminals. In addition, the connection terminal and the corresponding connection terminal are inserted together in the alignment hole, and corresponding connection terminals are disposed under the connection terminal, and the connection terminal and the corresponding connection terminal are formed in the alignment hole They can be connected to each other.

According to embodiments of the present invention, the alignment holes may be provided in a one-to-one correspondence with the connection terminals.

According to embodiments of the present invention, the alignment hole may have a radius smaller than the diameter of the connection terminal and larger than the radius of the connection terminal for aligning the connection terminal inserted in the alignment hole and the corresponding connection terminal Lt; / RTI >

According to embodiments of the present invention, the connection terminal may be a pogo pin.

According to embodiments of the present invention, the inlet portion into which the connection terminals are inserted and the inlet portion into which the connection terminals are inserted may be filled or chamfered.

According to the embodiments of the present invention as described above, a test apparatus for inspecting electrical characteristics of semiconductor devices includes an IC chip having a plurality of alignment holes for inserting connection terminals of a semiconductor device and connection terminals of a test socket, And an interposer aligns the connection terminals and the connection terminals. In particular, since the interposer can align the connection terminals of the connection terminals and the test socket together, unlike the conventional support film which aligns only the connection terminals of the semiconductor element, the semiconductor element having the fine pitch can also be accurately aligned, And the connection terminals can be stably connected.

Further, the semiconductor device testing apparatus can prevent the connection terminals from being pinched due to the use of the conventional support film.

Further, since the connection terminals of the semiconductor element can be self-aligned by the alignment holes of the interposer, the semiconductor element testing apparatus can improve the alignment accuracy between the semiconductor element and the test socket. As a result, since the electrical connection between the semiconductor element and the tester can be stably performed, the inspection reliability of the semiconductor element testing apparatus can be improved.

Moreover, since the interposer is less deformed due to the physical force than the conventional support film, the connection terminals of the semiconductor element and the connection terminals of the test socket can be stably aligned.

1 is a schematic exploded cross-sectional view illustrating a semiconductor device testing apparatus according to an embodiment of the present invention.
2 is a schematic plan view for explaining the interposer shown in Fig.
3 is a schematic partial cross-sectional view for explaining the arrangement relationship between the semiconductor element shown in FIG. 1, the interposer and the test socket.
4 is a partially enlarged sectional view for explaining a process of aligning the connection terminals of the semiconductor device and the connection terminals of the test socket by the interposer shown in FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described in more detail below with reference to the accompanying drawings showing embodiments of the invention. However, the present invention should not be construed as limited to the embodiments described below, but may be embodied in various other forms. The following examples are provided so that those skilled in the art can fully understand the scope of the present invention, rather than being provided so as to enable the present invention to be fully completed.

When an element is described as being placed on or connected to another element or layer, the element may be directly disposed or connected to the other element, and other elements or layers may be placed therebetween It is possible. Alternatively, if one element is described as being placed directly on or connected to another element, there can be no other element between them. The terms first, second, third, etc. may be used to describe various items such as various elements, compositions, regions, layers and / or portions, but the items are not limited by these terms .

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Furthermore, all terms including technical and scientific terms have the same meaning as will be understood by those skilled in the art having ordinary skill in the art, unless otherwise specified. These terms, such as those defined in conventional dictionaries, shall be construed to have meanings consistent with their meanings in the context of the related art and the description of the present invention, and are to be interpreted as being ideally or externally grossly intuitive It will not be interpreted.

Embodiments of the present invention are described with reference to schematic illustrations of ideal embodiments of the present invention. Accordingly, changes from the shapes of the illustrations, e.g., changes in manufacturing methods and / or tolerances, are those that can be reasonably expected. Accordingly, the embodiments of the present invention should not be construed as being limited to the specific shapes of the areas illustrated in the drawings, but include deviations in shapes, the areas described in the drawings being entirely schematic and their shapes Is not intended to illustrate the exact shape of the area and is not intended to limit the scope of the invention.

1 is a schematic exploded cross-sectional view illustrating a semiconductor device testing apparatus according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor device testing apparatus 100 according to an embodiment of the present invention may be used to examine the electrical characteristics of the semiconductor device 10. For example, the semiconductor device testing apparatus 100 may provide an inspection signal to the semiconductor device 10 and analyze the signal output from the semiconductor device 10 in response to the inspection signal, The electrical performance of the device is checked.

The semiconductor device testing apparatus 100 includes an insert 110 in which the semiconductor device 10 is accommodated, a tester (not shown) disposed below the insert 110 and providing the inspection signal, A test socket 120 for electrically connecting the semiconductor device 10 and the test socket 120 and an interposer 120 disposed between the insert 110 and the test socket 120 for aligning the semiconductor device 10 and the test socket 120. [ (130).

Although not shown in the drawing, the semiconductor device testing apparatus 100 includes a test tray (not shown) provided with a plurality of inserts 110 and a test chamber (not shown) providing a space for performing an electrical characteristic test on the semiconductor devices Not shown). The semiconductor device testing apparatus 100 further includes a plurality of transfer modules (not shown) for transferring the semiconductor elements from the customer tray (not shown) to the test tray and transferring the test tray accommodated therein to the test chamber Time). The transfer modules take out the test tray from the test chamber after the inspection process is completed in the test chamber, and transfer the semiconductor devices stored in the test tray to an empty customer tray. The semiconductor device testing apparatus 100 may further include a preheating chamber (not shown) for adjusting the temperature of the semiconductor device 10 in advance and a heat generating chamber (not shown) for recovering the temperature of the semiconductor device 10 to room temperature ).

Specifically, the semiconductor element 10 transferred from the customer tray may be received in the insert 110. The insert 110 has a pocket 112 in which the semiconductor device 10 is housed and the semiconductor device 10 and the test socket 120 are connected to each other on the bottom surface of the pocket 112, An opening is formed as much as possible. Here, the opening may be opened or closed by the semiconductor element 10.

Although not shown in detail in the drawing, latches (not shown) for fixing the semiconductor device 10 may be provided in the pockets 112 of the insert 110. The latches press the upper surface edge portion of the semiconductor element 10 to fix the position of the semiconductor element 10.

The test socket 120 may be disposed below the insert 110. The test socket 120 is disposed to face the semiconductor device 10 and includes a plurality of connection terminals 122 for electrically connecting to the semiconductor device 10. The semiconductor device 10 may have a plurality of connection terminals 12 to be connected to the connection terminals 122 of the test socket 120. The connection terminals 12 and the connection terminals 122 may be provided in a one-to-one correspondence with each other. Here, the connection terminals 12 may include solder balls 12, and the connection terminals 122 may include pogo pins.

The interposer 130 may be disposed between the semiconductor element 10 and the test socket 120 housed in the insert 110. Particularly, the interposer 130 guides the positions of the connection terminals 12 and the connection terminals 122 of the semiconductor device 10, and the connection terminals 12 and the connection terminals 122 May be in electrical contact with each other within the interposer 130. [

FIG. 2 is a schematic plan view for explaining the interposer shown in FIG. 1, and FIG. 3 is a schematic partial cross-sectional view for explaining the arrangement relationship of the semiconductor element, the interposer and the test socket shown in FIG.

2 and 3, the interposer 130 includes a base substrate 132, connection terminals 12 of the semiconductor device 10, connection terminals 122 of the test socket 120, And a plurality of alignment holes 134 for aligning the plurality of alignment holes.

Specifically, the base substrate 132 is disposed between the semiconductor device 10 and the test socket 120, and may be disposed to face the semiconductor device 10 and the test socket 120.

The alignment holes 134 may be formed in the base substrate 132 and the alignment holes 134 may be formed through the base substrate 132 as shown in FIG.

In one embodiment of the present invention, the alignment holes 134 may be provided in a one-to-one correspondence with the connection terminals 12.

The connection terminals 12 and the connection terminals 122 may be inserted into the alignment holes 134 and aligned by the alignment holes 134. That is, the connection terminals 12 and the connection terminals 122 corresponding to one another among the connection terminals 12 and the connection terminals 122 may be inserted into the single alignment hole 134. At this time, the connection terminal 12 is inserted through the upper inlet of the alignment hole 134, and the connection terminal 122 is inserted through the lower inlet of the alignment hole 134. As shown in FIG. 3, the connection terminals 12 and the connection terminals 122, which are inserted into the alignment holes 134, can be electrically connected to each other in the alignment holes 134.

Particularly, the alignment hole 134 has a diameter PD of the connection terminal 122 for aligning the connection terminal 122 inserted in the alignment hole 134 and the corresponding connection terminal 12, And has a radius (HR) that is larger than the radius (SR) of the connection terminal (12). Even if the center lines of the connection terminal 12 and the connection terminal 122 inserted in the alignment hole 134 are arranged to be shifted from each other, And the alignment error between the center lines can be minimized.

Hereinafter, a process of aligning the connection terminals 12 and the connection terminals 122 will be described in detail with reference to the drawings.

4 is a partially enlarged sectional view for explaining a process of aligning the connection terminals of the semiconductor device and the connection terminals of the test socket by the interposer shown in FIG.

4, the insert 110 may have a predetermined angle of inclination of the inner sides of the pocket 112 to self-align the position of the semiconductor device 10 within the pocket 12. [ In other words, the inner surfaces of the pocket 112 may have inclined sides 114 whose width gradually decreases downward to guide the semiconductor device 10 directly above the interposer 130. The semiconductor device 10 can be guided downwardly by the inclined sides 114 of the pocket 112 in the course of being dropped into the pocket 112 by the pick up device, The connection terminals 12 of the semiconductor device 10 can be inserted into the alignment holes 134 of the interposer 130 disposed below.

The inclination angle of the inclined side surfaces 114 may be set within a range in which contact between the edge portions of the semiconductor element 10 and the inclined side surfaces 114 is prevented. This is because the degree of integration of the semiconductor element 10 is increased and the distance between the side surfaces of the semiconductor element 10 and the outermost connection terminals 12 of the connection terminals 12 becomes very narrow, 12 because the tolerance for the gap between the side surfaces of the semiconductor element 10 and the outermost connection terminals is relatively large.

That is, when the contact between the edge portions of the semiconductor element 10 and the inclined side surfaces 114 is allowed, the edge portions of the semiconductor element 10 are placed on the inclined side surfaces 114 So that the connection terminals 12 of the semiconductor device 10 may not be inserted into the alignment holes 134.

In order to solve such a problem, the inclination angle of the inclined side surfaces 114 of the pocket 112 is set within a range that can prevent the contact between the edge portions of the semiconductor element 10 and the inclined side surfaces 114 .

4, the alignment holes 134 may have an inlet portion 34A into which the connection terminals 12 are inserted and an inlet portion 34B into which the connection terminals 122 are inserted Fillet or chamfered. Accordingly, the connection terminals 12 and the connection terminals 122 can be inserted into the alignment holes 134 more easily. For example, as shown in FIG. 4, even if the connection terminals 12 are seated on the upper surface of the interposer 130, the inlet portion 34A of the fillet or chamfered alignment holes 134 ) Into the alignment holes (134).

1 and 3, the semiconductor device testing apparatus 100 further includes a pusher 140 for closely contacting the semiconductor element 10 in the pocket 112 to the interposer 130 side .

The pusher 140 is disposed on the upper side of the insert 10 and is inserted into the pocket 112 in a state in which the semiconductor element 10 is aligned with the interposer 130 and the test socket 120, And presses the semiconductor element 10 toward the interposer 130 side. The connection terminals 12 inserted into the alignment holes 134 and the connection terminals 122 are brought into close contact with each other so that the semiconductor element 10 and the test socket 120 can be stably conducted .

As described above, the semiconductor device testing apparatus 100 includes the interposer 130 having a plurality of alignment holes 134 for inserting the connection terminals 12 and the connection terminals 122 Respectively. Particularly, the interposer 130 aligns the connection terminals 12 of the test socket 120 with the connection terminals 12, unlike the conventional support film which aligns only the connection terminals 12 The semiconductor device having a fine pitch can be accurately aligned and the connection terminals 12 and the connection terminals 122 can be stably connected.

Also, the semiconductor device testing apparatus 100 can prevent the connection terminals 12 from being pinched due to the use of the conventional support film.

Since the connection terminals 12 of the semiconductor device 10 can be self-aligned by the alignment holes 134 of the interposer 130, The alignment accuracy between the device 10 and the test socket 120 can be improved. As a result, since the electrical connection between the semiconductor device 10 and the tester can be stably performed, the inspection reliability of the semiconductor device testing apparatus 100 can be improved.

The connection terminals 12 of the semiconductor device 10 and the connection terminals 122 of the test socket 120 are connected to each other via the interposer 130, ) Can be stably aligned.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

10: Semiconductor device 12: Connection terminal
100: semiconductor device test apparatus 110: insert
112: pocket 114: oblique side
120: test socket 122: connection terminal
130: interposer 132: base substrate
134: alignment hole 140: pusher

Claims (6)

An insert having a pocket in which a semiconductor element is received and an opening formed in a bottom portion of the pocket;
A test socket having a plurality of connection terminals for electrically connecting the semiconductor device and the test apparatus; And
And an interposer having a plurality of alignment holes into which the connection terminals and the connection terminals are inserted to align the connection terminals and the connection terminals of the semiconductor device and disposed between the insert and the test socket Wherein the semiconductor device is a semiconductor device. The method according to claim 1,
The connection terminals are provided in a one-to-one correspondence with the connection terminals,
The connection terminal and the corresponding connection terminal are inserted together in the alignment hole, and corresponding connection terminals are disposed under the connection terminal,
Wherein the connection terminal and the corresponding connection terminal are electrically connected to each other in the alignment hole. 3. The method of claim 2,
Wherein the alignment holes are provided in a one-to-one correspondence with the connection terminals. The method of claim 3,
Wherein the alignment hole has a radius smaller than a diameter of the connection terminal and larger than a radius of the connection terminal for aligning the connection terminal inserted in the alignment hole and the corresponding connection terminal. . 5. The method of claim 4,
Wherein the connection terminal is a pogo pin. 3. The method of claim 2,
Wherein the inlet portion into which the connection terminals are inserted and the inlet portion into which the connection terminals are inserted are filled or chamfered.

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