KR20170133974A - Light emitting diode - Google Patents

Abstract

According to embodiments of the present invention, the present invention relates to a light emitting diode, which comprises: a first conductive semiconductor layer; a mesa including a second conductive semiconductor layer disposed on the first conductive semiconductor layer, and an active layer interposed between the second and first conductive semiconductor layers; a first contact layer including an external contact portion being in contact with the first conductive semiconductor layer at a place adjacent to an edge of the first conductive semiconductor layer along the circumference of the mesa, and an internal contact portion being in contact with the first conductive semiconductor layer within a region surrounded by the external contact portion; a second contact layer disposed on the mesa, and being in contact with the second conductive semiconductor layer; and a first insulating layer for covering the first conductive semiconductor layer and the mesa, and insulating the first contact layer from the mesa and the second contact layer. The first insulating layer exposes the first conductive semiconductor layer to allow the external and internal contact portions to be in contact with the first conductive semiconductor layer. The external contact portion and the first insulating layer are in contact with the first conductive semiconductor layer along a side surface of the mesa, alternatively.

Description

[0001] LIGHT EMITTING DIODE [0002]

The present invention relates to a light emitting diode, and more particularly, to a light emitting diode in the form of a chip scale package.

In general, nitrides of a Group III element such as gallium nitride (GaN) and aluminum nitride (AlN) have excellent thermal stability and have a direct bandgap energy band structure. Recently, nitride materials for visible light and ultraviolet Has received a lot of attention. In particular, blue and green light emitting diodes using indium gallium nitride (InGaN) are utilized in various applications such as large-scale color flat panel displays, traffic lights, indoor lighting, high density light sources, high resolution output systems and optical communication.

2. Description of the Related Art In recent years, light emitting diodes are being studied in the form of a chip scale package in which a packaging process is performed at a chip level. Such a light emitting diode is smaller in size than a general package and does not require a separate packaging work, which can further simplify the process and save time and money.

The light emitting diode in the form of a chip scale package generally has a flip chip electrode structure, and thus has excellent heat dissipation characteristics.

However, researches on such light emitting diodes are still in progress, and in particular, efforts are needed to increase the light extraction efficiency and evenly disperse light emitting regions.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a chip scale package type light emitting diode with improved light extraction efficiency.

Another object of the present invention is to provide a light emitting diode in which a light emitting region is evenly dispersed.

According to embodiments of the present invention, the first conductive semiconductor layer; A second conductivity type semiconductor layer disposed on the first conductivity type semiconductor layer, and an active layer interposed between the second conductivity type semiconductor layer and the first conductivity type semiconductor layer; An external contact portion contacting the first conductivity type semiconductor layer near the edge of the first conductivity type semiconductor layer along the mesa periphery and an internal contact portion contacting the first conductivity type semiconductor layer in a region surrounded by the external contact portion, A first contact layer comprising; A second contact layer disposed on the mesa and contacting the second conductive semiconductor layer; And a first insulating layer covering the first conductive semiconductor layer and the mesa and insulating the first contact layer from the mesa and the second contact layer, Exposing the first conductivity type semiconductor layer such that the first conductivity type semiconductor layer contacts the first conductivity type semiconductor layer, and the external contact portion and the first insulation layer alternately contact the first conductivity type semiconductor layer A light emitting diode is provided.

According to embodiments of the present invention, by reducing the area in which the first contact layer contacts the first conductive type semiconductor layer and increasing the area in which the first insulating layer contacts the first conductive type semiconductor layer, Further, by using the first insulating layer including the distributed Bragg reflector which is excellent in reflection performance, more light can be reflected and the light extraction efficiency of the light emitting diode can be improved.

Other features and technical advantages of the present invention will become readily apparent from the following detailed description or from the detailed description.

1 is a schematic plan view of a light emitting diode according to an embodiment of the present invention.
2 is an enlarged view of a portion indicated by I in Fig.
FIG. 3 is a cross-sectional view taken along the perforated line AA and FIG. 2 along the perforated line BB.
FIGS. 4 to 10 are schematic plan views for explaining a method of manufacturing a light emitting diode according to an embodiment of the present invention, and cross-sectional views taken along a perforated line CC in each plan view. FIG.
11 is a schematic plan view illustrating a light emitting diode according to another embodiment of the present invention.
12 is a photograph showing the light emission pattern of the light emitting diodes of FIGS. 1 and 11. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

According to an embodiment of the present invention, a light emitting diode includes: a first conductive semiconductor layer; A second conductivity type semiconductor layer disposed on the first conductivity type semiconductor layer, and an active layer interposed between the second conductivity type semiconductor layer and the first conductivity type semiconductor layer; An external contact portion contacting the first conductivity type semiconductor layer near the edge of the first conductivity type semiconductor layer along the mesa periphery and an internal contact portion contacting the first conductivity type semiconductor layer in a region surrounded by the external contact portion, A first contact layer comprising; A second contact layer disposed on the mesa and contacting the second conductive semiconductor layer; And a first insulating layer covering the first conductive semiconductor layer and the mesa and insulating the first contact layer from the mesa and the second contact layer, Exposes the first conductivity type semiconductor layer such that the first conductivity type semiconductor layer is in contact with the first conductivity type semiconductor layer, and the external contact portion and the first insulation layer alternately contact the first conductivity type semiconductor layer along the side surface of the mesa .

Since the first contact layer includes an inner contact portion and an outer contact portion, the current dispersion performance is excellent. In addition, since the external contact portion continuously contacts the protruding portion of the first insulating layer without contacting the first conductive type semiconductor layer, the contact area of the external contact portion is reduced and the light loss can be reduced.

Moreover, the first insulating layer may comprise a distributed Bragg reflector. Accordingly, light can be reflected at a high reflectance using the first insulating layer, and the light extraction efficiency is improved.

The first insulating layer may include a protrusion and a recess portion around the mesa. The first contact layer may contact the first conductive type semiconductor layer at a recess portion of the first insulating layer.

Alternatively, the first contact layer may include a protrusion and a recessed portion around the mesa, the protrusion of the first contact layer may contact the first conductive type semiconductor layer, and the recess may be formed on the first insulating layer Lt; / RTI >

In some embodiments, the mesa has an indentation located between the fingers and the fingers, and the inner contact may be disposed in the indentation.

In other embodiments, the mesa may have a groove through the second conductivity type semiconductor layer and the active layer to expose the first conductivity type semiconductor layer, and the groove may be formed in the second conductivity type semiconductor layer and the active layer And the inner contact portion can contact the first conductive type semiconductor layer exposed in the groove.

The grooves have an H shape including two straight lines and connecting lines connecting them, and may be disposed in a central region of the mesa.

Furthermore, the internal contact may be formed in the two straight lines in the H-shaped groove, and the first contact layer may be spaced from the first conductivity type semiconductor layer by the first insulating layer on the connection line. Also, at least one of the end ends of the groove may have a wider width than other portions of the straight line.

On the other hand, the shortest distance between the inner contact portion and the outer contact portion may be the same at any point of the inner contact portion. By placing the inner contact in the middle of the mesa, light can be emitted evenly across the entire area of the mesa.

The distance between the inner contact portions formed on the two straight lines may be the same as the shortest distance between the inner contact portion and the outer contact portion.

Wherein the light emitting diode comprises: an upper insulating layer having a first opening overlapping the first contact layer and a second opening overlapping the second contact layer; A first electrode pad electrically connected to the first contact layer through the first opening; And a second electrode pad electrically connecting to the second contact layer through the second opening.

The light emitting diode may further include an intermediate connection portion connected to the second contact layer, wherein the first contact layer has an opening overlapping the second contact layer, And the second opening of the upper insulating layer exposes the intermediate connection portion, and the second electrode pad can be connected to the intermediate connection portion. By disposing the intermediate connection portion, the first electrode pad and the second electrode pad can be formed at the same level, so that the manufacturing process of the light emitting diode can be further stabilized. The intermediate connection portion may be formed of the same material as the first contact layer in the same process.

Furthermore, the first insulating layer has an opening exposing the second contact layer, and the intermediate connection portion can be connected to the second contact layer through the opening of the first insulating layer.

In some embodiments, the first insulating layer may have a plurality of openings exposing the second contact layer. In addition, the second opening of the upper insulating layer may expose all openings that expose the second contact layer.

On the other hand, the first insulating layer may be located on the first conductivity type semiconductor layer, around the second contact layer of the mesa phase, and on the second contact layer, The first insulating layer may be thicker than the first insulating layer located on the second contact layer.

In addition, the first insulating layer located around the second contact layer of the mesa may be thicker than the first insulating layer located on the first conductive type semiconductor layer.

Embodiments of the present invention will now be described in more detail with reference to the drawings.

1 is a schematic plan view (a) and a sectional view (b) for explaining a light emitting diode according to an embodiment of the present invention. Here, the sectional view (b) is taken along the cutting line A-A in the plan view (a). 2 is an enlarged view of a portion indicated by I in Fig. 1, Fig. 3 is a partial cross-sectional view taken along a perforated line B-B and a partial cross-sectional view taken along a perforated line C-C in Fig.

Referring to FIG. 1, the LED includes a substrate 21, a first conductive semiconductor layer 23, an active layer 25, a second conductive semiconductor layer 27, a first contact layer 35a, And includes a contact layer 31, a first insulating layer 29 and 33, an upper insulating layer 37, a first electrode pad 39a, and a second electrode pad 39b.

The substrate 21 is not particularly limited as long as it is a substrate capable of growing a gallium nitride based semiconductor layer. Examples of the substrate 21 include a sapphire substrate, a gallium nitride substrate, a SiC substrate, a Si substrate, and the like. The substrate 21 may have a rectangular or square contour as seen in plan view (a). The size of the substrate 21 may be, for example, a square shape of 1000 mu m x 1000 mu m or 700 mu m x 700 mu m or a rectangular shape of similar size. The size of the substrate 21 is not particularly limited and may be variously selected.

The first conductivity type semiconductor layer 21 is disposed on the substrate 21. The first conductivity type semiconductor layer 21 is a layer grown on the substrate 21 and is a gallium nitride based semiconductor layer. The first conductivity type semiconductor layer 21 may be a gallium nitride-based semiconductor layer doped with an impurity, for example, Si.

A mesa (M) is disposed on the first conductivity type semiconductor layer. The mesa M may be located within the region surrounded by the first conductivity type semiconductor layer 23 so that the regions near the edges of the first conductivity type semiconductor layer are not covered by the mesa M, Exposed.

The mesa M includes a second conductivity type semiconductor layer 27 and an active layer 25. The active layer 25 is interposed between the first conductivity type semiconductor layer 23 and the second conductivity type semiconductor layer 27. The active layer 25 may have a single quantum well structure or a multiple quantum well structure. The composition and thickness of the well layer in the active layer 25 determine the wavelength of the generated light. In particular, by controlling the composition of the well layer, it is possible to provide an active layer that generates ultraviolet light, blue light or green light.

On the other hand, the second conductivity type semiconductor layer 27 may be a p-type impurity, for example, a gallium nitride based semiconductor layer doped with Mg. Although the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27 may each be a single layer, the present invention is not limited thereto, and may be a multiple layer or a superlattice layer.

Meanwhile, the mesa M may include a finger refusal (F) and a palm area (P). An indent is formed between the fingers F, and the upper surface of the first conductive type semiconductor layer 23 is exposed by the indentation. In the present embodiment, the mesa M is described as having the finger rejection F and the palm portion P, but is not limited thereto. For example, the mesa M may have a rectangular shape similar to that of the substrate 21, and through holes may be formed in the mesa M to expose the first conductivity type semiconductor layer 23. In this embodiment, the number of fingers F is three, but the number of fingers F is not limited to three, but may be two or four or more.

On the other hand, the second contact layer 31 is disposed on the mesa M and contacts the second conductivity type semiconductor layer 27. The second contact layer 31 may be disposed over substantially the entire region of the mesa M in the mesa M upper region. For example, the second contact layer 31 may cover at least 80%, and thus at least 90%, of the mesa M upper region.

The second contact layer 31 may include a reflective metal layer and may thus reflect the light generated in the active layer 25 and traveling to the second contact layer 31 toward the substrate 21. Alternatively, the second contact layer 31 may comprise a transparent oxide layer such as indium tin oxide (ITO) or ZnO.

On the other hand, the preliminary insulating layer 29 may cover the mesa M around the second contact layer 31. The preliminary insulating layer 29 may be formed of, for example, SiO 2, and may cover a side surface of the mesa M and further cover a part of the first conductive type semiconductor layer 23. In another embodiment, the pre-insulating layer 29 may be disposed only around the second contact layer 31 at the top of the mesa M. [

On the other hand, the first contact layer 35a covers the upper region of the mesa M. The first contact layer 35a includes an inner contact portion 35a1 and an outer contact portion 35a2 which are in contact with the first conductivity type semiconductor layer 23. The external contact portion 35a2 contacts the first conductivity type semiconductor layer 23 near the edge of the substrate 21 along the periphery of the mesa M and the internal contact portion 35a1 contacts the inside of the region surrounded by the external contact portion 35a2 And contacts the first conductivity type semiconductor layer 23. As shown in Fig. 1 (a), furthermore, as can be seen more clearly in Fig. 8, the inner contact portion 35a1 can extend to the outer contact portion 35a2. The inner contact portion 35a1 may be connected to the outer contact portion 35a2 or may be spaced apart.

Meanwhile, the first contact layer 35a may have an opening in the upper portion of the mesa M, and the intermediate connection portion 35b may be disposed in the opening. The intermediate contact portions 35b may be formed together while forming the first contact layer 35a.

The lower insulating layer 33 may be disposed between the first contact layer 35a and the mesa M to isolate the first contact layer 35a from the mesa M and the second contact layer 31 . The lower insulating layer 33 has opening regions 33a1 and 33a2 that cover the preliminary insulating layer 29 and are integrated with the preliminary insulating layer 29 and expose the first conductive type semiconductor layer 23. A first insulating layer 29 and 33 including both a preliminary insulating layer 29 and a lower insulating layer 33 disposed between the mesa M region and the first contact layer 35a. do. The external contact portion 35a2 and the internal contact portion 35a1 described above may be formed by the opening regions 33a1 and 33a2 formed in the lower insulating layer 33 and the preliminary insulating layer 29. [ The lower insulating layer 33 may also be interposed between the intermediate contact portion 35b and the second contact layer 31 and may have an opening portion 33b for exposing the second contact layer 31. [ And the intermediate contact portion 35b can be connected to the second contact layer 31 through these openings 33b.

As best shown in Fig. 2, the first insulating layer 29, 33 has a protrusion 33p and a recess portion 33r near the edge of the substrate 21. The projecting portion 33p is located closer to the edge of the substrate 21 than the recessed portion 33r. The protruding portion 33p and the recess portion 33r may be located on the first conductivity type semiconductor layer 23. The projecting portion 33p) reduces the opening region 33a2 in which the first conductivity type semiconductor layer 23 is exposed.

Fig. 3 (a) is a sectional view taken along the perforated line B-B passing through the recessed portion 33r, and Fig. 3 (b) is a sectional view taken along the perforated line C-C passing through the projected portion 33p. 3 (a) and 3 (b), the forefront of the first contact layer 35a is located on the protruding portion 33p, and also near the recess portion 33r, (23).

That is, the first contact layer 35a contacts the first conductivity type semiconductor layer 23 exposed by the recess portion 33r to form an external contact portion 35a2. As a result, the external contact portions 35a2 and the protrusions 33p are alternately brought into contact with the first conductivity type semiconductor layer along the mesa M, thereby reducing the contact area of the external contact portions 35a2. Therefore, light loss due to the first contact layer 35a can be reduced.

The upper insulating layer 37 is disposed on the first contact layer 35a and the intermediate contact portion 35b and has an opening portion 37a for exposing the first contact layer 35a and an opening portion for exposing the intermediate contact portion 35b 37b. The upper insulating layer 37 may cover the side wall of the opening portion of the first contact layer 35a and the side wall of the intermediate connecting portion 35b.

The first insulating layers 29 and 33 and the upper insulating layer 37 may be formed of a single layer of SiO ₂ , but the present invention is not limited thereto. For example, the lower insulating layer 33 or the upper insulating layer 37 may have a multi-layer structure including a silicon nitride film and a silicon oxide film, or may be a distributed Bragg reflector in which a silicon oxide film and a titanium oxide film are alternately laminated.

In particular, when the lower insulating layer 33 is formed of a distributed Bragg reflector with high reflectance, the light extraction efficiency can be increased by reflecting the light by using the projecting portion 33p of the lower insulating layer 33. [

The first electrode pad 39a is electrically connected to the first contact layer 35a through the opening 37a of the upper insulating layer 37 and the second electrode pad 39b is electrically connected to the intermediate contact pad 35b through the opening 37b. (35b). Accordingly, the second electrode pad can be electrically connected to the second contact layer 31 through the intermediate connection portion 35b.

1 to 3 are schematically shown for convenience of explanation, and the structure of the light emitting diode and the respective components will be more clearly understood through the light emitting diode manufacturing method described later.

4 to 10 are views for explaining a method of manufacturing a light emitting diode according to an embodiment of the present invention. In each of FIGS. 4 to 10, (a) is a plan view and (b) Fig.

4, a first conductivity type semiconductor layer 23, an active layer 25, and a second conductivity type semiconductor layer 27 are grown on a substrate 21. The substrate 21 is not particularly limited as long as the substrate can grow the gallium nitride-based semiconductor layer. Examples of the substrate 21 include a sapphire substrate, a gallium nitride substrate, a SiC substrate, a Si substrate, and the like.

Meanwhile, the first conductive semiconductor layer 23 may include an n-type gallium nitride layer and the second conductive semiconductor layer 27 may include a p-type gallium nitride layer. In addition, the active layer 25 may be a single quantum well structure or a multiple quantum well structure, and may include a well layer and a barrier layer. Further, the well layer may be selected from its compositional elements depending on the wavelength of the required light, and may include, for example, InGaN.

The first conductive semiconductor layer 23, the active layer 25 and the second conductive semiconductor layer 27 may be grown on the substrate 21 by metal organic chemical vapor deposition (MOCVD). Here, the first conductive semiconductor layer 23 may be doped with an n-type impurity, for example, Si. The first conductivity type semiconductor layer 23 may have a doping concentration within a range of, for example, 8E17 / cm3 to 1E18 / cm3.

Next, the mesa M is formed on the first conductivity type semiconductor layer 23 by patterning the second conductivity type semiconductor layer 27 and the active layer 25. The mesa M may include the active layer 25 and the second conductivity type semiconductor layer 27 and may further include a thickness of the first conductivity type semiconductor layer 23. The mesa M is disposed inside the edge region of the first conductivity type semiconductor layer 23 and may include a finger F and a palm portion P. [ However, the present invention is not limited to this, and may have a structure in which a groove is formed in a quadrangular mesa. This will be described later in another embodiment.

On the other hand, as shown in FIG. 4, the number of fingers F may be three, but is not limited thereto, and may be two or four or more. The first conductive semiconductor layer 23 around the mesa M is exposed and the indentation B is disposed between the fingers F. [ The indentation portion B is not particularly limited, but may be embossed to about half the length of one side of the mesa M. [ Accordingly, the finger portions F may have substantially the same length as the palm portion P. [ By disposing the finger portions F and the palm portions P, the second conductivity type semiconductor layers 27 can be connected together, and subsequent processes for current dispersion can be simplified.

The side surface of the mesa M may be formed obliquely using a technique such as photoresist reflow. The inclined profile of the mesa (M) side improves the extraction efficiency of the light generated in the active layer 25.

Referring to FIG. 5, a pre-insulating layer 29 is formed to cover the first conductivity type semiconductor layer 23 and the mesa M. The preliminary insulating layer 29 may be formed of SiO ₂ using, for example, a chemical vapor deposition technique.

A photoresist pattern 30 is formed on the preliminary insulating layer 29. The photoresist pattern 30 has openings exposing the mesa M upper region. The opening may be substantially similar to the shape of the mesa M, but may be formed slightly smaller than the mesa M. That is, the photoresist can cover the edge portions of the mesa M. Further, the opening may be formed so that the width of the bottom portion is wider than the width of the inlet. For example, by using a negative type photoresist, it is possible to easily form the photoresist pattern 30 having the opening with the above-described shape.

Next, the preliminary insulating layer 29 is etched using the photoresist pattern 30 as an etching mask, thereby exposing the second conductive type semiconductor layer 27. Then, as shown in FIG. The pre-insulating layer 29 may be etched using, for example, a wet etching technique.

A second contact layer (e.g., p contact layer, 31) is then formed. The second contact layer 31 may be formed on the mesa M by a coating technique using an electron beam evaporation method.

Referring to FIG. 6, the photoresist pattern 30 is removed. In addition, the material deposited on the photoresist is also removed along with the photoresist pattern 30. As a result, the second contact layer 31 that contacts the second conductive type semiconductor layer 27 remains on the mesa M, and the preliminary insulating layer 29 remains around the second contact layer 31 . The preliminary insulating layer 29 may also cover the exposed portion of the first conductive type semiconductor layer 23.

Here, the second contact layer 31 may be a single metal material layer, but is not limited thereto, and may be a multiple layer. For example, the second contact layer 31 may comprise a reflective layer, a capping layer, and an anti-oxidation layer. Further, a stress relieving layer may be interposed between the reflective layer and the capping layer.

The reflective layer may be formed of, for example, Ni / Ag / Ni / Au, and the capping layer may cover the upper and side surfaces of the reflective layer to protect the reflective layer. The reflective layer is formed using an electron beam evaporation method, and the capping layer is formed using a sputtering technique or an electron-beam evaporation method (e.g., planetary e-beam evaporation) in which the substrate 21 is rotated by tilting and vacuum evaporated . The capping layer may include Ni, Pt, Ti, or Cr, and may be formed, for example, by depositing at least one pair of Ni / Pt or at least one pair of Ni / Ti. Alternatively, the capping layer may comprise TiW, W, or Mo.

The stress relieving layer intervenes between the reflective layer and the capping layer to relieve the stress, and thus can be variously selected depending on the metal material of the reflective layer and the capping layer. The stress relieving layer may be a single layer of Ag, Cu, Ni, Pt, Ti, Rh, Pd, or Cr, or may be a single layer of Ag, Cu, Ni, Pt, or the like when the reflective layer is Al or an Al alloy and the capping layer comprises W, Ni, Pt, Ti, Rh, Pd or Au. When the reflective layer is Al or an Al alloy and the capping layer is Cr, Pt, Rh, Pd or Ni, the stress relieving layer may be a single layer of Ag or Cu, or a composite layer of Ni, Au, Cu or Ag.

The stress relieving layer may be a single layer of Cu, Ni, Pt, Ti, Rh, Pd or Cr, or may be a single layer of Cu , Ni, Pt, Ti, Rh, Pd, Cr, or Au. When the reflective layer is Ag or Ag alloy and the capping layer is Cr or Ni, the stress relieving layer may be a single layer of Cu, Cr, Rh, Pd, TiW or Ti, or a composite layer of Ni, Au or Cu.

Further, the antioxidant layer contains Au to prevent oxidation of the capping layer, and may be formed of Au / Ni or Au / Ti, for example. Ti is preferred because of the good adhesion of the oxide layer such as SiO ₂ . The antioxidant layer may also be formed using sputtering or electron-beam evaporation (e. G., Planetary e-beam evaporation) in which the substrate 21 is tilted and rotated and vacuum deposited.

Although the second contact layer 31 is a metal layer in the present embodiment, the present invention is not limited thereto. Any material that makes an ohmic contact with the second conductivity type semiconductor layer 27 may be used as the second contact layer 31). For example, the second contact layer 31 may be a transparent conductive layer such as ITO or ZnO.

Referring to FIG. 7, a lower insulating layer 33 covering the mesa M and the first conductive semiconductor layer 23 is formed. The lower insulating layer 33 covers the second contact layer 31 and also covers the pre-insulating layer 29. Accordingly, the lower insulating layer 33 can be integrated with the preliminary insulating layer 29 and into one insulating layer, and can be patterned together with the preliminary insulating layer 29. In this embodiment, the preliminary insulating layer 29 is described in advance, but the preliminary insulating layer 29 may be omitted. In addition, the preliminary insulating layer 29 may be located on the mesa M. It is not easy to distinguish the preliminary insulating layer 29 from the lower insulating layer 33 because the preliminary insulating layer 29 is thin. Therefore, unless otherwise stated, the first insulating layer 29, 33 includes all the insulating layers disposed between the mesa M and the first contact layer 35a.

The insulating layers 29 and 33 expose the first conductivity type semiconductor layer 23 along the periphery of the mesa M to allow electrical connection to the first conductivity type semiconductor layer 23 in a specific region, Thereby exposing the first conductivity type semiconductor layer 23 in the region between the first conductivity type semiconductor layers. These opening areas are indicated by the reference numerals 33a1 and 33a2. Furthermore, the first insulating layer 29, 33 has openings 33b for allowing electrical connection to the second contact layer 31. [ The first insulating layers 29 and 33 may have different thicknesses at respective positions depending on whether or not the pre-insulating layer 29 is present. As can be seen, the thickness of the first insulating layer 29, 33 located on the second contact layer 31 is greater than the thickness of the first insulating layer 29 and 33 located around the second contact layer 31 It may be thinner than the thickness. When the preliminary insulating layer 29 is formed around the second contact layer 31 at the upper portion of the mesa M and the second insulating layer 29 is formed around the second contact layer 31 and the first conductive semiconductor layer 23, The thickness of the first insulating layers 29 and 33 located around the second contact layer 31 on the mesa M is thicker than the thickness of the first insulating layer 33. [ On the other hand, the opening regions 33a1 and 33a2 may be formed by patterning the lower insulating layer 33 and the preliminary insulating layer 29 together and the opening 33b may be formed by the lower insulating layer 33 As shown in FIG. In addition, the opening 33b is located on the second contact layer 31 and overlaps with the second contact layer 31. [

The opening regions 33a1 are located between the fingers F to expose the first conductive type semiconductor layer 23. Further, an opening region 33a2 is formed near the periphery of the substrate 21 along the mesa (M). The opening region 33a2 and the opening region 33a1 may be connected to each other, but not limited thereto, and may be spaced apart from each other.

The opening region 33a2 is determined by the position of the front line of the first insulating layer 29, 33. That is, an opening region 33a2 between the edge of the upper surface of the first conductivity type semiconductor layer 23 and the forefront of the first insulating layers 29 and 33 is exposed. On the other hand, the forefront of the first insulating layers 29, 33 includes the projecting portion 33p and the recess portion 33r. The forefront may, for example, have the form of a trigonometric waveform, but it is not limited thereto and may have various forms. Further, the protrusion 33p and the recess portion 33r can be alternately repeated. Accordingly, the opening region 33a2 has a shape in which a large region and a narrow region are repeated.

On the other hand, the opening 33b is disposed on the palm portion P of the mesa M. [ Therefore, the number of openings 33b is not particularly limited, and may be one or more. When there are a plurality of openings 33b, they may be arranged so as to have a symmetrical structure, but the present invention is not limited thereto.

The lower insulating layer 33 may be formed of an oxide film such as SiO ₂ , a nitride film such as SiNx, or an insulating film of MgF ₂ using a technique such as chemical vapor deposition (CVD), and may be patterned using photolithography and etching techniques .

The lower insulating layer 33 may be formed of a distributed Bragg reflector (DBR) in which a low refractive material layer and a high refractive material layer are alternately laminated. For example, an insulating reflection layer having a high reflectance can be formed by laminating SiO ₂ / TiO ₂ or SiO ₂ / Nb ₂ O ₅ layers.

Referring to FIG. 8, a first contact layer 35a and an intermediate connection portion 35b are formed on the first insulation layers 29 and 33. In FIG. The first contact layer 35a and the intermediate connection portion 35b may be formed simultaneously using the same material, for example, using a lift-off technique.

The first contact layer 35a covers most of the region above the first conductivity type semiconductor layer 23 except for the region where the intermediate connection portion 35b is to be formed. The first contact layer 35a is insulated from the mesa M and the second contact layer 31 by a first insulating layer 29, The first contact layer 35a has an opening surrounding the intermediate connection portion 35b and the intermediate connection portion 35b is formed in the opening.

The first contact layer 35a is electrically connected to the first conductivity type semiconductor layer 34a through an inner contact portion 35a1 and an opening region 33a2 which are in contact with the first conductivity type semiconductor layer 23 exposed in the opening 33a1, 23 which are in contact with each other. The external contact portion 35a2 contacts the first conductivity type semiconductor layer 23 in the vicinity of the edge of the first conductivity type semiconductor layer 23 along the periphery of the mesa M. [ At this time, a part of the forefront of the first contact layer 35a is located on the protruding portion 33p of the first insulating layer 29, 33 and is separated from the first conductivity type semiconductor layer 23, The external contact portion 35a2 is formed on the first conductive type semiconductor layer 23 exposed in the recess portion 33r of the insulating layers 29 and 33. [ The external contact portions 35a of the first contact layer 35a come into contact with the first conductive type semiconductor layer 23 alternately with the first insulating layers 29 and 33 along the side surface of the mesa M. [ This reduces the total area of the external contact portion 35a2 as compared with the case where the line-shaped external contact portions 35a2 are formed in the first insulating layers 29 and 33 formed without the projections 33p, The light can be reflected by using the first and second reflecting mirrors 29 and 33, and the light extraction efficiency can be improved.

The inner contact portion 35a1 is connected to the first conductivity type semiconductor layer 23 in the region surrounded by the outer contact portion 35a2, particularly in the region between the fingers F. [ In particular, three or more finger portions F may be formed, and a plurality of internal contact portions 35a1 may be connected to the first conductivity type semiconductor layer 23. [ Accordingly, since a plurality of internal contacts 35a1 together with the external contacts 35a2 are connected to various points of the first conductive type semiconductor layer 23, the current can be easily dispersed.

The opening of the first contact layer 35a is formed so as to surround the opening 33b of the first insulating layer such as the lower insulating layer 33 and the intermediate connecting portion 35b is formed so as to surround the opening 33b of the lower insulating layer 33. [ And covers the opening 33b. The intermediate connection portion 35b is connected to the second contact layer 31 through the opening 33b of the lower insulating layer 33. [ The intermediate contact portion 35b is also disposed over the second contact layer 31, and may be specifically located on the palm portion P of the mesa M. [

According to the present embodiment, the first contact layer 35a is formed on almost the entire region of the first conductivity type semiconductor layer 23 except for the openings. Therefore, the current can be easily dispersed through the first contact layer 35a. The first contact layer 35a may comprise a highly reflective metal layer such as an Al layer and the highly reflective metal layer may be formed on an adhesive layer such as Ti, Cr or Ni. Further, a protective layer of a single layer or a multiple layer structure such as Ni, Cr, Au or the like may be formed on the highly reflective metal layer. The first contact layer 35a may have a multilayer structure of Cr / Al / Ni / Ti / Ni / Ti / Au / Ti, for example.

Referring to FIG. 9, an upper insulating layer 37 is formed on the first contact layer 35a. The upper insulating layer 37 has an opening 37a exposing the first contact layer 35a and an opening 37b exposing the intermediate connecting portion 35b. The opening 37a may be formed to overlap the first contact layer 35a over the fingers F of the mesa M and the opening 37b may be formed on the palm portion P of the mesa M, 2 contact layer 31 on the intermediate contact 35b.

The opening 37b is positioned to overlap the second contact layer 31 and may have a smaller size than the intermediate connection portion 35b. Therefore, the edge and the side wall of the intermediate connection portion 35b are covered with the upper insulating layer 37. [ Furthermore, the sidewalls of the openings of the first contact layer 35a are also covered with the upper insulating layer 37.

The upper insulating layer 37 may be formed of a single layer of a silicon nitride film or a silicon oxide film, but is not limited thereto. The upper insulating layer 37 may be formed of a multi-layered or distributed Bragg reflector structure. The upper insulating layer 37 may cover the side surface of the first conductive type semiconductor layer 23 so as to cover the inclined plane L1.

Referring to FIG. 10, a first electrode pad 39a and a second electrode pad 39b are formed on the upper insulating layer 37. Referring to FIG. The first electrode pad 39a is connected to the first contact layer 35a through the opening 37a of the upper insulating layer 37 and the second electrode pad 39b is connected to the opening 37b To the intermediate connection portion 35b. The first electrode pad 39a and the second electrode pad 39b are used for mounting a light emitting diode on a submount, a printed circuit board, or the like. The first electrode pad 39a and the second electrode pad 39b may be formed of AuSn and may be mounted on a submount or the like through eutectic bonding.

The distance D between the first and second electrode pads may be about 80 탆 or more so as to prevent a short circuit.

Meanwhile, the first and second electrode pads 39a and 39b may be formed together using the same process, for example, using a lift-off technique.

Subsequently, the LEDs are individually separated by dividing the light emitting diodes into individual light emitting diodes by a process such as laser scribing and cracking.

11 is a schematic plan view illustrating a light emitting diode according to another embodiment of the present invention.

Although the internal contact portions 35a1 are formed in the recessed portions in the above-described embodiment, the internal contact portions 35a1 may be formed in the mesa structure of the first conductive semiconductor layer 23 exposed in the groove formed in the mesa M, And the like.

That is, the mesa M has a groove penetrating the second conductivity type semiconductor layer 27 and the active layer 25 to expose the first conductivity type semiconductor layer 23. The grooves are surrounded by the second conductivity type semiconductor layer 27 and the active layer 25 and the inner contact portion 35a1 is in contact with the first conductivity type semiconductor layer 23 exposed in the groove. Thereby, the inner contact portion 35a1 is separated from the outer contact portion 35a2.

On the other hand, as can be seen from FIG. 11, the grooves may have an H shape including two straight lines and connecting lines connecting them. The grooves may be disposed in the central region of the mesa M. [ Furthermore, the inner contact portion 35a1 is formed in the two straight lines in the H-shaped groove, and the inner contact portion 35a1 may not be formed in the connection line. That is, the first contact layer 35b may be disposed above the connection line, but may be spaced apart from the first conductivity type semiconductor layer 23 by the first insulation layer 29, 33.

On the other hand, at least one of the end ends of the groove may have a wider width than other portions of the straight line. These ends are located near the area where the first electrode pad 39a and the second electrode pad 39b are located, respectively. As shown in FIG. 11, the first electrode pad 39a may be disposed on two ends of the end portions, and the second electrode pad 39b may be formed to surround the other two ends. .

On the other hand, the shortest distance between the inner contact portion 35a1 and the outer contact portion 35a2 may be the same at any point of the inner contact portion 35a1. Further, the distance between the inner contact portions 35a1 formed on the two straight lines in the H-shaped groove may be the same as the shortest distance between the inner contact portion 35a1 and the outer contact portion 35a2. Thus, the current can be evenly distributed over the entire light emitting region.

12 is a photograph showing a light emission pattern of a light emitting diode according to the above-described embodiments. 12 (a) is a light emission pattern of the light emitting diode in which the inner contact portion is disposed in the indentation portion, and FIG. 12 (b) is a light emission pattern of the light emitting diode in which the inner contact portion is disposed in the H-shaped groove. The light emission pattern is observed from the side of the substrate 21 which is the light emitting surface of the flip chip type light emitting diode.

12 (a) shows that light is mainly emitted in the recessed regions where the inner contact portion 35a1 is formed, and light is not emitted well in the region where the second electrode pad 39b is disposed. On the other hand, FIG. 12 (B) shows that light is emitted satisfactorily in most of the regions.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, the elements or components described in relation to one embodiment can be applied to other embodiments without departing from the technical idea of the present invention.

Claims (18)

A first conductive semiconductor layer;
A second conductivity type semiconductor layer disposed on the first conductivity type semiconductor layer, and an active layer interposed between the second conductivity type semiconductor layer and the first conductivity type semiconductor layer;
An external contact portion contacting the first conductivity type semiconductor layer near the edge of the first conductivity type semiconductor layer along the mesa periphery and an internal contact portion contacting the first conductivity type semiconductor layer in a region surrounded by the external contact portion, A first contact layer comprising;
A second contact layer disposed on the mesa and contacting the second conductive semiconductor layer;
And a first insulating layer covering the first conductive semiconductor layer and the mesa and insulating the first contact layer from the mesa and the second contact layer,
Wherein the first insulating layer exposes the first conductivity type semiconductor layer such that the external contact portion and the internal contact portion contact the first conductivity type semiconductor layer,
Wherein the external contact portion and the first insulating layer alternately contact the first conductive type semiconductor layer along a side surface of the mesa. The method according to claim 1,
Wherein the first insulating layer comprises a distributed Bragg reflector. The method according to claim 1,
Wherein the first insulating layer includes a protrusion and a recessed portion around the mesa,
Wherein the first contact layer contacts the first conductive type semiconductor layer at a recess portion of the first insulating layer. The method according to claim 1,
Wherein the first contact layer includes a protrusion and a recessed portion around the mesa, the protrusion of the first contact layer contacts the first conductive type semiconductor layer, and the recessed portion is located on the first insulating layer Light emitting diode. The method according to claim 1,
The mesa having an indentation located between the fingers and the fingers,
Wherein the inner contact is disposed in the indent. The method according to claim 1,
Wherein the mesa has a groove penetrating the second conductivity type semiconductor layer and the active layer to expose the first conductivity type semiconductor layer, the groove being surrounded by the second conductivity type semiconductor layer and the active layer, And the first conductive semiconductor layer exposed in the groove. The method of claim 6,
The grooves having an H-shape including two straight lines and connecting lines connecting them, and arranged in a central region of the mesa. The method of claim 7,
Wherein the internal contact is formed in the two straight lines in the H-shaped groove, and wherein the first contact layer on the connection line is spaced from the first conductive semiconductor layer by the first insulating layer. The method of claim 7,
Wherein at least one of the ends of the groove has a wider width than other portions of the straight line. The method of claim 8,
Wherein the shortest distance between the inner contact portion and the outer contact portion is the same at any point of the inner contact portion. The method of claim 10,
Wherein a distance between the inner contacts formed on the two straight lines is equal to a shortest distance between the inner contact and the outer contact. The method according to claim 1,
An upper insulating layer having a first opening overlapping with the first contact layer and a second opening overlapping with the second contact layer;
A first electrode pad electrically connected to the first contact layer through the first opening; And
And a second electrode pad electrically connected to the second contact layer through the second opening. The method of claim 12,
And an intermediate connection portion connected to the second contact layer,
Wherein the first contact layer has an opening overlapping the second contact layer,
The intermediate connection portion is located inside the opening of the first contact layer,
A second opening of the upper insulating layer exposes the intermediate connection,
And the second electrode pad is connected to the intermediate connection portion. 14. The method of claim 13,
Wherein the first insulating layer has an opening exposing the second contact layer,
And the intermediate connecting portion is connected to the second contact layer through the opening of the first insulating layer. 15. The method of claim 14,
Wherein the first insulating layer has a plurality of openings for exposing the second contact layer. 16. The method of claim 15,
And the second opening of the upper insulating layer exposes all openings that expose the second contact layer. The method according to claim 1,
The first insulating layer may be located on the first conductive type semiconductor layer, around the second contact layer of the mesa phase, and on the second contact layer, 1 < / RTI > insulating layer is thicker than the first insulating layer located on the second contact layer. 18. The method of claim 16,
Wherein the first insulating layer located around the second contact layer of the mesa is thicker than the first insulating layer located on the first conductive type semiconductor layer.

Images