KR20150067566A - Light emitting diode with wavelength conversion layer and method of fabricating the same - Google Patents

Abstract

Disclosed are a light emitting diode and a fabricating method thereof. The light emitting diode comprises: a support substrate; a semiconductor multilayer structure located on the support substrate, and including a first conductivity semiconductor layer, an active layer, and a second conductivity semiconductor layer; and a wavelength conversion layer arranged between the support substrate and the first conductivity semiconductor layer. Accordingly, the present invention can prevent light from being emitted to the outside by not passing through the wavelength conversion layer.

Description

TECHNICAL FIELD [0001] The present invention relates to a light emitting diode having a wavelength conversion layer and a method of manufacturing the same. BACKGROUND OF THE INVENTION [0002]

The present invention relates to a light emitting diode and a method of manufacturing the same, and more particularly, to a light emitting diode having a wavelength conversion layer and a method of manufacturing the same.

BACKGROUND ART GaN-based LEDs have been used in various applications such as color LED display devices, LED traffic signals, and white LEDs since gallium nitride (GaN) -based light emitting diodes have been developed.

Gallium nitride based light emitting diodes are generally formed by growing epitaxial layers on a substrate such as sapphire and include an N-type semiconductor layer, a P-type semiconductor layer, and an active layer interposed therebetween. On the other hand, an N-electrode pad is formed on the N-type semiconductor layer, and a P-electrode pad is formed on the P-type semiconductor layer. The light emitting diode is electrically connected to an external power source through the electrode pads.

Generally, light emitting diodes are fabricated in a chip form and then packaged. Conventionally, a light emitting diode package is manufactured by mounting a previously manufactured light emitting diode chip in a package housing or the like. That is, the light emitting diode chip fabrication process and the light emitting diode package fabrication process are separated. Therefore, the chip fabrication line and the packaging line are generally separated. On the other hand, the wavelength conversion layer is formed on the light emitting diode chip after the light emitting diode chip is manufactured, or on the light emitting diode chip in the package making process.

2. Description of the Related Art In recent years, a wafer level light emitting diode package that packages a light emitting diode chip manufacturing process and a package manufacturing process in a chip manufacturing line has been studied. Unlike the prior art, fabrication of a wafer level light emitting diode package is intended to complete the chip fabrication process and the packaging fabrication process together. For example, Korean Patent Laid-Open Publication No. 10-2013-0030178 discloses a method of manufacturing a flip chip structure light emitting diode package at a wafer level.

The prior art discloses an embodiment in which a growth substrate is used as a support substrate of a light emitting diode package, a support is additionally formed for supporting the package, a growth substrate is removed, and a wavelength conversion layer is formed.

In the embodiment in which the growth substrate is left, it is difficult to form the wavelength conversion layer on the side surface of the growth substrate. That is, in order to form the light emitting diode package at the wafer level, the wavelength conversion layer must be formed on the growth substrate and the wafer must be divided into individual chips. In this case, the wavelength conversion layer is not formed on the side surface of the growth substrate, and therefore, a part of the light generated in the active layer is emitted without wavelength conversion through the side surface of the growth substrate.

On the other hand, in the embodiment in which the supporting portion is additionally provided, since the growth substrate is removed and the wavelength conversion layer is formed, light can be prevented from being emitted to the side surface of the substrate without wavelength conversion. However, since the support is additionally formed, the package manufacturing process becomes complicated. Furthermore, since the supporting portions must support the wafer instead of the growth substrate and the pad electrodes must be exposed to the outside through the supporting portion, there is a problem that the process of forming the supporting portion is extremely complicated.

Korean Patent Publication No. 10-2013-0030178

A problem to be solved by the present invention is to provide a light emitting diode capable of forming a wavelength conversion layer at a wafer level and a method of manufacturing the same.

Another object of the present invention is to provide a wafer level light emitting diode package which can be manufactured by a simple process and a method of manufacturing the same.

Another object of the present invention is to provide a wafer level light emitting diode package that can prevent light from being emitted to the outside without passing through the wavelength conversion layer and a method of manufacturing the same.

Another object of the present invention is to provide a light emitting diode which can be directly mounted on a printed circuit board or the like by using a solder paste and a method of manufacturing the same.

According to one aspect of the present invention, there is provided a light emitting diode comprising: a support substrate; A semiconductor stacked structure located on the support substrate and including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer; And a wavelength conversion layer disposed between the supporting substrate and the first conductivity type semiconductor layer.

The light is emitted to the outside through the support substrate. Since the wavelength conversion layer is disposed between the support substrate and the first conductivity type semiconductor layer, all light incident on the support substrate passes through the wavelength conversion layer. Therefore, it is possible to prevent light from being emitted to the outside without passing through the wavelength conversion layer.

In some embodiments, the wavelength conversion layer may be in direct contact with the semiconductor laminated structure. Furthermore, the wavelength conversion layer may include a SOG containing a phosphor.

In other embodiments, the light emitting diode may further include an adhesive layer disposed between the wavelength conversion layer and the first conductive type semiconductor layer. Further, the adhesive layer may comprise SOG.

On the other hand, the first conductivity type semiconductor layer may have a rough surface on the wavelength conversion layer side. The roughened surface prevents total internal reflection between the first conductivity type semiconductor layer and the adhesive layer (or the wavelength conversion layer), thereby improving light extraction efficiency.

The light emitting diode may include a plurality of mesas on the first conductive type semiconductor layer, and the plurality of mesas may include the active layer and the second conductive type semiconductor layer, respectively.

Further, the light emitting diode may include a first electrode pad electrically connected to the first conductive semiconductor layer; And a second electrode pad electrically connected to the second conductivity type semiconductor layer of each of the mesas. The first electrode pad and the second electrode pad may include a solder preventing layer and an oxidation preventing layer, respectively. Accordingly, it is possible to provide a wafer level light emitting diode package that can be directly mounted on a printed circuit board or the like by using solder paste.

Unlike the AuSn solder, the solder paste is a mixture of a metal alloy and an organic material and is cured by heat treatment to perform an adhesive function. Therefore, the metallic element such as Sn in the solder paste is likely to diffuse unlike the metallic element in the conventional AuSn solder.

By forming the first electrode pad and the second electrode pad in a structure including a solder preventing layer, it is possible to prevent metal elements such as Sn in the solder paste from diffusing into the light emitting diode.

The light emitting diode includes: a reflective electrode structure disposed on the mesas; And a second electrode layer covering the plurality of mesas and the first conductivity type semiconductor layer and having openings that are located in the respective mesa upper regions and expose the reflective electrode structures and which are in ohmic contact with the first conductivity type semiconductor layer, And a current-dispersive layer insulated from the mesas. Here, the first electrode pad is electrically connected to the current dispersion layer, and the second electrode pad is electrically connected to the reflective electrode structures.

Since the current spreading layer covers the plurality of mesas and the first conductivity type semiconductor layer, the current dispersion performance of the light emitting diode is improved.

The light emitting diode further includes an upper insulating layer covering at least a part of the current spreading layer, the openings exposing the reflective electrode structures, and the second electrode pad is located on the upper insulating layer, And can be electrically connected to the exposed reflective electrode structures through the openings of the insulating layer.

Furthermore, the light emitting diode may further include a diffusion prevention layer positioned between the reflective electrode structures and the second electrode pad. The diffusion preventive reinforcement layer can prevent the diffusion of the metal element diffused through the second electrode pad into the light emitting diode. The diffusion preventing reinforcing layer may be formed of the same material as the current spreading layer.

The light emitting diode may further include a lower insulating layer disposed between the plurality of mesas and the current dispersion layer to insulate the current dispersion layer from the plurality of mesas. The lower insulating layer may have openings located within the respective mesa upper regions and exposing the reflective electrode structures.

The light emitting diode may be a wafer level light emitting diode package.

According to another aspect of the present invention, there is provided a method of manufacturing a light emitting diode, comprising: forming a semiconductor stacked structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer on a substrate; A step of removing the substrate from the semiconductor laminated structure, forming a wavelength conversion layer on the supporting substrate, attaching the supporting substrate to the semiconductor laminated structure such that the wavelength conversion layer and the semiconductor laminated structure face each other, Removing the carrier.

Thus, there is provided a wafer in which the wavelength conversion layer is disposed between the support substrate and the first conductivity type semiconductor layer, and the wafer level light emitting diode package can be manufactured using the wafer, thereby simplifying the package production process.

The supporting substrate may be attached to the semiconductor laminated structure by an adhesive layer. Further, the adhesive layer may comprise SOG. By using the optically transparent SOG, the light loss can be reduced, and by using the inorganic SOG, the stability of the manufacturing process of the light emitting diode package can be achieved.

In some embodiments, the light emitting diode manufacturing method may further include forming a rough surface on the surface of the first conductivity type semiconductor layer before attaching the support substrate.

Further, the light emitting diode may be a wafer level light emitting diode package.

According to another aspect of the present invention, there is provided a method of manufacturing a light emitting diode, comprising: forming a semiconductor stacked structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer on a substrate; Removing the substrate from the semiconductor laminate structure, attaching a supporting substrate to the semiconductor laminate structure, and removing the carrier. Further, the supporting substrate is attached to the semiconductor laminated structure by an adhesive layer containing a phosphor.

Thus, the adhesive layer functions as the wavelength conversion layer, and the fluorescent substance can be disposed closer to the active layer, so that the light emitted to the outside without wavelength conversion can be further reduced.

The adhesive layer may include a SOG containing a phosphor. That is, the support substrate can be attached to the semiconductor laminated structure using the SOG mixed with the phosphor.

The method of manufacturing a light emitting diode may further include forming a rough surface on the surface of the first conductivity type semiconductor layer before attaching the support substrate.

Further, the light emitting diode may be a wafer level light emitting diode package.

According to embodiments of the present invention, the manufacturing process of the wafer level light emitting diode package can be simplified by manufacturing the light emitting diode package using the wafer including the support substrate and the wavelength conversion layer. Particularly, according to embodiments of the present invention, a light emitting diode package in which a wavelength conversion layer is formed at a wafer level is provided. Further, since the wavelength conversion layer is disposed between the support substrate and the semiconductor laminated structure, light can be prevented from being emitted to the outside without passing through the wavelength conversion layer. Further, a wafer level light emitting diode package that can be directly mounted on a printed circuit board or the like by using a solder paste by forming a solder prevention layer or the like can be provided.

Other features and advantages of the invention will also be apparent from the detailed description of the invention.

1 to 13 are views for explaining a method of manufacturing a light emitting diode according to an embodiment of the present invention. In each of FIGS. 4 to 12, (a) is a plan view, (b) Fig.
FIGS. 14 to 16 are views for explaining a method of fabricating a light emitting diode according to another embodiment of the present invention, in which (a) is a plan view and (b) is a sectional view taken along the cutting line AA.
17 to 20 are diagrams for explaining a method of manufacturing a light emitting diode according to yet another embodiment of the present invention, wherein (a) is a plan view and (b) is a sectional view taken along the cutting line AA.
21 is a cross-sectional view illustrating a method of fabricating a light emitting diode according to another embodiment of the present invention.
22 is a cross-sectional view illustrating a method of fabricating a light emitting diode according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

Hereinafter, a light emitting diode and a method of manufacturing the same will be described. In particular, a wafer level light emitting diode package and a method of manufacturing it are described. As used herein, the term "wafer level light emitting diode package" means a light emitting device in which a packaging process is completed with completion of a chip fabrication process, and can be directly mounted on a printed circuit board or the like without additional packaging process. This wafer level light emitting diode package includes a wavelength conversion layer that is incorporated into the wafer during the process of manufacturing the light emitting diode package at the wafer level. Further, the wavelength conversion layer is disposed close to the active layer, and therefore, most of light emitted to the outside from the light emitting diode package passes through the wavelength conversion layer.

Before describing the structure of the wafer level light emitting diode package according to the embodiments of the present invention, a method of manufacturing the wafer level light emitting diode package will be described first. The structure of the wafer level light emitting diode package according to the embodiment of the present invention will also be clarified through this manufacturing method.

1 to 13 are views for explaining a method of manufacturing a light emitting diode according to an embodiment of the present invention. In each of FIGS. 4 to 12, (a) is a plan view, (b) Fig.

1 (a), a first conductivity type semiconductor layer 23, an active layer 25, and a second conductivity type semiconductor layer 27 are grown on a substrate 21. The substrate 21 may be a sapphire substrate, a silicon carbide substrate, a gallium nitride (GaN) substrate, a spinel substrate, or the like as a substrate on which the gallium nitride based semiconductor layer can be grown. In particular, the substrate may be a patterned substrate.

The first conductivity type semiconductor layer 23 may include, for example, an n-type gallium nitride layer and the second conductivity type semiconductor layer 27 may include a p-type gallium nitride layer. In addition, the active layer 25 may be a single quantum well structure or a multiple quantum well structure, and may include a well layer and a barrier layer. Further, the well layer may be a gallium nitride-based composition element depending on the wavelength of the required light, and may include, for example, InGaN.

1 (b), a carrier 51 is attached on the second conductivity type semiconductor layer 27, and the substrate 21 is removed. The material of the carrier 51 is not particularly limited and may be a polymer-based substrate, for example.

The substrate 21 can be removed using various techniques for removing conventional growth substrates, such as laser lift-off, chemical lift-off, or stress lift-off.

2, a wavelength conversion layer 63 is formed on a support substrate 61. [ The support substrate 61 may be a glass substrate, a quartz substrate, a silicon carbide substrate, or the like, which can transmit light.

The wavelength conversion layer 63 may be deposited or coated on the holding substrate 61, and may have a uniform thickness. The wavelength conversion layer 63 may contain a phosphor for wavelength-converting the light generated in the active layer 25. Furthermore, the wavelength converting layer 63 may be a sintered body of the phosphor, but may also include an inorganic binder.

The wavelength conversion layer 63 can be deposited or coated by various methods such as aerosol, pulsed laser deposition (PLD), printing, spin coating using SOG (spin-on-glass) .

The step of forming the wavelength conversion layer 63 on the supporting substrate 61 may be performed before or after removing the substrate 21 from the semiconductor layers 23,

3 (a), a support substrate 61 having a wavelength conversion layer 63 formed thereon is attached to the semiconductor layers 23, 25, and 27 described with reference to FIG. 1 (b). The support substrate 61 may be attached to the semiconductor layers 23, 25, 27 using an adhesive layer 65. For example, SOG is coated on the first conductive type semiconductor layer 23 and / or the wavelength conversion layer 63 and prebaking the coated SOG at 150 to 250 ° C. Thereafter, after the first conductivity type semiconductor layer 23 and the wavelength conversion layer 63 are in close contact with each other with the SOG therebetween, the SOG can be hard baked at a high temperature, for example, 400 to 600 ° C have. Accordingly, the semiconductor layers 23, 25, and 27 can be attached to the support substrate 61 by the SOG adhesive layer 65. [

Referring to FIG. 3 (b), after the support substrate 61 is attached, the carrier 51 is removed. When the carrier 51 is a polymer, the carrier 51 can be easily removed using an organic solvent.

Thus, the wafer on which the support substrate 61 and the wavelength conversion layer 63 are attached is provided instead of the growth substrate 21. [ This wafer is formed on the support substrate 61, the wavelength conversion layer 63, and the adhesive layer 65 in comparison with the structure of Fig. 1 (a) in which the semiconductor layers 23, 25, There is a difference in that the substrate 21 is replaced. However, the wafer has a laminated structure of the semiconductor layers 23, 25 and 27, which are the same as in Fig. 1 (a).

The wafer-level light emitting diode package can be manufactured using this wafer. Hereinafter, a method of manufacturing a light emitting diode package by performing a wafer level process will be described in detail as an embodiment of the present invention. This method provides a light emitting diode package that can be mounted on a printed circuit board or the like using a solder paste containing Sn in an amount of 50 wt% or more based on the total metal weight.

Referring to FIG. 4, a preliminary insulating layer 29 may be formed on the second conductive semiconductor layer 27. The preliminary insulating layer 29 may be formed of SiO ₂ using, for example, a chemical vapor deposition technique.

Then, a photoresist pattern 30 is formed. The photoresist pattern 30 is patterned to have openings 30a for forming a reflective electrode structure. The openings 30a are formed so that the width of the bottom portion is larger than the width of the inlet. By using the negative type photoresist, the photoresist pattern 30 having the openings 30a having the above-described shape can be easily formed.

Referring to FIG. 5, the pre-oxidized layer 29 is etched using the photoresist pattern 30 as an etch mask. The pre-oxide layer 29 may be etched using a wet etching technique. The pre-oxidized layer 29 in the openings 30a of the photoresist pattern 30 is etched to form openings 29a of the pre-oxidized layer 29 that expose the second conductivity type semiconductor layer 27 . The openings 29a generally have an area similar to or larger than the bottom area of the openings 30a of the photoresist pattern 30.

Referring to FIG. 6, a reflective electrode structure 35 is then formed using a lift-off technique. The reflective electrode structure 35 may include a reflective metal portion 31, a capping metal portion 32, and an anti-oxidation metal portion 33. The reflective metal portion 31 includes a reflective layer and may include a stress relief layer between the reflective metal portion 31 and the capping metal portion 32. The stress relieving layer relaxes the stress due to the difference in thermal expansion coefficient between the reflective metal portion 31 and the capping metal portion 32.

The reflective metal portion 31 may be formed of Ni / Ag / Ni / Au, for example, and may have a total thickness of about 1600 ANGSTROM. The reflecting metal portion 31 is formed such that the side surface is inclined, that is, the bottom portion has a relatively wider shape as shown in the figure. The reflective metal portion 31 may be formed using an electron-beam evaporation method.

On the other hand, the capping metal portion 32 covers the upper surface and the side surface of the reflective metal portion 31 to protect the reflective metal portion 31. The capping metal portion 32 may be formed using sputtering techniques or by using an electron-beam evaporation method (e. G., Planetary e-beam evaporation) in which the substrate 21 is tilted and rotated and vacuum deposited. The capping metal portion 32 may comprise Ni, Pt, Ti, or Cr and may be formed, for example, by depositing about 5 pairs of Ni / Pt or about 5 pairs of Ni / Ti. Alternatively, the capping metal portion 32 may comprise TiW, W, or Mo.

The stress relieving layer may be variously selected depending on the metal material of the reflective layer and the capping metal portion 32. [ For example, when the reflective layer is Al or Al alloy and the capping metal portion 32 comprises W, TiW or Mo, the stress relieving layer may be a single layer of Ag, Cu, Ni, Pt, Ti, Rh, Or a composite layer of Cu, Ni, Pt, Ti, Rh, Pd or Au. When the reflective layer 142 is Al or an Al alloy and the capping metal portion 32 is Cr, Pt, Rh, Pd or Ni, the stress relieving layer may be a single layer of Ag or Cu, Ag.

The stress relieving layer may be a single layer of Cu, Ni, Pt, Ti, Rh, Pd or Cr, or may be a single layer of Cu , Ni, Pt, Ti, Rh, Pd, Cr, or Au. When the reflective layer is Ag or Ag alloy and the capping metal portion 32 is Cr or Ni, the stress relieving layer may be a single layer of Cu, Cr, Rh, Pd, TiW or Ti, or a composite of Ni, Layer.

Further, the anti-oxidation metal portion 33 includes Au to prevent oxidation of the capping metal portion 32, and may be formed of Au / Ni or Au / Ti, for example. Ti is preferred because the adhesion of the oxide layer such as SiO ₂ is good. The anti-oxidation metal part 33 may also be formed using sputtering or an electron-beam evaporation method (e. G., Planetary e-beam evaporation) in which the substrate 21 is tilted and rotated and vacuum deposited.

After the reflective metal structure 35 is deposited, the photoresist pattern 30 is removed to leave the reflective metal structure 35 on the second conductive type semiconductor layer 27 as shown in FIG.

Referring to FIG. 7, a plurality of mesas M spaced from each other are formed on the first conductive semiconductor layer 23. The plurality of mesas M each include an active layer 25 and a second conductivity type semiconductor layer 27. The active layer 25 is located between the first conductivity type semiconductor layer 23 and the second conductivity type semiconductor layer 27. [ On the other hand, the reflective electrode structures 35 are positioned on the plurality of mesas M, respectively.

The plurality of mesas M may be formed by patterning the second conductivity type semiconductor layer 27 and the active layer 25 so that the first conductivity type semiconductor layer 23 is exposed. The sides of the plurality of mesas M may be formed obliquely by using a technique such as photoresist reflow. The inclined profile of the mesa (M) side improves the extraction efficiency of the light generated in the active layer 25.

The plurality of mesas M may have an elongated shape extending parallel to each other in one direction as shown. This shape simplifies the formation of a plurality of mesas M of the same shape in a plurality of chip areas on the substrate 21. [

The reflective electrode structures 35 substantially cover the upper surface of the mesa M and have substantially the same shape as the planar shape of the mesa M. [

During the etching of the second conductive type semiconductor layer 27 and the active layer 25, the pre-oxidized layer 29 remaining thereon is also partially etched and removed. On the other hand, the pre-oxidized layer 29 may remain on the mesa M near the edge of the reflective electrode structure 35, but the pre-oxidized layer 29 may be removed through a wet etching process or the like. Alternatively, the pre-oxidized layer 29 may be removed before forming the mesas M.

Referring to FIG. 8, after the plurality of mesas M are formed, the first conductive semiconductor layer 23 may be etched to separate light emitting diode regions on a chip-by-chip basis. Thus, the adhesive layer 65 or the wavelength conversion layer 63 can be exposed near the edge of the first conductivity type semiconductor layer 23.

The plurality of mesas M may be formed to be confined within the upper region of the first conductivity type semiconductor layer 23 as shown in FIG. That is, a plurality of mesas M may be located on the upper region of the first conductivity type semiconductor layer 23 in an island shape. Alternatively, the mesa M extending in one direction may be formed to reach the upper edge of the first conductive type semiconductor layer 23 shown in FIG. That is, one edge of the lower surface of the plurality of mesas M may be aligned with one edge of the first conductive semiconductor layer 23.

Referring to FIG. 9, a lower insulating layer 37 covering the plurality of mesas M and the first conductive semiconductor layer 23 is formed. The lower insulating layer 37 has openings 37a and 37b for allowing electrical connection to the first conductivity type semiconductor layer 23 and the second conductivity type semiconductor layer 27 in a specific region. For example, the lower insulating layer 37 may have openings 37b exposing the first conductivity type semiconductor layer 23 and openings 37a exposing the reflective electrode structures 35.

The openings 37a are located on the upper side of the mesa M and are biased to the same end side of the mesa. On the other hand, the openings 37b may be located near the region between the mesas M and the edge of the substrate 21, and may have an elongated shape extending along the mesa M.

The lower insulating layer 37 may be formed of an oxide film such as SiO ₂ , a nitride film such as SiNx, or an insulating film of MgF ₂ using a technique such as chemical vapor deposition (CVD). The lower insulating layer 37 may have a thickness of 4000 to 12000 ANGSTROM, for example. The lower insulating layer 37 may be formed as a single layer, but is not limited thereto and may be formed in multiple layers. Further, the lower insulating layer 37 may be formed of a distributed Bragg reflector (DBR) in which a low refractive material layer and a high refractive material layer are alternately laminated. For example, an insulating reflection layer having a high reflectance can be formed by laminating SiO ₂ / TiO ₂ or SiO ₂ / Nb ₂ O ₅ layers.

Referring to FIG. 10, a current spreading layer 39 is formed on the lower insulating layer 37. The current spreading layer 39 covers the plurality of mesas M and the first conductivity type semiconductor layer 23. In addition, the current-spreading layer 39 has openings 39a that are located in the respective upper regions of the mesa M and expose the reflective electrode structures 35. The current spreading layer 39 can make an ohmic contact with the first conductive semiconductor layer 23 through the openings 37b of the lower insulating layer 37. [ The current spreading layer 39 is insulated from the plurality of mesas M and the reflective electrodes 35 by the lower insulating layer 37.

The openings 39a of the current spreading layer 39 are formed to have a larger area than the openings 37a of the lower insulating layer 37 so as to prevent the current spreading layer 39 from being connected to the reflective electrode structures 35, Respectively. Therefore, the sidewalls of the openings 39a are located on the lower insulating layer 37.

The current spreading layer 39 is formed on almost the entire region of the substrate 21 except for the openings 39a. Therefore, the current can be easily dispersed through the current dispersion layer 39. The current spreading layer 39 may include a highly reflective metal layer such as an Al layer and the highly reflective metal layer may be formed on an adhesive layer such as Ti, Cr, or Ni. Further, a protective layer of a single layer or a multiple layer structure such as Ni, Cr, Au or the like may be formed on the highly reflective metal layer. The current spreading layer 39 may have a multilayer structure of Cr / Al / Ni / Ti / Ni / Ti / Au / Ti, for example.

Referring to FIG. 11, an upper insulating layer 41 is formed on the current spreading layer 39. The upper insulating layer 41 has openings 41b for exposing the reflective electrode structures 35 together with the openings 41a for exposing the current spreading layer 39. [ The opening 41a may have an elongated shape in a direction perpendicular to the longitudinal direction of the mesa M and has a relatively large area as compared with the openings 41b. The openings 41b expose the exposed reflective electrode structures 35 through the openings 39a of the current spreading layer 39 and the openings 37a of the lower insulating layer 37. [ The openings 41b may have a smaller area than the openings 39a of the current spreading layer 39 and may have a larger area than the openings 37a of the lower insulating layer 37. [ Accordingly, the sidewalls of the openings 39a of the current spreading layer 39 may be covered with the upper insulating layer 41.

The upper insulating layer 41 may be formed of a silicon nitride film to prevent metal elements of the solder paste from diffusing, and may have a thickness of 1 μm or more and 2 μm or less. If it is less than 1 mu m, it is difficult to prevent diffusion of the metal elements of the solder paste.

Referring to FIG. 12, a first electrode pad 43a and a second electrode pad 43b are formed on the upper insulating layer 41. Referring to FIG. The first electrode pad 43a is connected to the current spreading layer 39 through the opening 41a of the upper insulating layer 41 and the second electrode pad 43b is connected to the openings 41b of the upper insulating layer 41 To the reflective electrode structures 35. The first electrode pad 43a and the second electrode pad 43b are used to mount the light emitting diode on the printed circuit board or the like through the solder paste. Therefore, in order to prevent the first electrode pad 43a and the second electrode pad 43b from being short-circuited by the solder paste, the distance D between the electrode pads is preferably about 300 mu m or more.

Meanwhile, the first and second electrode pads 43a and 43b may be formed together in the same process, and may be formed using, for example, a photo and etching technique or a lift-off technique. The first and second electrode pads 43a and 43b may include an anti-solder layer and an anti-oxidation layer, respectively. The anti-solder layer prevents diffusion of the metal elements in the solder paste, and the anti-oxidation layer prevents the anti-solder layer from being oxidized. The anti-solder layer may include Cr, Ti, Ni, Mo, TiW, or W, and the anti-oxidation layer may include Au, Ag, or an organic material layer.

For example, the anti-solder layer may comprise about 5 pairs of Ti / Ni or about 5 pairs of Ti / Cr, and the anti-oxidation layer may comprise Au. By the above structure, the total thickness of the first and second electrode pads 43a and 43b can be reduced to less than 2 占 퐉, and further to less than 1 占 퐉, while preventing diffusion of the metal element of the solder paste.

Referring to Fig. 13, the surface of the support substrate 61 is then processed to form a light extracting pattern 61R on the surface. The light extracting pattern 61R may be formed by patterning the supporting substrate 61 using a photolithography technique. The light extracting pattern 61R reduces the total reflection of light on the surface of the holding substrate 61, thereby improving light extraction efficiency.

Thereafter, the substrate 61 is divided into individual chip units to manufacture light emitting diodes separated from each other. The light emitting diode is a wafer level light emitting diode package and requires no additional packaging process. Further, since the light emitting diode manufactured according to the present embodiment can prevent the diffusion of tin (Sn) in the solder paste, the solder paste containing 50% by weight or more of Sn relative to the total weight of the metal can be used to directly mount the printed circuit board And the like.

In the wafer level light emitting diode package according to the present embodiment, the wavelength conversion layer 63 is positioned between the support substrate 61 and the semiconductor layers 23, 25, Further, the light generated in the active layer 25 is emitted to the outside through the supporting substrate 61. Therefore, all light emitted to the outside through the support substrate 61 passes through the wavelength conversion layer 63.

In the present embodiment, a plurality of mesas M are formed on the first conductivity type semiconductor layer 23, but a single mesa may be formed.

14 to 16 are diagrams for explaining a method of manufacturing a light emitting diode according to yet another embodiment of the present invention, in which (a) is a plan view and (b) is a sectional view taken along the cutting line A-A.

Referring to FIG. 14, a method of fabricating a light emitting diode according to this embodiment is substantially similar to the method of fabricating a light emitting diode described above with reference to FIGS. 1 to 13, but differs in that a diffusion preventive reinforcement layer 40 is further formed.

In the method of manufacturing a light emitting diode according to the present embodiment, a lower insulating layer 37 is formed through a process as described with reference to FIGS. 1 to 9. Thereafter, as described with reference to Fig. 10, the current-spreading layer 39 is formed. At this time, the diffusion preventive reinforcement layer 40 is formed on the reflective electrode structures 35 during formation of the current dispersion layer 39. The anti-image-enhancement layer 40 may be formed of the same material as the current-spreading layer 39 by the same process, and is spaced apart from the current-spreading layer 39.

Referring to Fig. 15, an upper insulating layer 41 is formed thereafter, as described with reference to Fig. At this time, the openings 41b of the upper insulating layer 41 expose the diffusion preventive reinforcing layer 40.

Referring to FIG. 16, first and second electrode pads 43a and 43b are formed as described with reference to FIG. And the second electrode pad 43b is connected to the diffusion preventive reinforcement layer 40. [ Thus, the diffusion preventive reinforcement layer 40 is located between the reflective metal structure 35 and the second electrode pad 43b, and prevents the metal elements of the solder paste from diffusing into the reflective metal structure 35.

Thereafter, the light extraction pattern 61R may be formed on the surface of the support substrate 61 as described with reference to Fig. Thereafter, the supporting substrate 61 is separated into individual chip units to complete the light emitting diode package.

17 to 20 are diagrams for explaining a method of manufacturing a light emitting diode according to yet another embodiment of the present invention, in which (a) is a plan view and (b) is a sectional view taken along the cutting line A-A.

Although the mesas M are formed after forming the reflective electrode structures 35 in the embodiments described above, in the present embodiment, the mesas M are formed before the reflective electrode structures 35 are formed do.

17, a first conductivity type semiconductor layer 23, an active layer 25, and a second conductivity type semiconductor layer are formed on a support substrate 61 on which a wavelength conversion layer 63 is formed through the steps described with reference to FIGS. And the second conductivity type semiconductor layer 27 are located. Then, a plurality of mesas M are formed through a patterning process. Since the mesas M are similar to those described with reference to FIG. 7, a detailed description thereof will be omitted.

Referring to FIG. 18, a pre-oxidized layer 29 is formed to cover the first conductivity type semiconductor layer 23 and the plurality of mesas M. The pre-oxide layer 29 can be formed using the same materials and fabrication techniques as described with reference to Fig. A photoresist pattern 30 having openings 30a on the pre-oxidized layer 29 is formed. The openings 30a of the photoresist pattern 30 are located in the upper region of the mesa M. The photoresist pattern 30 is the same as that described with reference to FIG. 4 except that the photoresist pattern 30 is formed on the supporting substrate 61 on which the mesas M are formed, and thus a detailed description thereof will be omitted.

19, the pre-oxidized layer 29 is etched using the photoresist pattern 30 as an etch mask, thereby forming openings 29a for exposing the second conductive type semiconductor layer 27 .

Referring to FIG. 20, a reflective electrode structure 35 is then formed on each of the mesas M using a lift-off technique, as described in detail with reference to FIG. Thereafter, the light emitting diode can be manufactured through the steps described with reference to FIGS. 8 to 13.

According to the present embodiment, since the mesa M is formed before the reflective electrode structure 35, the pre-oxidized layer 29 can remain in the region between the side of the mesa M and the mesa M . The pre-oxidized layer 29 is then covered with a lower insulating layer 39 and patterned with a lower insulating layer 39.

As in the present embodiment, the process sequence for manufacturing the light emitting diode can be variously modified. For example, the process of isolating the light emitting diode regions (ISO process) may be performed before forming the mesas M or before forming the reflective electrode structures 35.

21 is a cross-sectional view illustrating a method of fabricating a light emitting diode according to another embodiment of the present invention.

In the foregoing embodiments, the support substrate 61 is shown attached to the surface of the first conductive type semiconductor layer 23 which is relatively flat. However, the rough surface 23R may be formed on the surface of the first conductivity type semiconductor layer 23 and the support substrate 61 may be attached on the rough surface 23R through the adhesive layer 65 have.

The rough surface 23R increases the surface area of the first conductivity type semiconductor layer 23 and improves the adhesion. Furthermore, it is possible to prevent total internal total reflection of light traveling from the active layer 25 to the side of the support substrate 61, thereby improving light extraction efficiency.

The roughened surface 23R may be formed by dry or wet etching the surface of the exposed first conductivity type semiconductor layer 23 after the substrate 21 is removed.

Thereafter, after the carrier 51 is removed as described with reference to Fig. 3 (b), the wafer-level light emitting diode package can be provided through the wafer-level process according to the previous embodiments using this wafer.

22 is a cross-sectional view illustrating a method of fabricating a light emitting diode according to another embodiment of the present invention.

The wavelength conversion layer 63 is formed on the support substrate 61 and the wavelength conversion layer 63 is formed on the semiconductor layers 23 and 25 through the adhesive layer 65. In this case, , 27 (see Fig. 3 (a)), but in this embodiment, the adhesive layer and the wavelength conversion layer 73 are integrated into one.

That is, in this embodiment, the wavelength conversion layer 73 is also an adhesive layer, and the fluorescent material is distributed in the adhesive layer 73. For example, SOG mixed with a phosphor is coated on the supporting substrate 61 and / or the first conductivity type semiconductor layer 23, and prebaking is performed. Thereafter, the support substrate 61 and the first conductivity type semiconductor layer 23 are brought into close contact with each other with the SOG prebaked therebetween, and then the SOG hard baking is performed at a high temperature. Thus, the semiconductor layers 23, 25, and 27 can be attached to the support substrate 61 by the SOG adhesive layer 73. [ Furthermore, because the phosphor is distributed in the adhesive layer 73, it can function as a wavelength conversion layer.

Thereafter, after the carrier 51 is removed as described with reference to Fig. 3 (b), the wafer-level light emitting diode package can be provided through the wafer-level process according to the previous embodiments using this wafer.

According to this embodiment, the distance between the wavelength conversion layer 73 and the active layer 25 is closer to that of the above embodiments, and therefore, the light emitted without the wavelength conversion through the side surface of the adhesive layer 65 Can be reduced.

In the foregoing embodiments, a wafer level light emitting diode package and a method of manufacturing it are described. Unlike a light emitting diode chip, a wafer level light emitting diode package can be directly mounted on a printed circuit board or the like to fabricate a light emitting diode module. However, the present invention does not exclude the mounting of the wafer level light emitting diode package again on a package housing or the like. The wafer level light emitting diode package may be mounted on another package housing or the like. Therefore, the technical features of the present invention can be applied to fabricate a light emitting diode chip including a wavelength conversion layer. Therefore, the present invention should not be construed as being limited only to a wafer level light emitting diode package.

Claims (23)

A support substrate;
A semiconductor stacked structure located on the support substrate and including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer; And
And a wavelength conversion layer disposed between the support substrate and the first conductive type semiconductor layer. The method according to claim 1,
Wherein the wavelength conversion layer is in direct contact with the semiconductor laminated structure. The method of claim 2,
Wherein the wavelength conversion layer comprises a SOG containing a phosphor. The method according to claim 1,
And an adhesive layer disposed between the wavelength conversion layer and the first conductive type semiconductor layer. The method of claim 4,
Wherein the adhesive layer comprises SOG. The method according to claim 1,
And the first conductivity type semiconductor layer has a rough surface on the side of the wavelength conversion layer. The method according to claim 1,
Wherein the first conductivity type semiconductor layer includes a plurality of mesas, and the plurality of mesas include the active layer and the second conductivity type semiconductor layer, respectively. The method of claim 7,
A first electrode pad electrically connected to the first conductivity type semiconductor layer; And
And a second electrode pad electrically connected to the second conductivity type semiconductor layer of each of the mesas,
Wherein the first electrode pad and the second electrode pad each include a solder preventing layer and an oxidation preventing layer. The method of claim 8,
A reflective electrode structure positioned on the mesas, respectively; And
A plurality of mesas and a first conductivity type semiconductor layer disposed on the first conductivity type semiconductor layer, wherein the plurality of mesas and the first conductivity type semiconductor layer have openings that are located in the respective mesa upper regions and expose the reflective electrode structures, Further comprising a current-dispersive layer insulated from the current-
The first electrode pad is electrically connected to the current dispersion layer,
And the second electrode pad is electrically connected to the reflective electrode structures. The method of claim 9,
Further comprising an upper insulating layer covering at least a portion of the current spreading layer, the upper insulating layer having openings exposing the reflective electrode structures,
Wherein the second electrode pad is located on the upper insulating layer and is electrically connected to the reflective electrode structures exposed through the openings of the upper insulating layer. The method of claim 10,
And a diffusion prevention layer located between the reflective electrode structures and the second electrode pad. The method of claim 11,
Wherein the diffusion preventive reinforcement layer is formed of the same material as the current dispersion layer. The method of claim 9,
And a lower insulating layer located between the plurality of mesas and the current dispersion layer to insulate the current dispersion layer from the plurality of mesas,
Wherein the lower insulating layer has openings located within the respective mesa upper regions and exposing the reflective electrode structures. The method according to claim 1,
Wherein the light emitting diode is a wafer level light emitting diode package. A semiconductor multilayer structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer is formed on a substrate,
A carrier is attached to the semiconductor laminated structure,
Removing the substrate from the semiconductor laminated structure,
A wavelength conversion layer is formed on a support substrate,
The supporting substrate is attached to the semiconductor laminated structure such that the wavelength conversion layer and the semiconductor laminated structure face each other,
And removing the carrier. 16. The method of claim 15,
Wherein the supporting substrate is attached to the semiconductor laminated structure by an adhesive layer. 18. The method of claim 16,
Wherein the adhesive layer comprises SOG. 16. The method of claim 15,
Further comprising forming a roughened surface on the surface of the first conductive type semiconductor layer before attaching the supporting substrate. 16. The method of claim 15,
Wherein the light emitting diode is a wafer level light emitting diode package. A semiconductor multilayer structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer is formed on a substrate,
A carrier is attached to the semiconductor laminated structure,
Removing the substrate from the semiconductor laminated structure,
A supporting substrate is attached to the semiconductor laminated structure,
Removing the carrier,
Wherein the supporting substrate is attached to the semiconductor laminated structure by an adhesive layer containing a phosphor. The method of claim 20,
Wherein the adhesive layer comprises SOG containing a phosphor. The method of claim 20,
Further comprising forming a roughened surface on the surface of the first conductive type semiconductor layer before attaching the supporting substrate. The method of claim 20,
Wherein the light emitting diode is a wafer level light emitting diode package.

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