KR20180106720A - Light emitting diode with stack of dbrs - Google Patents

Abstract

A light emitting diode according to an embodiment of the present invention includes: a semiconductor stack including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; and a plurality of distributed Bragg reflectors disposed on one side of the semiconductor stack, wherein the plurality of distributed Bragg reflectors are stacked with different areas., an emission light directing pattern of the light emitting diode can be adjusted by using the distributed Bragg reflectors. Accordingly, the present invention can omit a lens.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a light emitting diode (LED) having a distributed Bragg reflector laminate,

The present invention relates to a light emitting diode, and more particularly to a light emitting diode having a distributed Bragg reflector laminate.

In general, nitrides of a Group III element such as gallium nitride (GaN) and aluminum nitride (AlN) have excellent thermal stability and have a direct bandgap energy band structure. Recently, nitride materials for visible light and ultraviolet Has received a lot of attention. In particular, blue and green light emitting diodes using indium gallium nitride (InGaN) are utilized in various applications such as large-scale color flat panel displays, traffic lights, indoor lighting, high density light sources, high resolution output systems and optical communication.

Light emitting diodes are generally used in packages through a packaging process, and lenses have been used together to control the directional pattern of the emitted light.

 2. Description of the Related Art In recent years, light emitting diodes are being studied in the form of a chip scale package in which a packaging process is performed at a chip level. Such a light emitting diode is smaller in size than a general package and does not require a separate packaging process, which further simplifies the process and saves time and money. The light emitting diode in the form of a chip scale package generally has a flip-chip electrode structure and is excellent in heat radiation characteristics.

On the other hand, the size of the light emitting module is increased because the lens used for adjusting the directing pattern of the emitted light is relatively larger than the light emitting diode. Further, since the lens is provided separately from the light emitting diode, adjustment of the directivity pattern using the lens is not suitable for the light emitting diode technology trend to simplify the process.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a light emitting diode capable of adjusting a light directing pattern without using a lens.

Another object of the present invention is to provide a flip chip structure light emitting diode in the form of a chip scale package.

A light emitting diode according to an embodiment of the present invention includes: a semiconductor stacked body including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; And a plurality of distributed Bragg reflectors disposed on one side of the semiconductor stack, wherein the plurality of distributed Bragg reflectors are stacked with different areas.

According to another embodiment of the present invention, there is provided a light emitting diode comprising: a semiconductor stacked body including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; And a stack of distributed Bragg reflectors disposed on one side of the semiconductor stack, wherein the stack of distributed Bragg reflectors comprises regions of different thickness, and wherein the stack of distributed Bragg reflectors has a thicker thickness region Lt; RTI ID = 0.0 > reflectivity.

According to embodiments of the present invention, the orientation pattern of the outgoing light can be adjusted through the stacking of the distributed Bragg reflectors, thereby omitting the lens.

Other advantages and effects of the present invention will become more apparent from the detailed description.

1 is a schematic cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.
FIG. 2 is a schematic diagram illustrating an outgoing light directing pattern of a light emitting diode according to an embodiment of the present invention. Referring to FIG.
3A is a schematic plan view illustrating a light emitting diode according to another embodiment of the present invention.
Figure 3b is a schematic cross-sectional view taken along the tear line AA of Figure 3a.
4 to 9 are plan views and sectional views for explaining a method of manufacturing a light emitting diode according to an embodiment of the present invention.
10 is a schematic cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can sufficiently convey the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. It is also to be understood that when an element is referred to as being "above" or "above" another element, But also includes the case where another component is interposed between the two. Like reference numerals designate like elements throughout the specification.

A light emitting diode according to an embodiment of the present invention includes: a semiconductor stacked body including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; And a plurality of distributed Bragg reflectors disposed on one side of the semiconductor stack, wherein the plurality of distributed Bragg reflectors are stacked with different areas.

By stacking distributed Bragg reflectors having different areas, the reflectance can be adjusted according to the position, and thus the directivity pattern of the outgoing light can be adjusted.

On the other hand, the plurality of distributed Bragg reflectors may have a narrow area from the semiconductor laminate. Since the distributed Bragg reflectors have a sequentially narrow area, they can be manufactured relatively easily.

In one embodiment, the plurality of distributed Bragg reflectors may have the same central axis. Accordingly, it is possible to symmetrically form the directing pattern of the emitted light and reduce the amount of light emitted in the direction of the center axis of the light emitting diode.

In another embodiment, the plurality of distributed Bragg reflectors may be stacked such that one side faces are parallel. Thus, the directivity pattern of the emitted light can be formed asymmetrically.

On the other hand, each of the distributed Bragg reflectors may exhibit a reflectance in the range of 5% to 50%. These distributed Bragg reflectors are stacked together to exhibit a higher reflectivity.

The reflectance of the region in which the distributed Bragg reflectors are most overlapped may exhibit a reflectance of 90% or more with respect to the light emitted from the active layer. Also, the reflectance of the least overlapping regions of the distributed Bragg reflectors may exhibit a reflectivity of less than 10%.

The light emitting diode may further include a substrate positioned between the semiconductor stack and the plurality of distributed Bragg reflectors.

The light emitting diode may include: a lower insulating layer covering the semiconductor stacked body, the lower insulating layer including a first opening exposing the first conductive type semiconductor layer of the semiconductor stacked body; And a first metal layer disposed on the lower insulating layer and electrically connected to the first conductive type semiconductor layer through a first opening of the lower insulating layer.

The light emitting diode further includes an ohmic reflective layer disposed on the second conductive semiconductor layer and ohmic-contacting the second conductive semiconductor layer, wherein the lower insulating layer has a second opening exposing the ohmic reflective layer, As shown in FIG.

The light emitting diode may further include: an upper insulating layer covering the first metal layer; Further comprising a first bump pad and a second bump pad which are located on the upper insulating layer and are electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer of the semiconductor laminate, Layer includes a first opening exposing the first metal layer and the first bump pad is connectable to the first metal layer through the first opening.

In some embodiments, the semiconductor stack includes a plurality of light emitting cells spaced apart from each other, and the first metal layer includes a connection portion for electrically connecting the adjacent light emitting cells in series to form a serial array of light emitting cells And a first pad metal layer electrically connected to the first conductive semiconductor layer of the last light emitting cell disposed at the end of the serial array. Thus, it is possible to provide a light emitting diode which can be driven at a high voltage.

The light emitting diode may include an ohmic reflective layer disposed on the second conductivity type semiconductor layer of each light emitting cell and making ohmic contact with the second conductivity type semiconductor layer; And a second pad metal layer disposed on the lower insulating layer and electrically connected to the ohmic reflective layer of the first light emitting cell disposed at the first end of the serial array, And the second pad metal layer may be electrically connected to the ohmic reflective layer on the first light emitting cell through the second opening.

Further, the light emitting diode may include an upper insulating layer covering the connection portion (s), the first and second pad metal layers, and having openings for exposing upper surfaces of the first and second pad metal layers, respectively; And a first bump pad and a second bump pad respectively connected to upper surfaces of the first pad metal layer and the second pad metal layer exposed by the openings of the upper insulating layer. By adopting the second pad metal layer, the first bump pad and the second bump pad can be formed at the same height.

In some embodiments, the first bump pad and the second bump pad may each be disposed over an upper area of two or more light emitting cells. Therefore, the first and second bump pads can be formed relatively large, and the mounting of the light emitting diode can be facilitated.

According to another embodiment of the present invention, there is provided a light emitting diode comprising: a semiconductor stacked body including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; And a stack of distributed Bragg reflectors disposed on one side of the semiconductor stack, wherein the stack of distributed Bragg reflectors comprises regions of different thickness, and wherein the stack of distributed Bragg reflectors has a thicker thickness region Lt; RTI ID = 0.0 > reflectivity.

It is possible to control the directing pattern of the outgoing light by adjusting the thickness of the laminate of the distributed Bragg reflectors.

Furthermore, the stack of distributed Bragg reflectors exhibits the highest reflectance in the center and the lowest reflectance near the edges. Accordingly, the light emitted from the light emitting diode can be dispersed without using a dispersion lens for dispersing the light.

On the other hand, at least a part of the light generated in the active layer can be emitted to the outside through the stack of the distributed Bragg reflectors.

The light emitting diode may further include a substrate disposed between the stack of semiconductor stacks and the distributed Bragg reflectors.

The light emitting diode may further include a first bump pad and a second bump pad disposed on the semiconductor stack and electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer, respectively . Thus, a light emitting diode having a flip chip structure can be provided.

Hereinafter, the present invention will be described in detail with reference to the drawings.

1 is a schematic cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.

1, the light emitting diode includes a substrate 21, a semiconductor laminate 30, a first bump pad 39a and a second bump pad 39b, and a plurality of distributed Bragg reflectors 51, 53, 55, 57, 59).

The substrate 21 may be, for example, a substrate on which a gallium nitride-based semiconductor layer can be grown. The substrate 21 may include a sapphire substrate, a gallium nitride substrate, a SiC substrate, or the like, and may be a patterned sapphire substrate. The substrate 21 may have a rectangular or square planar shape, but is not limited thereto. The size of the substrate 21 is not particularly limited and may be variously selected.

The semiconductor laminated body 30 includes a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, and emits light using the combination of electrons and holes in the active layer. The specific structure of the semiconductor laminate 30 will be described later in detail with reference to Fig.

On the other hand, a first bump pad 39a and a second bump pad 39b are disposed on the semiconductor stack 30, and the first and second bump pads 39a, And the second conductivity type semiconductor layer.

On the other hand, a stack of distributed Bragg reflectors 51 to 59 is disposed on the substrate 21. [ As shown in Fig. 1, a plurality of distributed Bragg reflectors 51 to 59 are stacked with different areas. The first distributed Bragg reflector 51 closest to the substrate 21 may have the same area as the substrate 21, but may be smaller. The first distributed Bragg reflector 51 may be disposed on the substrate 21 such that its central axis coincides with the central axis of the substrate 21. [ In addition, the distributed Bragg reflectors 53 to 59 disposed thereon can be arranged in a narrow area with increasing distance from the substrate 21. Further, as shown in Fig. 1, the central axes of the distributed Bragg reflectors 51 to 59 may be arranged to coincide with each other.

Thus, all of the distributed Bragg reflectors 51 to 59 are stacked on the central region of the substrate 21, and the number of distributed Bragg reflectors stacked on the edge decreases. Thus, the stack of distributed Bragg reflectors 51-59 is thickest in the central region and thinnest near the edges.

The distributed Bragg reflectors 51, 53, 55, 57, and 59 may reflect the light generated in the active layer, respectively, with a reflectance in the range of 5% to 50%. Further, since these distributed Bragg reflectors 51 to 59 are laminated to each other, they exhibit a higher reflectance in a region where the number of layers is large, that is, in a thick region. For example, the central region where all of the distributed Bragg reflectors 51 to 59 are stacked in FIG. 1 can exhibit a reflectance of 90% or more with respect to the light generated in the active layer, and at the edge where only the distributed Bragg reflector 51 is disposed It is possible to exhibit a reflectance of 10% or less.

The distributed Bragg reflectors 51, 53, 55, 57, and 59 each have a structure in which first and second material layers having different refractive indexes are alternately stacked. For example, the first material layer may be a SiO ₂ or MgF _2, the second material layer may be a material having a refractive index higher than that of the first material layer. The second material layer may be, for example, TiO _2, Nb ₂ O ₅ or ZrO _2. The distributed Bragg reflectors 51, 53, 55, 57, 59 may all be formed of the same first and second material layers, but are not limited thereto and may be formed of different first and second material layers . For example, the first distributed Bragg reflector 51 may be formed of SiO2 / TiO2, and the second distributed Bragg reflector may be formed of SiO2 / ZrO2.

The reflectance of the distributed Bragg reflectors can be adjusted by adjusting the types of the first and second material layers constituting the distributed Bragg reflectors 51 to 59, the forming method, the thicknesses of these layers, and the number of layers.

On the other hand, although the side of each of the distributed Bragg reflectors 51 to 59 is shown as being vertical in the drawing, it is not limited thereto. In particular, the side surfaces of the distributed Bragg reflectors 51 to 59 may have an inclination angle within a range of about 20 to 70 degrees with respect to the surface of the substrate 21.

The light generated in the active layer is generally emitted to the outside through the distributed Bragg reflectors 51 to 59. On the semiconductor laminated body 30 on the first bump pad 39a and the second bump pad 39b side, light is emitted to the substrate (not shown) on the substrate 21 in order to emit light through the distributed Bragg reflectors 51 to 59 on the substrate 21 21) may be provided.

According to the present embodiment, it is possible to control the emission amount of the outgoing light by using the laminated structure of the distributed Bragg reflectors 51 to 59. The directional pattern of the emitted light can be adjusted by controlling the amount of light emitted according to the position.

On the other hand, in the present embodiment, although the distributed Bragg reflectors 51 to 59 are described as being disposed on the substrate 21 in opposition to the semiconductor laminate 30, (30). ≪ / RTI > In this case, the light generated in the active layer will be emitted in the direction opposite to the substrate 21 through the distributed Bragg reflectors 51 to 59.

FIG. 2 is a schematic diagram illustrating an outgoing light directing pattern of a light emitting diode according to an embodiment of the present invention. Referring to FIG.

Referring to FIG. 2, as shown in FIG. 1, by arranging the distributed Bragg reflectors 51 to 59 such that the reflectance is high and the reflectance at the edge is low in the central region of the substrate 21, The intensity of the emitted light can be reduced and more light can be emitted with a larger angle of incidence.

Since the directivity pattern of the emitted light can be adjusted by using the distributed Bragg reflectors 51 to 59, the amount of light in the central region can be reduced. Therefore, it is not necessary to use a separate lens such as a dispersion lens used for changing the directing pattern of the light emitting diode.

Further, the light emitting diode can be used without a lens as a light source of a backlight, thereby making the backlight module of the direct-type light emitting module thinner.

3A is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention, and FIG. 3B is a sectional view taken along the cutting line A-A in FIG. 3A.

3A and 3B, the light emitting diode includes a substrate 21, a semiconductor laminate 30, an ohmic reflective layer 31, a lower insulating layer 33, a first pad metal layer 35a, The first bump pad 39a and the second bump pad 39b and the distributed Bragg reflectors 51 to 59 as shown in Fig. The semiconductor laminate 30 includes a first conductivity type semiconductor layer 23, an active layer 25 and a second conductivity type semiconductor layer 27 and may be separated into a plurality of light emitting cells C1 to C7 .

The substrate 21 is not particularly limited as long as it is a substrate capable of growing a gallium nitride-based semiconductor layer. Examples of the substrate 21 include a sapphire substrate, a gallium nitride substrate, a SiC substrate, and the like, and may be a patterned sapphire substrate. The substrate 21 may have a rectangular or square shape as shown in the plan view of FIG. 3A, but is not limited thereto. The size of the substrate 21 is not particularly limited and may be variously selected.

The semiconductor stacked body 30 may be divided into a plurality of light emitting cells C1 to C7. The plurality of light emitting cells C1 to C7 are arranged on the substrate 21 so as to be spaced apart from each other. Although seven light emitting cells (C1 to C7) are shown in this embodiment, the number of light emitting cells can be adjusted. Although the semiconductor stacked body 30 is described as being divided into the plurality of light emitting cells C1 to C7 in this embodiment, it may be a single light emitting cell which is not separated.

Each of the light emitting cells C1 to C7 includes a first conductivity type semiconductor layer 23. The first conductive type semiconductor layer 23 is disposed on the substrate 21. The first conductivity type semiconductor layer 23 may be a layer grown on the substrate 21 and may be a gallium nitride based semiconductor layer doped with an impurity such as Si.

The active layer 25 and the second conductivity type semiconductor layer 27 are disposed on the first conductivity type semiconductor layer 23. The active layer 25 is disposed between the first conductivity type semiconductor layer 23 and the second conductivity type semiconductor layer 27. The active layer 25 and the second conductivity type semiconductor layer 27 may have a smaller area than the first conductivity type semiconductor layer 23. The active layer 25 and the second conductivity type semiconductor layer 27 may be located on the first conductivity type semiconductor layer 23 in a mesa form by mesa etching.

The edges of the first conductivity type semiconductor layer 23 and the mesas such as the active layer 25 and the second conductivity type semiconductor layer 23 at the edges adjacent to the edge of the substrate 21 among the edges of the light emitting cells C1- The marginal portions of the projections 27 may be spaced apart from each other. That is, a part of the upper surface of the first conductivity type semiconductor layer 23 is exposed to the outside of the mesa. The active layer 25 is spaced farther from the edge of the substrate 21 than the first conductivity type semiconductor layer 23 and thus the active layer 25 can be prevented from being damaged during the substrate separation process by laser.

The edges of the first conductivity type semiconductor layer 23 and the edges of the active layer 25 and the second conductivity type semiconductor layer 27, which are adjacent to the light emitting cells of the light emitting cells C1 to C7, May be positioned on the same inclined plane. Therefore, the upper surface of the first conductive type semiconductor layer 23 may not be exposed on the side where the light emitting cells face each other. As a result, the light emitting area of the light emitting cells C1 to C7 can be secured.

The active layer 25 may have a single quantum well structure or a multiple quantum well structure. The composition and thickness of the well layer in the active layer 25 determine the wavelength of the generated light. In particular, by controlling the composition of the well layer, it is possible to provide an active layer that generates ultraviolet light, blue light or green light.

On the other hand, the second conductivity type semiconductor layer 27 may be a p-type impurity, for example, a gallium nitride based semiconductor layer doped with Mg. Although the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27 may each be a single layer, the present invention is not limited thereto, and may be a multiple layer or a superlattice layer. The first conductivity type semiconductor layer 23, the active layer 25 and the second conductivity type semiconductor layer 27 are formed by a known method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) And may be formed on the substrate 21 by growing.

The light emitting cells C1 to C7 have through holes 30a that penetrate the second conductive semiconductor layer 27 and the active layer 23 and expose the first conductive semiconductor layer 23, respectively. The through holes 30a are surrounded by the second conductivity type semiconductor layer 27 and the active layer 25. As shown in the figure, the through holes 30a may be arranged in the central region of the light emitting cells C1 to C7 and may have an elongated shape. However, the present invention is not limited thereto, and a plurality of through holes may be formed in each light emitting cell.

On the other hand, the ohmic reflective layer 31 is disposed on the second conductivity type semiconductor layer 27 and electrically connected to the second conductivity type semiconductor layer 27. The ohmic reflective layer 31 may be disposed over substantially the entire region of the second conductivity type semiconductor layer 27 in the upper region of the second conductivity type semiconductor layer 27. For example, the ohmic reflective layer 31 may cover 80% or more, and more preferably 90% or more of the area above the second conductivity type semiconductor layer 27.

The OMR reflective layer 31 may include a reflective metal layer so that the light generated in the active layer 25 and traveling to the OMR reflective layer 31 can be reflected to the substrate 21 side. For example, the ohmic reflective layer 31 may be formed of a single reflective metallic layer, but is not limited thereto, and may include an ohmic layer and a reflective layer. As the ohmic layer, a metal layer such as Ni or a transparent oxide layer such as indium tin oxide (ITO) may be used. As the reflective layer, a metal layer having high reflectance such as Ag or Al may be used.

The lower insulating layer 33 covers the light emitting cells C1 to C7 and the ohmic reflective layer 31. [ The lower insulating layer 33 may cover not only the upper surface of the light emitting cells C1 to C7 but also the side surfaces of the light emitting cells C1 to C7 along the periphery of the light emitting cells C1 to C7, 21 may be partially covered. The lower insulating layer 33 covers the cell isolation region ISO between the light emitting cells C1 to C7 and further exposes the first conductivity type semiconductor layer 23 exposed in the through holes 30a to the partial Respectively.

The lower insulating layer 33 has first openings 33a for exposing the first conductive type semiconductor layer and second openings 33b for exposing the ohmic reflective layers 31. [ The first opening 33a exposes the first conductive type semiconductor layer 23 in the through hole 30a and exposes the upper surface of the substrate 21 along the edge of the substrate 21. [

The second opening 33b is located above the OMR reflective layer 31 to expose the OMR reflective layer 31. The position and shape of the second openings 33b may be variously modified for arranging the light emitting cells C1 to C7 and for electrical connection. 1, one second opening 33b is disposed on each light emitting cell, but a plurality of second openings 33b may be disposed on each light emitting cell.

On the other hand, the lower insulating layer 33 may be formed of a single layer such as a silicon oxide film or a silicon nitride film. In addition, the lower insulating layer 33 may be formed of multiple layers, and in particular, may have a laminated structure in which a first material layer having a first refractive index and a second material layer having a second refractive index are alternately laminated. In particular, the lower insulating layer 33 may be a distributed Bragg reflector having a high reflectance in a specific wavelength band through such a laminated structure. Here, the first material layer may be SiO ₂ or MgF ₂ , and the second material layer may be a material layer having a higher refractive index than the first material layer. The second material layer may be, for example, TiO _2, Nb ₂ O ₅ or ZrO _2. In particular, the first material layer may be formed of a SiO ₂ layer and the second material layer may be formed of a ZrO ₂ layer, thereby improving moisture resistance of the lower insulating layer 33.

On the other hand, the first pad metal layer 35a, the second pad metal layer 35b, and the connection portions 35ab are disposed on the lower insulating layer 33. The second pad metal layer 35a is located above the first light emitting cell C1 and the first pad metal layer 35b is located above the last light emitting cell C7. On the other hand, the connection portions 35ab are located over the neighboring two light emitting cells, and electrically connect the light emitting cells C1 to C7 in series. Thus, the seven light emitting cells C1 to C7 are connected in series by the connection portions 35ab to form a serial array. Here, the first light emitting cell C1 is located at the first end of the serial array, and the seventh light emitting cell C7, which is the last light emitting cell, is located at the end of the serial array.

The first pad metal layer 35a is formed in the upper region of the last light emitting cell C7 and further in the upper region of the second conductive semiconductor layer 27 of the last light emitting cell C7, As shown in FIG. The first pad metal layer 35a is also electrically connected to the first conductivity type semiconductor layer 23 of the last light emitting cell C7 through the first opening 33a of the lower insulating layer 33. [ The first pad metal layer 35a may directly contact the first conductivity type semiconductor layer 23 through the first opening 33a.

The second pad metal layer 35b may be located within the upper region of the first light emitting cell C1 and further within the upper region of the second conductive semiconductor layer 27 of the first light emitting cell C1 have. The second pad metal layer 35b is electrically connected to the ohmic reflective layer 31 on the first light emitting cell C1 through the second opening 33b of the lower insulating layer 33. [ The second pad metal layer 35b can directly contact the ohmic reflective layer 31 through the second opening 33b.

The second pad metal layer 35b may be surrounded by the connection portion 35ab so that a boundary region surrounding the second pad metal layer 35b is formed between the second pad metal layer 35b and the connection portion 35ab . This boundary region exposes the lower insulating layer 33.

Meanwhile, the connection portions 35ab electrically connect neighboring light emitting cells. Each of the connecting portions 35ab is electrically connected to the first conductive semiconductor layer 23 of one light emitting cell and the ohmic reflective layer 31 of the neighboring light emitting cell and thus the second conductive semiconductor layer 27, And these light emitting cells are connected in series. More specifically, the connection portions 35ab can be electrically connected to the first conductive type semiconductor layer 23 exposed through the first opening 33a of the lower insulating layer 33, and the second opening 33b And can be electrically connected to the exposed ohmic reflective layer 31 through the opening. Furthermore, the connection portions 35ab may directly contact the first conductivity type semiconductor layer 23 and the ohmic reflective layer 31. [

Each connecting portion 35ab passes the cell separation region ISO between the light emitting cells. Each of the connection portions 35ab may pass only one upper edge region of the plurality of edges of the first conductive type semiconductor layer 23. [ Accordingly, the area of the connection portion 35ab located above the cell isolation region ISO can be reduced. Further, all the remaining portions except for the connecting portion 35ab passing through the cell isolation region ISO are limited to the upper portion of the light emitting cells region to connect the neighboring light emitting cells. For example, the light emitting cells C1 to C7 may each have a rectangular shape as shown in Fig. 3A, and thus have four edges. The connection portion 35ab may pass through only one edge upper region of the edges of one light emitting cell and may be spaced from the upper region of the remaining edges of the light emitting cell. However, the present invention is not limited thereto, and the connection portions 35ab may cover two or more side surfaces of the light emitting cells, and may cover the cell separation regions around the four sides of the light emitting cells.

The first pad metal layer 35a, the second pad metal layer 35b and the connecting portions 35ab may be formed together with the same material in the same process after the lower insulating layer 33 is formed, can do. The first pad metal layer 35a, the second pad metal layer 35b and the connection portions 35ab may include portions located on the lower insulating layer 33, though not necessarily limited thereto.

The first and second pad metal layers 35a and 35b and the connecting portion 35ab may include a reflective layer such as an Al layer and the reflective layer may be formed on an adhesive layer such as Ti, Cr, or Ni. Further, a protective layer of a single layer or a multiple layer structure such as Ni, Cr, Au, etc. may be formed on the reflective layer. The first and second pad metal layers 35a and 35b and the connection portions 35ab may have a multilayer structure of Cr / Al / Ni / Ti / Ni / Ti / Au / Ti, for example.

The upper insulating layer 37 covers the first and second pad metal layers 35a and 35b and the connection portions 35ab. The upper insulating layer 37 may cover the edge of the lower insulating layer 33 along the light emitting cells C1 to C7. However, the upper insulating layer 37 may expose the upper surface of the substrate 21 along the edge of the substrate 21.

In one embodiment, the shortest distance from the edge of the upper insulating layer 37 to the connecting portions 35ab may be about 15um or more to prevent water from penetrating and damaging the connecting portions 35ab.

The upper insulating layer 37 has a first opening 37a exposing the first pad metal layer 35a and a second opening 37b exposing the second pad metal layer 35b. The first opening 37a and the second opening 37b are disposed in the area above the last light emitting cell C7 and the first light emitting cell C1, respectively. Except for the first and second openings 37a and 37b, other regions of the light emitting cells C1 to C7 may be covered with the upper insulating layer 37. [ Therefore, both the upper surface and the side surface of the connection portions 35ab can be covered with the upper insulating layer 37 and sealed.

In one embodiment, the second opening 37b of the upper insulating layer 37 may be laterally spaced apart so as not to overlap the second opening 33b of the lower insulating layer 33. This prevents the solder from diffusing into the second opening 33b of the lower insulating layer 33 even if the solder penetrates through the second opening 37b of the upper insulating layer 37, So that contamination of the reflective layer 31 can be prevented. However, the present invention is not limited thereto, and the second opening 37b of the upper insulating layer 37 may be arranged to overlap with the second opening 33b of the lower insulating layer 33. [

The upper insulating layer 37 may be formed of a single layer of SiO ₂ or Si ₃ N ₄ , but is not limited thereto. For example, the upper insulating layer 37 may have a multi-layer structure in which a first material layer having a first refractive index and a second material layer having a second refractive index are alternately stacked, similarly to the lower insulating layer 33 . For example, the first material layer may be a SiO ₂ or MgF _2, the second material layer may be a material having a refractive index higher than that of the first material layer. The second material layer may be, for example, TiO _2, Nb ₂ O ₅ or ZrO _2. In particular, the first material layer may be formed of a SiO ₂ layer and the second material layer may be formed of a ZrO ₂ layer. Thus, a light-emitting diode having high humidity resistance can be provided. In particular, the upper insulating layer may be a distributed Bragg reflector.

On the other hand, the first bump pad 39a is in electrical contact with the first pad metal layer 35a exposed through the first opening 37a of the upper insulating layer 37, and the second bump pad 39b is electrically connected to the second And can be electrically connected to the second pad metal layer 35b exposed through the opening 37b. The first bump pad 39a covers and seals the first openings 37a of the upper insulating layer 37 and the second bump pad 39b covers the second openings 37b of the upper insulating layer 37 Cover all.

Further, as shown in FIG. 3A, the first and second bump pads 39a and 39b may be disposed over a plurality of light emitting cells. 3A, the first bump pad 39a is disposed over the upper area of the second, third, fifth, sixth, and seventh light emitting cells C2, C3, C5, C6, and C7, The bump pad 39b is disposed over the upper area of the first, fourth, fifth, and sixth light emitting cells C1, C4, C5, and C6. Accordingly, the first and second bump pads 39a and 39b can be formed relatively large, and thus the mounting process of the light emitting diode can be assisted.

The first bump pad 39a and the second bump pad 39b are formed of a material suitable for bonding as a part bonded to a submount, a printed circuit board, or the like. For example, the first and second bump pads 39a and 39b may comprise an Au layer or an AuSn layer.

On the other hand, the distributed Bragg reflectors 51 to 59 are disposed on the substrate 21 in opposition to the semiconductor stack 30. Since the distributed Bragg reflectors 51 to 59 are as described with reference to Figs. 1 and 2, detailed description thereof is omitted here.

Although the light emitting diode having seven light emitting cells C1 to C7 has been described above, the number of light emitting cells may be larger or smaller. Furthermore, the light emitting diode may include a single light emitting cell, in which case the connection portion 35ab is not required.

Meanwhile, the structure of the light emitting diode will be described more clearly through the light emitting diode manufacturing method described below.

FIGS. 4 to 9 are schematic plan views and sectional views for explaining a method of manufacturing the light emitting diode according to the embodiment of FIG. 3A. In each of the drawings, a is a plan view and b is a cross-sectional view taken along a perforated line A-A of each plan view.

4A and 4B, a semiconductor multilayer body 30 including a first conductivity type semiconductor layer 23, an active layer 25, and a second conductivity type semiconductor layer 27 is formed on a substrate 21, . The substrate 21 may be a sapphire substrate, a silicon carbide substrate, a gallium nitride (GaN) substrate, a spinel substrate, or the like as a substrate on which the gallium nitride based semiconductor layer can be grown. In particular, the substrate 21 may be a patterned substrate such as a patterned sapphire substrate.

The first conductivity type semiconductor layer 23 may include, for example, an n-type gallium nitride layer and the second conductivity type semiconductor layer 27 may include a p-type gallium nitride layer. In addition, the active layer 25 may be a single quantum well structure or a multiple quantum well structure, and may include a well layer and a barrier layer. Further, the well layer may have its compositional element selected depending on the wavelength of the required light, and may include AlGaN, GaN, or InGaN, for example.

Subsequently, the semiconductor laminate 30 is patterned to form a plurality of light emitting cells C1 to C7. For example, a mesa formation process for exposing the top surface of the first conductivity type semiconductor layer 23 and a cell separation process for forming the cell isolation region ISO may be performed using a photolithography and etching process.

The light emitting cells C1 to C7 are spaced apart from each other by a cell isolation region ISO and have through holes 30a, respectively. As shown in FIG. 4B, the sidewalls of the cell isolation region ISO and the sidewalls of the through holes 30a may be inclined.

On the other hand, the upper surface of the first conductivity type semiconductor layer 23 of each light emitting cell is exposed by the mesa etching process. The through holes 30a may be formed together in the mesa etching process. However, the top surface of the first conductivity type semiconductor layer 23 may be exposed along the periphery of the second conductivity type semiconductor layer 27 and the active layer 23, but the present invention is not limited thereto. The top surface of the first conductivity type semiconductor layer 23 is exposed near the edges of the light emitting cells C1 to C7 located near the edge of the substrate 21 as shown in Figs. 4A and 4B, The second conductivity type semiconductor layer 27, the active layer 23 and the first conductivity type semiconductor layer 23 may be continuous slopes in the vicinity of the edges of the first conductivity type semiconductor layer 23, The upper surface may not be exposed. In certain embodiments, there may be an isolated light emitting cell surrounded by the light emitting cells, wherein the edges of the isolated light emitting cell are spaced from the edge of the substrate 21. In this case, the first conductivity type semiconductor layer 23 of the isolated light emitting cell forms a continuous inclined surface together with the second conductivity type semiconductor layer 27 and the active layer 25, and the upper surface exposed near the edge You may not have it at all.

A plurality of light emitting cells C1 to C7 spaced apart from each other by the cell isolation region ISO are formed on the substrate 21 to form a morphology having positions different in height. In this morphology, the upper surface of the second conductivity type semiconductor layer 27 of each light emitting cell is the highest, and the surface of the substrate 21 exposed to the cell separation region ISO is the lowest.

5A and 5B, the ohmic reflective layers 31 are formed on the light emitting cells C1 to C7, respectively. The ohmic reflective layer 31 may be formed using, for example, a lift-off technique. The ohmic reflective layer 31 may be formed as a single layer or a multilayer, and may include, for example, an ohmic layer and a reflective layer. These layers may be formed, for example, using an electron-beam evaporation method. A preliminary insulating layer (not shown) having an opening in an area where the OMR reflective layer 31 is to be formed may be formed before the OMR reflective layer 31 is formed.

In the present embodiment, it is described that the ohmic reflective layer 31 is formed after the light emitting cells C1 to C7 are formed, but the present invention is not limited thereto. For example, the ohmic reflective layer 31 may be formed first, the light emitting cells C1 to C7 may be formed, and a metal layer for the ohmic reflective layer 31 may be deposited on the semiconductor stack 30, The metal layer and the semiconductor lamination layer 30 may be patterned together to form the ohmic reflective layer 31 and the light emitting cells C1 to C7 together.

6A and 6B, a lower insulating layer 33 covering the ohmic reflective layer 31 and the light emitting cells C1 to C7 is formed. The lower insulating layer 33 may be formed of a single layer such as SiO2 or Si3N4. Alternatively, the lower insulating layer 33 may be formed by alternately laminating a first material layer and a second material layer having different refractive indices using a technique such as chemical vapor deposition (CVD). For example, the first material layer may be a SiO ₂ or MgF _2, the second material layer may be a material having a refractive index higher than that of the first material layer. The second material layer may be, for example, TiO _2, Nb ₂ O ₅ or ZrO _2. In particular, the first material layer may be a SiO ₂ layer, for example, and the second material layer may be a ZrO ₂ layer. By adopting the ZrO ₂ layer as the second material layer, the lower insulating layer 33 having high moisture resistance can be provided.

The preliminary insulating layer (not shown) described above can be integrated with the lower insulating layer 33. [ Therefore, the thickness of the lower insulating layer 33 may differ depending on the position due to the pre-insulating layer formed around the OMR reflective layer 31. [ That is, the lower insulating layer 33 on the OMR reflective layer 31 may be thinner than the lower insulating layer 33 around the OMR reflective layer 31.

The lower insulating layer 33 may be patterned through a photolithography and etching process so that the lower insulating layer 33 is patterned to expose the first conductive semiconductor layer 23 in the through holes 30a, And has a second opening 33b having an opening 33a and exposing the ohmic reflective layer 31 on each light emitting cell. Furthermore, the lower insulating layer 33 has a side disposed near the edge of the substrate 21. [

7A and 7B, a first pad metal layer 35a, a second pad metal layer 35b, and connection portions 35ab are formed on the lower insulating layer 33. In FIG.

The connection portions 35ab electrically connect the first to fourth light emitting cells C1 to C7 to form a serial array of the light emitting cells C1 to C7. The first light emitting cell C1 is located at the first end of the serial array and the seventh light emitting cell C7 is located at the end of the serial array.

In particular, the connection portions 35ab electrically connect the first conductive semiconductor layer 23 of one light emitting cell and the second conductive semiconductor layer 27 of the adjacent light emitting cell. The connection portions 35ab may be electrically connected to the first conductive type semiconductor layer 23 exposed in the through holes 30a through the first openings 33a of the lower insulating layer 33, Can be electrically connected to the exposed ohmic reflective layer (31) through the second openings (33b) of the second electrode (33). Furthermore, the connection portions 35ab can directly contact the first conductive semiconductor layer 23 and the ohmic reflective layer 31. [

The connection portions 35ab pass the cell isolation region ISO to connect neighboring light emitting cells. As shown in FIG. 7A, each of the connection portions 35ab is formed to have only one edge of the edges of the first conductivity type semiconductor layer 23 of one light emitting cell in order to reduce the influence of the morphology on the substrate 21 Cross the top. That is, in this embodiment, the first conductivity type semiconductor layer 23 of each light emitting cell has four edges, and the connection portion 35ab extends over only one edge of these edges. It is possible to prevent the connection portion 35ab from passing unnecessarily through the cell separation region ISO to the electrical connection, thereby reducing the damage of the connection portion 35ab due to the influence of the morphology. However, the present invention is not limited thereto, and the connection portion 35ab may cover two or more side surfaces of the light emitting cell, and may cover two or more cell isolation regions ISO around the light emitting cell.

The first pad metal layer 35a is located on the last light emitting cell C7 located at the end of the serial array of light emitting cells and the second pad metal layer 35b is located on the first light emitting cell C1 located at the first end. do. The first pad metal layer 35a may be positioned within the region above the second conductivity type semiconductor layer 27 of the last light emitting cell C7 and the second pad metal layer 35b may be located within the region above the second light emitting cell C1. May be confined within the upper region.

The first pad metal layer 35a is electrically connected to the first conductive type semiconductor layer 23 through the first opening 33a of the lower insulating layer 33 on the last light emitting cell C7. The first pad metal layer 35a may be in direct contact with the first conductive type semiconductor layer 23. Accordingly, the first pad metal layer 35a may include an ohmic layer that makes an ohmic contact with the first conductive type semiconductor layer 23. [

The second pad metal layer 35b is electrically connected to the ohmic reflective layer 31 through the second opening 33b of the lower insulating layer 33 on the first light emitting cell C1. The second pad metal layer 35b can directly contact the ohmic reflective layer 31. [ Further, as shown in Fig. 7A, the second pad metal layer 35b may be surrounded by the connecting portion 35ab. Accordingly, a boundary region may be formed between the second pad metal layer 35b and the connection portion 35ab, and the lower insulation layer 33 may be exposed to the boundary region.

The first pad metal layer 35a, the second pad metal layer 35b, and the connection portions 35ab may be formed of the same material together in the same process. For example, the first pad metal layer 35a, the second pad metal layer 35b, and the connection portions 35ab may include Ti, Cr, Ni, or the like as an adhesive layer, and may include Al as a metal reflective layer. In addition, the first pad metal layer 35a, the second pad metal layer 35b, and the connection portions 35ab may include a diffusion preventing layer for preventing diffusion of a metal element such as Sn and an oxidation preventing layer for preventing oxidation of the diffusion preventing layer. . As the diffusion preventing layer, for example, Cr, Ti, Ni, Mo, TiW or W may be used. As the oxidation preventing layer, Au may be used.

8A and 8B, an upper insulating layer 37 is formed to cover the first pad metal layer 35a, the second pad metal layer 35b, and the connecting portions 35ab. The upper insulating layer 31 has an opening 37a for exposing the first pad metal layer 35a and an opening 37b for exposing the second pad metal layer 35b. In the present embodiment, a plurality of openings 37a are shown, but not limited thereto, and one opening 37a may be used.

The opening 37b of the upper insulating layer 37 may be disposed laterally spaced from the second opening 33b of the lower insulating layer 33. [ The openings 37b of the upper insulating layer 37 and the second openings 33b of the lower insulating layer 33 are spaced apart from each other so as not to overlap each other so that the ohmic reflective layer 31 can be prevented from being contaminated by solder or the like. However, the present invention is not limited thereto, and the second opening 33b of the lower insulating layer 33 and the opening 37b of the upper insulating layer 37 may overlap each other.

The upper insulating layer 37 may cover the edge of the lower insulating layer 33 along the edge of the substrate 21 and may expose a part of the vicinity of the edge of the substrate 21. The edge of the upper insulating layer 37 may be formed so as to be spaced apart from the connecting portions 35ab by at least 11 um, and further by at least 15 um.

The upper insulating layer 37 may be formed of a single layer of a silicon oxide film or a silicon nitride film, or may be formed of a multi-layered distributed Bragg reflector. The upper insulating layer 37 may also be a distributed Bragg reflector in which the first material layer and the second material layer are alternately stacked similarly to the lower insulating layer 33. [ For example, the first material layer may be a SiO ₂ or MgF _2, the second material layer may be a material having a refractive index higher than that of the first material layer. The second material layer may be, for example, TiO _2, Nb ₂ O ₅ or ZrO _2. In particular, the upper insulating layer 37 may be formed of a distributed Bragg reflector in which SiO2 layer / ZrO2 layers are alternately laminated.

The upper insulating layer 37 may also be patterned using photolithography and etching processes, so that openings 37a and 37b may be formed. These openings 37a and 37b may also have offset side walls such as the openings 33a and 33b of the lower insulating layer 33. [

Referring to FIGS. 9A and 9B, a first bump pad 39a and a second bump pad 39b are formed on the upper insulating layer 37. As shown in FIG.

The first bump pad 39a is electrically connected to the first pad metal layer 35a through the opening 37a of the upper insulating layer 37 and the second bump pad 39b is electrically connected to the opening of the upper insulating layer 37 And is electrically connected to the second pad metal layer 35b through the second pad metal layer 37b.

The first and second bump pads 39a and 39b may be formed over a plurality of light emitting cells as shown in FIG. 9A. The upper insulating layer 37 prevents an electrical short between the light emitting cells and the first and second bump pads 39a and 39b.

After the first and second bump pads 39a and 39b are formed, the bottom surface of the substrate 21 may be partially removed by grinding and / or lapping to reduce the thickness of the substrate 21. [ Subsequently, the distributed Bragg reflectors 51 to 59 of FIG. 3A are sequentially formed on the substrate 21 to form a stack of distributed Bragg reflectors 51 to 59, and the substrate 21 is divided into individual chip units The light emitting diodes separated from each other by the division are provided. At this time, the substrate 21 may be separated using a laser scribing technique.

The distributed Bragg reflectors 51-59 may be sequentially formed from a distributed Bragg reflector 51 close to the substrate 21 using photolithographic and etching processes or lift-off techniques. That is, a first distributed Bragg reflector 51 is formed, and a second distributed Bragg reflector 53, a third distributed Bragg reflector 55, a fourth distributed Bragg reflector 57, and a fifth distributed Bragg reflector 59 ) Can be sequentially formed. Alternatively, after the first material layer and the second material layer are alternately stacked on the substrate 21 so as to have a reflectance of 90% or more, the fifth distributed Bragg reflector 59 is formed by patterning from above, 4 distribution Bragg reflector 57, a third distributed Bragg reflector 55 and a second distributed Bragg reflector 53 may be formed by patterning in order to form a stack of distributed Bragg reflectors 51-59.

The distributed Bragg reflectors 51, 53, 55, 57, and 59 each have a structure in which first and second material layers having different refractive indexes are alternately stacked. For example, the first material layer may be a SiO ₂ or MgF _2, the second material layer may be a material having a refractive index higher than that of the first material layer. The second material layer may be, for example, TiO _2, Nb ₂ O ₅ or ZrO _2. The distributed Bragg reflectors 51, 53, 55, 57, 59 may all be formed of the same first and second material layers, but are not limited thereto and may be formed of different first and second material layers . For example, the first distributed Bragg reflector 51 may be formed of SiO2 / TiO2, and the second distributed Bragg reflector may be formed of SiO2 / ZrO2.

On the other hand, the side surfaces of the distributed Bragg reflectors 51 to 59 formed by using the etching process or the lift-off technique may have an inclination angle, and the inclination angle may be within a range of about 20 to 70 degrees with respect to the surface of the substrate 21.

10 is a schematic cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.

10, the light emitting diode according to the present embodiment is substantially similar to the light emitting diode described with reference to FIG. 1, except that the distributed Bragg reflectors 51 to 59 are all disposed on one side of the substrate 21 . For example, the distributed Bragg reflectors 51-59 may be stacked such that one side faces are parallel. The light emitting diode of FIG. 1 has a symmetrical directing pattern as shown in FIG. 2, but the light emitting diode of this embodiment has an asymmetrical directing pattern of emitted light.

In this embodiment, although the side surfaces of the distributed Bragg reflectors 51 to 59 are described as being juxtaposed, the position and shape of the distributed Bragg reflectors 51 to 59 may be variously modified, The directional pattern of the emitted light of the diode can be varied variously.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, the elements or components described in relation to one embodiment can be applied to other embodiments without departing from the technical idea of the present invention.

Claims (20)

A semiconductor multilayer body including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; And
A plurality of distributed Bragg reflectors disposed on one side of the semiconductor stack,
Wherein the plurality of distributed Bragg reflectors are stacked with different areas. The method according to claim 1,
Wherein the plurality of distributed Bragg reflectors have a narrow area from the semiconductor laminate. The method of claim 3,
Wherein the plurality of distributed Bragg reflectors have the same central axis. The method of claim 3,
And the plurality of distributed Bragg reflectors are stacked such that one side faces thereof are parallel to each other. The method of claim 2,
Each of the distributed Bragg reflectors exhibiting a reflectance in the range of 5% to 50%. The method of claim 5,
Wherein the reflectance of the region in which the distributed Bragg reflectors are most overlapped exhibits a reflectance of 90% or more with respect to the light emitted from the active layer. The method of claim 6,
Wherein the reflectance of the least overlapped region of the distributed Bragg reflectors is less than or equal to 10%. The method according to claim 1,
And a substrate positioned between the semiconductor stack and the plurality of distributed Bragg reflectors. The method of claim 8,
A lower insulating layer covering the semiconductor stacked body, the lower insulating layer including a first opening exposing the first conductive type semiconductor layer of the semiconductor stacked body; And
And a first metal layer disposed on the lower insulating layer and electrically connected to the first conductive type semiconductor layer through a first opening of the lower insulating layer. The method of claim 9,
And an ohmic reflective layer disposed on the second conductive type semiconductor layer and ohmic-contacting the second conductive type semiconductor layer,
And the lower insulating layer further includes a second opening exposing the ohmic reflective layer. The method of claim 10,
An upper insulating layer covering the first metal layer;
And a first bump pad and a second bump pad which are located on the upper insulating layer and are electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer of the semiconductor multilayer body, respectively,
Wherein the upper insulating layer includes a first opening exposing the first metal layer,
And the first bump pad connects to the first metal layer through the first opening. The method of claim 9,
Wherein the semiconductor laminate includes a plurality of light emitting cells spaced from each other,
The first metal layer may be electrically connected to the first conductive semiconductor layer of the last light emitting cell disposed at the end of the serial array by electrically connecting the neighboring light emitting cells electrically in series to form a serial array of light emitting cells, And a second pad metal layer connected to the second pad metal layer. The method of claim 12,
An ohmic reflective layer disposed on the second conductivity type semiconductor layer of each light emitting cell and making ohmic contact with the second conductivity type semiconductor layer; And
And a second pad metal layer disposed on the lower insulating layer and electrically connected to the ohmic reflective layer of the first light emitting cell disposed at the first end of the serial array,
Wherein the lower insulating layer further comprises second openings for exposing the ohmic reflective layer on each light emitting cell,
And the second pad metal layer is electrically connected to the ohmic reflective layer on the first light emitting cell through the second opening. The method of claim 12,
An upper insulating layer covering the connection portion (s), the first and second pad metal layers, and having openings exposing upper surfaces of the first and second pad metal layers, respectively; And
And a first bump pad and a second bump pad respectively connected to upper surfaces of the first pad metal layer and the second pad metal layer exposed by the openings of the upper insulating layer. 15. The method of claim 14,
Wherein the first bump pad and the second bump pad are disposed over an upper region of two or more light emitting cells, respectively. A semiconductor multilayer body including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; And
And a stack of distributed Bragg reflectors disposed on one side of the semiconductor stack,
Wherein the stack of distributed Bragg reflectors comprises regions of different thickness,
Wherein the stack of distributed Bragg reflectors has a higher reflectivity in a thicker region. 18. The method of claim 16,
Wherein the stack of distributed Bragg reflectors exhibits the highest reflectance at the center and the lowest reflectance near the edge. 18. The method of claim 16,
Wherein at least a portion of the light generated in the active layer is emitted to the outside through a laminate of the distributed Bragg reflectors. 19. The method of claim 18,
And a substrate disposed between the semiconductor stack and the stack of distributed Bragg reflectors. The method of claim 19,
And a first bump pad and a second bump pad disposed on the semiconductor stack and electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer, respectively.

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