WO2018174425A1

WO2018174425A1 - Light-emitting diode including distributed bragg reflector laminate

Info

Publication number: WO2018174425A1
Application number: PCT/KR2018/002542
Authority: WO
Inventors: 김재권; 김종규; 채종현
Original assignee: 서울바이오시스주식회사
Priority date: 2017-03-21
Filing date: 2018-03-02
Publication date: 2018-09-27
Also published as: KR20180106720A

Abstract

A light-emitting diode according to an embodiment comprises: a semiconductor laminate comprising a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; and a plurality of distributed Bragg reflectors arranged on one side of the semiconductor laminate, wherein the plurality of distributed Bragg reflectors are laminated while differing in area from one another. The directional pattern of light emitted by the light-emitting diode can be adjusted by using the distributed Bragg reflectors.

Description

Light Emitting Diodes With Distributed Bragg Reflector Stacks

TECHNICAL FIELD The present invention relates to light emitting diodes, and more particularly, to light emitting diodes having a distributed Bragg reflector stack.

In general, nitrides of Group III elements such as gallium nitride (GaN) and aluminum nitride (AlN) have excellent thermal stability and have a direct transition energy band structure. As a lot of attention. In particular, blue and green light emitting diodes using indium gallium nitride (InGaN) have been used in various applications such as large-scale color flat panel display devices, traffic lights, indoor lighting, high density light sources, high resolution output systems, and optical communications.

A light emitting diode is generally used in a package form through a packaging process, and a lens has been used together to adjust the directing pattern of the emitted light.

Recently, researches on a light emitting diode in the form of a chip scale package performing a packaging process at a chip level are being conducted. Such a light emitting diode is smaller in size than a general package and does not perform a separate packaging process, thereby simplifying the process and saving time and money. The light emitting diode in the form of a chip scale package generally has a flip chip-shaped electrode structure and has excellent heat dissipation characteristics.

On the other hand, the lens used to adjust the directing pattern of the emitted light is relatively large compared to the light emitting diode, thereby increasing the size of the light emitting module. In addition, since the lens is installed separately from the light emitting diode, the directional pattern adjustment using the lens is not suitable for the light emitting diode technology trend to simplify the process.

The problem to be solved by the present invention is to provide a light emitting diode that can adjust the light directing pattern without using a lens.

Another object of the present invention is to provide a flip chip structure light emitting diode in the form of a chip scale package.

A light emitting diode according to an embodiment of the present invention, a semiconductor laminate comprising a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; And a plurality of distributed Bragg reflectors disposed on one side of the semiconductor stack, wherein the plurality of Distributed Bragg reflectors are stacked with different areas.

In accordance with still another aspect of the present invention, there is provided a light emitting diode comprising: a semiconductor laminate including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; And a stack of distribution Bragg reflectors disposed on one side of the semiconductor stack, wherein the stack of Distribution Bragg reflectors includes regions having different thicknesses, and the stack of Distribution Bragg reflectors has a thick thickness region. Has a higher reflectivity at.

According to embodiments of the present invention, the direction pattern of the outgoing light may be adjusted through the stacking of the distribution Bragg reflectors, and thus, the lens may be omitted.

Other advantages and effects of the present invention will become more apparent from the detailed description.

1 is a schematic cross-sectional view for describing a light emitting diode according to an embodiment of the present invention.

2 is a schematic graph for explaining an emission light directing pattern of a light emitting diode according to an embodiment of the present invention.

3A is a schematic plan view illustrating a light emitting diode according to still another embodiment of the present invention.

FIG. 3B is a schematic cross sectional view taken along cut line A-A of FIG. 3A.

4 to 9 are plan views and cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention.

10 is a schematic cross-sectional view for describing a light emitting diode according to still another embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention; The following embodiments are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art to which the present invention pertains. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, the width, length, thickness, etc. of the components may be exaggerated for convenience. In addition, when one component is described as "on" or "on" another component, each component is different from each other as well as when the component is "just above" or "on" the other component. It also includes a case where another component is interposed therebetween. Like numbers refer to like elements throughout.

By stacking the distribution Bragg reflectors having different areas, the reflectance can be adjusted according to the position, and thus the directivity pattern of the emitted light can be adjusted.

On the other hand, the plurality of distributed Bragg reflectors may have a narrower area from the semiconductor laminate. Since distributed Bragg reflectors have a narrow area in sequence, they can be manufactured relatively easily.

In one embodiment, the plurality of distributed Bragg reflectors may have the same central axis. Accordingly, the directivity pattern of the emitted light can be formed symmetrically, and the amount of light emitted in the direction of the central axis of the light emitting diode can be reduced.

In another embodiment, the plurality of distributed Bragg reflectors may be stacked such that one side sides are side by side. Thereby, the directivity pattern of the emitted light can be formed asymmetrically.

On the other hand, each of the distribution Bragg reflectors may exhibit a reflectance in the range of 5% to 50%. These distributed Bragg reflectors are stacked on each other resulting in higher reflectance.

The reflectance of the region where the distribution Bragg reflectors are most overlapped may represent a reflectance of 90% or more with respect to the light emitted from the active layer. In addition, the reflectance of the region where the distribution Bragg reflectors least overlap, may exhibit a reflectance of 10% or less.

The light emitting diode may further include a substrate positioned between the semiconductor laminate and the plurality of distributed Bragg reflectors.

The light emitting diode may include a lower insulating layer covering the semiconductor stack and including a first opening exposing a first conductive semiconductor layer of the semiconductor stack; And a first metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through a first opening of the lower insulating layer.

Further, the light emitting diode further includes an ohmic reflective layer disposed on the second conductive semiconductor layer and ohmic contacting the second conductive semiconductor layer, wherein the lower insulating layer has a second opening exposing the ohmic reflective layer. It may further include.

The light emitting diode may further include an upper insulating layer covering the first metal layer; A first bump pad and a second bump pad disposed on the upper insulating layer and electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer of the semiconductor laminate, respectively; The layer may include a first opening that exposes the first metal layer, and the first bump pad may be connected to the first metal layer through the first opening.

In some embodiments, the semiconductor laminate may include a plurality of light emitting cells spaced apart from each other, and the first metal layer may be configured to electrically connect neighboring light emitting cells in series to form a series array of light emitting cells. And a first pad metal layer electrically connected to the first conductivity-type semiconductor layer of the last light emitting cell disposed at the end of the series array. Accordingly, it is possible to provide a light emitting diode that can be driven at a high voltage.

On the other hand, the light emitting diode, an ohmic reflective layer disposed on the second conductive semiconductor layer of each light emitting cell and ohmic contact with the second conductive semiconductor layer; And a second pad metal layer disposed on the lower insulating layer and electrically connected to the ohmic reflective layer of the first light emitting cell disposed at the first stage of the series array, wherein the lower insulating layer is the ohmic reflective layer on each light emitting cell. The second pad metal layer may be electrically connected to the ohmic reflective layer on the first light emitting cell through the second opening.

Further, the light emitting diode includes: an upper insulating layer covering the connection portion (s), the first and second pad metal layers, and having openings exposing upper surfaces of the first and second pad metal layers, respectively; And a first bump pad and a second bump pad connected to upper surfaces of the first pad metal layer and the second pad metal layer exposed by the openings of the upper insulating layer, respectively. By adopting the second pad metal layer, the first bump pad and the second bump pad can be formed at the same height.

In some embodiments, the first bump pad and the second bump pad may be disposed over an upper region of two or more light emitting cells, respectively. Therefore, the first and second bump pads can be formed relatively large, so that mounting of the light emitting diode can be facilitated.

By adjusting the thickness of the stack of distributed Bragg reflectors, the directing pattern of the emitted light can be controlled.

Furthermore, the stack of distributed Bragg reflectors may exhibit the highest reflectance in the center and the lowest reflectance near the edges. Accordingly, it is possible to disperse the light emitted from the light emitting diode without using a dispersing lens for dispersing the light.

Meanwhile, at least a part of the light generated in the active layer may be emitted to the outside through the stack of the distribution Bragg reflectors.

The light emitting diode may further include a substrate disposed between the semiconductor stack and the stack of distributed Bragg reflectors.

The light emitting diode may further include a first bump pad and a second bump pad disposed on the semiconductor laminate and electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer, respectively. . Accordingly, a light emitting diode having a flip chip structure can be provided.

It will be described below in detail with reference to the drawings.

Referring to FIG. 1, the light emitting diode includes a substrate 21, a semiconductor laminate 30, a first bump pad 39a and a second bump pad 39b, and a plurality of distributed

Bragg reflectors

51, 53, 55, 57, 59).

The substrate 21 may be, for example, a substrate capable of growing a gallium nitride based semiconductor layer. The substrate 21 may include a sapphire substrate, a gallium nitride substrate, a SiC substrate, or the like, and in particular, may be a patterned sapphire substrate. The substrate 21 may have a rectangular or square planar shape, but is not limited thereto. The size of the substrate 21 is not particularly limited and may be variously selected.

The semiconductor laminate 30 includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, and emits light using a combination of electrons and holes in the active layer. The specific structure of the semiconductor laminate 30 is described in detail later with reference to FIG. 3.

Meanwhile, the first bump pads 39a and the second bump pads 39b are disposed on the semiconductor laminate 30, and the first and

second bump pads

39a and 39b are respectively the first conductive semiconductor layer. And a second conductive semiconductor layer.

Meanwhile, a stack of distribution Bragg reflectors 51 to 59 is disposed on the substrate 21. As shown in FIG. 1, a plurality of distributed Bragg reflectors 51 to 59 are stacked with different areas. The first distributed Bragg reflector 51 closest to the substrate 21 may have the same area as the substrate 21 but may be smaller than that. The first distributed Bragg reflector 51 may be disposed on the substrate 21 such that its central axis coincides with the central axis of the substrate 21. In addition, the distributed Bragg reflectors 53 to 59 disposed thereon may be arranged in order with a narrower area as farther from the substrate 21 as possible. In addition, as illustrated in FIG. 1, the central axes of the distribution Bragg reflectors 51 to 59 may be disposed to coincide with each other.

Accordingly, all of the distribution Bragg reflectors 51 to 59 are stacked on the central region of the substrate 21, and the number of the distribution Bragg reflectors stacked toward the edge is reduced. Thus, the stack of distributed Bragg reflectors 51-59 is the thickest in the central region and the thinnest near the edge.

The distributed

Bragg reflectors

51, 53, 55, 57, 59 may each reflect light generated in the active layer with a reflectance in the range of 5% to 50%. In addition, these distributed Bragg reflectors 51 to 59 are stacked on each other, whereby a higher reflectance is exhibited in a region having a large number of stacked layers, that is, a thick region. For example, in FIG. 1, the central region in which all the distribution Bragg reflectors 51 to 59 are stacked may exhibit a reflectance of 90% or more with respect to the light generated in the active layer, and at the edge where only the Distribution Bragg reflectors 51 are disposed. A reflectance of 10% or less can be exhibited.

The distributed

Bragg reflectors

51, 53, 55, 57, 59 have a structure in which a first material layer and a second material layer having different refractive indices are alternately stacked. For example, the first material layer may be SiO ₂ or MgF ₂ , and the second material layer may be a material layer having a higher refractive index than the first material layer. The second material layer can be, for example, TiO ₂ , Nb ₂ O ₅ or ZrO ₂ . The

distribution Bragg reflectors

51, 53, 55, 57, 59 may all be formed of the same first and second material layers, but are not limited to this and are formed of different first and second material layers. May be For example, the first distributed Bragg reflector 51 may be formed of SiO 2 / TiO 2, and the second distributed Bragg reflector 51 may be formed of SiO 2 / ZrO 2.

The reflectance of the distributed Bragg reflectors can be adjusted by adjusting the types of the first and second material layers constituting the distributed Bragg reflectors 51 to 59, the formation method, the thickness and the number of the stacked layers.

Meanwhile, in the drawings, the side surfaces of each of the distribution Bragg reflectors 51 to 59 are vertical, but the present invention is not limited thereto. In particular, the sides of the distribution Bragg reflectors 51-59 may have an inclination angle within the range of about 20 to 70 degrees with respect to the substrate 21 surface.

Light generated in the active layer is generally emitted to the outside through the distribution Bragg reflectors 51 to 59. In order to emit light through the distribution Bragg reflectors 51 to 59 on the substrate 21, light is emitted onto the semiconductor laminate 30 on the side of the first bump pad 39a and the second bump pad 39b. Another reflector may be provided for reflecting toward 21).

According to the present embodiment, the amount of emitted light can be controlled by using a stacked structure of the distributed Bragg reflectors 51 to 59. By controlling the amount of light emitted according to the position, the directing pattern of the emitted light can be adjusted.

On the other hand, in the present embodiment, it is described that the distribution Bragg reflectors 51 to 59 are disposed on the substrate 21 opposite to the semiconductor stack 30, but the Distribution Bragg reflectors 51 to 59 are semiconductor stacks. It may be disposed on the sieve 30. In this case, the light generated in the active layer will be emitted in the direction opposite to the substrate 21 through the distribution Bragg reflectors 51 to 59.

Referring to FIG. 2, as shown in FIG. 1, the distribution Bragg reflectors 51 to 59 are disposed in the center region of the substrate 21 so as to have a high reflectance and a low reflectance at the edge thereof. It is possible to reduce the intensity of the light emitted and to allow more light to be emitted at a larger angle of directivity.

Since the distribution Bragg reflectors 51 to 59 can adjust the directing pattern of the emitted light, the amount of light in the central region can be reduced. Thus, there is no need to use a separate lens such as a dispersion lens used to change the directing pattern of the light emitting diode.

In addition, the light emitting diode may be used without a lens as a light source of the backlight, thereby reducing the backlight module of the direct type light emitting module.

3A is a schematic plan view illustrating a light emitting diode according to still another embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along the cutting line A-A of FIG. 3A.

3A and 3B, the light emitting diode includes a substrate 21, a semiconductor laminate 30, an ohmic reflective layer 31, a lower insulating layer 33, a first pad metal layer 35a, and a second pad metal layer. 35b, connecting portions 35ab, an upper insulating layer 37, a first bump pad 39a and a second bump pad 39b, and a stack of distributed Bragg reflectors 51 to 59. The semiconductor laminate 30 may include a first conductive semiconductor layer 23, an active layer 25, and a second conductive semiconductor layer 27, and may be separated into a plurality of light emitting cells C1 to C7. .

The substrate 21 is not particularly limited as long as it is a substrate capable of growing a gallium nitride semiconductor layer. Examples of the substrate 21 may include a sapphire substrate, a gallium nitride substrate, a SiC substrate, and the like, and may be a patterned sapphire substrate. The substrate 21 may have a rectangular or square outer shape as shown in the plan view of FIG. 3A, but is not necessarily limited thereto. The size of the substrate 21 is not particularly limited and may be variously selected.

The semiconductor laminate 30 may be separated into a plurality of light emitting cells C1 to C7. The plurality of light emitting cells C1 to C7 are spaced apart from each other on the substrate 21. Although seven light emitting cells C1 to C7 are shown in the present embodiment, the number of light emitting cells can be adjusted. In addition, in this embodiment, the semiconductor laminate 30 is described as being separated into a plurality of light emitting cells C1 to C7, but may be a single light emitting cell that is not separated.

The light emitting cells C1 to C7 each include a first conductivity type semiconductor layer 23. The first conductivity type semiconductor layer 23 is disposed on the substrate 21. The first conductivity-type semiconductor layer 23 is a layer grown on the substrate 21 and may be a gallium nitride-based semiconductor layer doped with impurities such as Si.

The active layer 25 and the second conductive semiconductor layer 27 are disposed on the first conductive semiconductor layer 23. The active layer 25 is disposed between the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27. The active layer 25 and the second conductive semiconductor layer 27 may have an area smaller than that of the first conductive semiconductor layer 23. The active layer 25 and the second conductive semiconductor layer 27 may be located on the first conductive semiconductor layer 23 in a mesa form by mesa etching.

At the edges of the light emitting cells C1 to C7 adjacent to the edge of the substrate 21, the edge and mesa of the first conductivity-type semiconductor layer 23, for example, the active layer 25 and the second conductivity-type semiconductor layer The edges of 27 may be spaced apart from each other. That is, a part of the upper surface of the first conductivity type semiconductor layer 23 is exposed to the outside of the mesa. The active layer 25 is spaced farther from the edge of the substrate 21 than the first conductive semiconductor layer 23, and thus, the active layer 25 may be prevented from being damaged in the substrate separation process by the laser.

Meanwhile, at the edges of the light emitting cells C1 to C7 facing the adjacent light emitting cells, the edge of the first conductive semiconductor layer 23, the active layer 25, and the second conductive semiconductor layer 27 are formed. The edge of) may be located on the same slope. Therefore, the top surface of the first conductivity-type semiconductor layer 23 may not be exposed in the light emitting cells facing each other. Accordingly, the light emitting area of the light emitting cells C1 to C7 can be secured.

The active layer 25 may have a single quantum well structure or a multiple quantum well structure. The composition and thickness of the well layer in the active layer 25 determines the wavelength of the light produced. In particular, it is possible to provide an active layer that generates ultraviolet light, blue light or green light by adjusting the composition of the well layer.

The second conductivity-type semiconductor layer 27 may be a gallium nitride-based semiconductor layer doped with p-type impurities, for example, Mg. Each of the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27 may be a single layer, but is not limited thereto, and may be a multilayer or a superlattice layer. The first conductive semiconductor layer 23, the active layer 25, and the second conductive semiconductor layer 27 may be formed using a known method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). It may be formed and grown on the substrate 21 within.

On the other hand, the light emitting cells C1 to C7 have through holes 30a through the second conductive semiconductor layer 27 and the active layer 23 to expose the first conductive semiconductor layer 23. The through holes 30a are surrounded by the second conductivity type semiconductor layer 27 and the active layer 25. As shown, the through holes 30a may be disposed in the central area of the light emitting cells C1 to C7 and may have an elongated shape. However, the present invention is not limited thereto, and a plurality of through holes may be formed in each light emitting cell.

On the other hand, the ohmic reflective layer 31 is disposed on the second conductive semiconductor layer 27 and electrically connected to the second conductive semiconductor layer 27. The ohmic reflective layer 31 may be disposed over almost the entire area of the second conductive semiconductor layer 27 in the upper region of the second conductive semiconductor layer 27. For example, the ohmic reflective layer 31 may cover 80% or more of the upper region of the second conductivity-type semiconductor layer 27 and more than 90%.

The ohmic reflective layer 31 may include a reflective metal layer, and thus may reflect light generated in the active layer 25 and traveling to the ohmic reflective layer 31 toward the substrate 21. For example, the ohmic reflective layer 31 may be formed of a single reflective metal layer, but is not limited thereto. The ohmic reflective layer 31 may include an ohmic layer and a reflective layer. As the ohmic layer, a metal layer such as Ni or a transparent oxide layer such as indium tin oxide (ITO) may be used, and a reflective metal layer such as Ag or Al may be used as the reflective layer.

The lower insulating layer 33 covers the light emitting cells C1 to C7 and the ohmic reflective layer 31. The lower insulating layer 33 may cover not only the upper surfaces of the light emitting cells C1 to C7 but also the side surfaces of the light emitting cells C1 to C7 along the periphery thereof, and the substrates around the light emitting cells C1 to C7 ( 21) can be partially covered. The lower insulating layer 33 particularly covers the cell isolation region ISO between the light emitting cells C1 to C7, and further partially covers the first conductivity-type semiconductor layer 23 exposed in the through holes 30a. Can be covered with

Meanwhile, the lower insulating layer 33 has first openings 33a exposing the first conductivity type semiconductor layer and second openings 33b exposing the ohmic reflective layers 31. The first opening 33a may expose the first conductivity-type semiconductor layer 23 in the through hole 30a and may expose the upper surface of the substrate 21 along the edge of the substrate 21.

The second opening 33b is positioned above the ohmic reflective layer 31 to expose the ohmic reflective layer 31. The position and shape of the second openings 33b may be variously modified to arrange and electrically connect the light emitting cells C1 to C7. In addition, although one second opening 33b is disposed on each light emitting cell in FIG. 1, a plurality of second openings 33b may be disposed on each light emitting cell.

The lower insulating layer 33 may be formed of a single layer such as a silicon oxide film or a silicon nitride film. In addition, the lower insulating layer 33 may be formed of multiple layers, and in particular, may have a laminated structure in which a first material layer having a first refractive index and a second material layer having a second refractive index are alternately stacked. In particular, the lower insulating layer 33 may be a distributed Bragg reflector having a high reflectance in a specific wavelength band through the stacked structure. Here, the first material layer may be SiO ₂ or MgF ₂ , and the second material layer may be a material layer having a higher refractive index than the first material layer. The second material layer can be, for example, TiO ₂ , Nb ₂ O ₅ or ZrO ₂ . In particular, the first material layer may be formed of an SiO ₂ layer, and the second material layer may be formed of a ZrO ₂ layer, thereby improving the moisture resistance of the lower insulating layer 33.

Meanwhile, the first pad metal layer 35a, the second pad metal layer 35b, and the connecting portions 35ab are disposed on the lower insulating layer 33. The second pad metal layer 35a is positioned on the first light emitting cell C1, and the first pad metal layer 35b is positioned on the last light emitting cell, that is, the seventh light emitting cell C7. Meanwhile, the connection parts 35ab are positioned over two neighboring light emitting cells, and electrically connect the light emitting cells C1 to C7 in series. Accordingly, seven light emitting cells C1 to C7 are connected in series by the connecting parts 35ab to form a series array. Here, the first light emitting cell C1 is located at the first end of the serial array, and the last light emitting cell, the seventh light emitting cell C7, is located at the end of the series array.

Although the present invention is not necessarily limited thereto, the first pad metal layer 35a is in the upper region of the last light emitting cell C7 and further, in the upper region of the second conductive semiconductor layer 27 of the last light emitting cell C7. It can be located within. The first pad metal layer 35a is also electrically connected to the first conductive semiconductor layer 23 of the last light emitting cell C7 through the first opening 33a of the lower insulating layer 33. The first pad metal layer 35a may directly contact the first conductive semiconductor layer 23 through the first opening 33a.

In addition, the second pad metal layer 35b may be located within the upper region of the first light emitting cell C1 and further, in the upper region of the second conductive semiconductor layer 27 of the first light emitting cell C1. have. The second pad metal layer 35b is electrically connected to the ohmic reflective layer 31 on the first light emitting cell C1 through the second opening 33b of the lower insulating layer 33. The second pad metal layer 35b may directly contact the ohmic reflective layer 31 through the second opening 33b.

On the other hand, the second pad metal layer 35b may be surrounded by the connecting portion 35ab, so that a boundary area surrounding the second pad metal layer 35b is formed between the second pad metal layer 35b and the connecting portion 35ab. Can be formed. This boundary region exposes the lower insulating layer 33.

Meanwhile, the connection parts 35ab electrically connect neighboring light emitting cells. Each connecting portion 35ab is electrically connected to the first conductive semiconductor layer 23 of one light emitting cell, and the ohmic reflective layer 31 of the neighboring light emitting cell, and thus, the second conductive semiconductor layer 27. These light emitting cells are connected in series by electrically connecting the same. In detail, each of the connection parts 35ab may be electrically connected to the first conductive semiconductor layer 23 exposed through the first opening 33a of the lower insulating layer 33, and the second opening 33b may be electrically connected to each other. It can be electrically connected to the ohmic reflective layer 31 exposed through. In addition, the connection parts 35ab may directly contact the first conductivity-type semiconductor layer 23 and the ohmic reflective layer 31.

Each connection part 35ab passes through a cell isolation region ISO between the light emitting cells. Each connection part 35ab may pass through only one edge upper region of the edges of the first conductivity-type semiconductor layer 23. Accordingly, the area of the connection portion 35ab positioned above the cell isolation region ISO may be reduced. Further, all of the remaining portions except for the portion of the connection portion 35ab passing through the cell separation region ISO are connected to the upper portion of the light emitting cells region to connect neighboring light emitting cells. For example, the light emitting cells C1 to C7 may each have a rectangular shape as shown in FIG. 3A, and thus have four edges. The connection part 35ab passes through an upper edge region of only one of the edges of one light emitting cell, and may be spaced apart from an upper region of the remaining edges of the light emitting cell. However, the present invention is not limited thereto, and the connection parts 35ab may cover two or more sides of the light emitting cell, and may cover cell separation regions around four sides of the light emitting cell.

Meanwhile, the first pad metal layer 35a, the second pad metal layer 35b, and the connecting portions 35ab may be formed together with the same material in the same process after the lower insulating layer 33 is formed, and thus are located at the same level. can do. Although not necessarily limited thereto, the first pad metal layer 35a, the second pad metal layer 35b, and the connecting portions 35ab may include portions positioned on the lower insulating layer 33, respectively.

The first and second

pad metal layers

35a and 35b and the connection part 35ab may include a reflective layer such as an Al layer, and the reflective layer may be formed on an adhesive layer such as Ti, Cr, or Ni. In addition, a protective layer having a single layer or a composite layer structure such as Ni, Cr, Au, or the like may be formed on the reflective layer. The first and second

pad metal layers

35a and 35b and the connecting portions 35ab may have, for example, a multilayer structure of Cr / Al / Ni / Ti / Ni / Ti / Au / Ti.

The upper insulating layer 37 covers the first and second

pad metal layers

35a and 35b and the connecting portions 35ab. In addition, the upper insulating layer 37 may cover the edge of the lower insulating layer 33 along the circumference of the light emitting cells C1 to C7. However, the upper insulating layer 37 may expose the upper surface of the substrate 21 along the edge of the substrate 21.

In one embodiment, the shortest distance from the edge of the upper insulating layer 37 to the connections 35ab may be about 15 um or more to prevent moisture from penetrating and damaging the connections 35ab.

Meanwhile, the upper insulating layer 37 has a first opening 37a exposing the first pad metal layer 35a and a second opening 37b exposing the second pad metal layer 35b. The first opening 37a and the second opening 37b are disposed in the last light emitting cell C7 and the upper region of the first light emitting cell C1, respectively. Except for the first and

second openings

37a and 37b, all other regions of the light emitting cells C1 to C7 may be covered with the upper insulating layer 37. Therefore, both the top and side surfaces of the connecting portions 35ab may be covered with the upper insulating layer 37 and sealed.

Meanwhile, in one embodiment, the second openings 37b of the upper insulating layer 37 may be spaced apart laterally so as not to overlap the second openings 33b of the lower insulating layer 33. Accordingly, even if the solder penetrates through the second opening 37b of the upper insulating layer 37, it is possible to prevent the solder from diffusing into the second opening 33b of the lower insulating layer 33, thereby preventing ohmic caused by the solder. Contamination of the reflective layer 31 can be prevented. However, the present invention is not limited thereto, and the second opening 37b of the upper insulating layer 37 may be disposed to overlap the second opening 33b of the lower insulating layer 33.

The upper insulating layer 37 may be formed of a single layer of SiO ₂ or Si ₃ N ₄ , but is not limited thereto. For example, the upper insulating layer 37 may have a multilayer structure in which a first material layer having a first refractive index and a second material layer having a second refractive index are alternately stacked similarly to the lower insulating layer 33. . For example, the first material layer may be SiO ₂ or MgF ₂ , and the second material layer may be a material layer having a higher refractive index than the first material layer. The second material layer can be, for example, TiO ₂ , Nb ₂ O ₅ or ZrO ₂ . In particular, the first material layer may be formed of a SiO ₂ layer, and the second material layer may be formed of a ZrO ₂ layer. Accordingly, a light emitting diode with high moisture resistance can be provided. In particular, the upper insulating layer may be a distributed Bragg reflector.

Meanwhile, the first bump pad 39a is in electrical contact with the first pad metal layer 35a exposed through the first opening 37a of the upper insulating layer 37, and the second bump pad 39b is second. The second pad metal layer 35b exposed through the opening 37b may be electrically connected to the second pad metal layer 35b. The first bump pad 39a covers and seals all of the first openings 37a of the upper insulating layer 37, and the second bump pad 39b covers the second opening 37b of the upper insulating layer 37. Cover all and seal.

In addition, as illustrated in FIG. 3A, the first and

second bump pads

39a and 39b may be disposed over the plurality of light emitting cells. In FIG. 3A, the first bump pad 39a is disposed over an upper region of the second, third, fifth, sixth, and seventh light emitting cells C2, C3, C5, C6, and C7. The bump pad 39b is disposed over an upper region of the first, fourth, fifth, and sixth light emitting cells C1, C4, C5, and C6. Accordingly, the first and

second bump pads

39a and 39b may be formed relatively large, and thus, may assist in the process of mounting the light emitting diode.

The first bump pads 39a and the second bump pads 39b are formed of a material suitable for bonding as portions of the light emitting diodes bonded to a submount or a printed circuit board. For example, the first and

second bump pads

39a and 39b may include an Au layer or an AuSn layer.

Meanwhile, the distribution Bragg reflectors 51 to 59 are disposed on the substrate 21 to face the semiconductor stack 30. Since the distribution Bragg reflectors 51 to 59 have been described with reference to FIGS. 1 and 2, the detailed description thereof will be omitted.

Although the light emitting diode having the seven light emitting cells C1 to C7 has been described above, the number of the light emitting cells may be larger or smaller. Furthermore, the light emitting diode may comprise a single light emitting cell, in which case the connection part 35ab is unnecessary.

On the other hand, the structure of the light emitting diode will be described more clearly through the light emitting diode manufacturing method described below.

4 through 9 are schematic plan views and cross-sectional views for describing a method of manufacturing a light emitting diode according to the embodiment of FIG. 3A. In each of the figures, a represents a plan view and b represents a cross sectional view taken along the cut line A-A of each plan view.

4A and 4B, a semiconductor laminate 30 including a first conductive semiconductor layer 23, an active layer 25, and a second conductive semiconductor layer 27 on a substrate 21. Is grown. The substrate 21 may be a substrate capable of growing a gallium nitride based semiconductor layer, and may be, for example, a sapphire substrate, a silicon carbide substrate, a gallium nitride (GaN) substrate, a spinel substrate, or the like. In particular, the substrate 21 may be a patterned substrate, such as a patterned sapphire substrate.

The first conductive semiconductor layer 23 may include, for example, an n-type gallium nitride based layer, and the second conductive semiconductor layer 27 may include a p-type gallium nitride based layer. In addition, the active layer 25 may be a single quantum well structure or a multi-quantum well structure, and may include a well layer and a barrier layer. In addition, the well layer may be selected in its composition according to the wavelength of light required, for example AlGaN, GaN or InGaN.

Subsequently, a plurality of light emitting cells C1 to C7 are formed by patterning the semiconductor stack 30. For example, a mesa forming process for exposing the top surface of the first conductivity type semiconductor layer 23 and a cell separation process for forming the cell isolation region ISO may be performed using a photo and etching process.

The light emitting cells C1 to C7 are spaced apart from each other by the cell isolation region ISO, and have through holes 30a. As shown in FIG. 4B, the sidewalls of the cell isolation region ISO and the sidewalls of the through holes 30a may be inclined.

Meanwhile, an upper surface of the first conductive semiconductor layer 23 of each of the light emitting cells is exposed by a mesa etching process. The through holes 30a may be formed together in a mesa etching process. However, the upper surface of the first conductive semiconductor layer 23 may be exposed in a ring shape along the circumferences of the second conductive semiconductor layer 27 and the active layer 23, but is not limited thereto. As shown in FIGS. 4A and 4B, the top surface of the first conductivity-type semiconductor layer 23 is exposed near the edges of the light emitting cells C1 to C7 positioned near the edge of the substrate 21. Near the outer edges, the second conductivity type semiconductor layer 27, the active layer 23 and the first conductivity type semiconductor layer 23 may form a continuous inclined surface, and thus, the first conductivity type semiconductor layer 23 The top surface may not be exposed. In a particular embodiment, there may be an isolated light emitting cell surrounded by light emitting cells, wherein the edges of the isolated light emitting cell are spaced apart from the edge of the substrate 21. In this case, the first conductive semiconductor layer 23 of the isolated light emitting cell forms a continuous inclined surface together with the second conductive semiconductor layer 27 and the active layer 25, and the upper surface exposed near the edge is formed. You may not have it at all.

As the plurality of light emitting cells C1 to C7 spaced apart from each other by the cell isolation region ISO on the substrate 21, morphologies having positions having different heights are formed. In this morphology, the top surface of the second conductivity-type semiconductor layer 27 of each light emitting cell is the highest, and the surface of the substrate 21 exposed to the cell isolation region ISO is the lowest.

5A and 5B, ohmic reflective layers 31 are formed on the light emitting cells C1 to C7, respectively. The ohmic reflective layer 31 may be formed using, for example, a lift off technique. The ohmic reflective layer 31 may be formed of a single layer or multiple layers, and may include, for example, an ohmic layer and a reflective layer. These layers can be formed using, for example, electron-beam evaporation. Before forming the ohmic reflective layer 31, a preliminary insulating layer (not shown) having an opening may be formed first in the region where the ohmic reflective layer 31 is to be formed.

In the present exemplary embodiment, the ohmic reflective layer 31 is formed after the light emitting cells C1 to C7 are formed, but is not limited thereto. For example, the ohmic reflective layer 31 may be formed first, and the light emitting cells C1 to C7 may be formed, and a metal layer for the ohmic reflective layer 31 is deposited on the semiconductor stack 30. The metal layer and the semiconductor stack 30 may be patterned together to form the ohmic reflective layer 31 and the light emitting cells C1 to C7 together.

6A and 6B, a lower insulating layer 33 covering the ohmic reflective layer 31 and the light emitting cells C1 to C7 is formed. The lower insulating layer 33 may be formed of a single layer such as SiO 2 or Si 3 N 4. Alternatively, the lower insulating layer 33 may be formed by alternately stacking a first material layer and a second material layer having different refractive indices using a technique such as chemical vapor deposition (CVD). For example, the first material layer may be SiO ₂ or MgF ₂ , and the second material layer may be a material layer having a higher refractive index than the first material layer. The second material layer can be, for example, TiO ₂ , Nb ₂ O ₅ or ZrO ₂ . In particular, the first material layer can be, for example, an SiO ₂ layer, and the second material layer can be a ZrO ₂ layer. By adopting the ZrO ₂ layer as the second material layer, the lower insulating layer 33 having high moisture resistance can be provided.

The preliminary insulating layer (not shown) described above may be integrated with the lower insulating layer 33. Therefore, due to the preliminary insulating layer formed around the ohmic reflective layer 31, the thickness of the lower insulating layer 33 may vary depending on the position. That is, the lower insulating layer 33 on the ohmic reflective layer 31 may be thinner than the lower insulating layer 33 around the ohmic reflective layer 31.

The lower insulating layer 33 may be patterned through a photolithography and an etching process. Accordingly, the lower insulating layer 33 may expose the first conductive semiconductor layer 23 in the through holes 30a. It has an opening 33a and has a second opening 33b exposing the ohmic reflective layer 31 on each light emitting cell. Further, the lower insulating layer 33 has a side surface disposed near the edge of the substrate 21.

7A and 7B, a first pad metal layer 35a, a second pad metal layer 35b, and connecting portions 35ab are formed on the lower insulating layer 33.

The connecting parts 35ab electrically connect the first to seventh light emitting cells C1 to C7 to form a series array of light emitting cells C1 to C7. The first light emitting cell C1 is positioned at the first end of the series array, and the seventh light emitting cell C7 is positioned at the end of the series array.

In particular, the connecting portions 35ab electrically connect the first conductive semiconductor layer 23 of one light emitting cell and the second conductive semiconductor layer 27 of the light emitting cell adjacent thereto. The connecting portions 35ab may be electrically connected to the first conductive semiconductor layer 23 exposed in the through holes 30a through the first openings 33a of the lower insulating layer 33. The ohmic reflective layer 31 may be electrically connected through the second openings 33b of 33. In addition, the connection parts 35ab may directly contact the first conductivity-type semiconductor layer 23 and the ohmic reflective layer 31.

The connection parts 35ab pass through the cell isolation region ISO to connect neighboring light emitting cells. As shown in FIG. 7A, each connection portion 35ab is formed at the edge of only one of the edges of the first conductivity-type semiconductor layer 23 of one light emitting cell in order to reduce the influence of the morphology on the substrate 21. Pass the upper part That is, in the present embodiment, the first conductive semiconductor layer 23 of each light emitting cell has four edges, and the connecting portion 35ab passes over the upper edge of only one of these edges. It is possible to prevent the connection part 35ab from passing through the cell isolation region ISO unnecessarily for electrical connection, thereby reducing the damage of the connection part 35ab due to the influence of the morphology. However, the present invention is not limited thereto, and the connection part 35ab may cover two or more side surfaces of the light emitting cell, and may cover two or more cell separation regions ISO around the light emitting cell.

Meanwhile, the first pad metal layer 35a is positioned on the last light emitting cell C7 located at the end of the series array of light emitting cells, and the second pad metal layer 35b is positioned on the first light emitting cell C1 located at the first end. do. The first pad metal layer 35a may be located within the upper region of the second conductive semiconductor layer 27 of the last light emitting cell C7, and the second pad metal layer 35b may be disposed on the first light emitting cell C1. It can be located confined in the upper region.

The first pad metal layer 35a is electrically connected to the first conductive semiconductor layer 23 through the first opening 33a of the lower insulating layer 33 on the last light emitting cell C7. The first pad metal layer 35a may directly contact the first conductive semiconductor layer 23. Therefore, the first pad metal layer 35a may include an ohmic layer that ohmic contacts the first conductive semiconductor layer 23.

Meanwhile, the second pad metal layer 35b is electrically connected to the ohmic reflective layer 31 on the first light emitting cell C1 through the second opening 33b of the lower insulating layer 33. The second pad metal layer 35b may directly contact the ohmic reflective layer 31. Furthermore, as shown in FIG. 7A, the second pad metal layer 35b may be surrounded by the connection part 35ab. Accordingly, a boundary region may be formed between the second pad metal layer 35b and the connection portion 35ab, and the lower insulating layer 33 may be exposed on the boundary region.

The first pad metal layer 35a, the second pad metal layer 35b, and the connecting portions 35ab may be formed together in the same process using the same material. For example, the first pad metal layer 35a, the second pad metal layer 35b, and the connecting portions 35ab may include Ti, Cr, Ni, or the like as an adhesive layer, and may include Al as the metal reflective layer. Further, the first pad metal layer 35a, the second pad metal layer 35b, and the connecting portions 35ab may include a diffusion barrier layer for preventing diffusion of a metal element such as Sn and an oxidation barrier layer for preventing oxidation of the diffusion barrier layer. It may further include. As the diffusion barrier layer, for example, Cr, Ti, Ni, Mo, TiW or W may be used, and Au may be used as the antioxidant layer.

8A and 8B, an upper insulating layer 37 covering the first pad metal layer 35a, the second pad metal layer 35b, and the connecting portions 35ab is formed. The upper insulating layer 31 has an opening 37a exposing the first pad metal layer 35a and an opening 37b exposing the second pad metal layer 35b. In the present embodiment, a plurality of openings 37a are illustrated, but the present invention is not limited thereto, and one opening 37a may be used.

The opening 37b of the upper insulating layer 37 may be disposed to be laterally spaced apart from the second opening 33b of the lower insulating layer 33. By separating the opening 37b of the upper insulating layer 37 and the second opening 33b of the lower insulating layer 33 from overlapping each other, it is possible to prevent the ohmic reflective layer 31 from being contaminated by solder or the like. However, the present invention is not limited thereto, and the second opening 33b of the lower insulating layer 33 and the opening 37b of the upper insulating layer 37 may overlap each other.

Meanwhile, the upper insulating layer 37 may also cover the edge of the lower insulating layer 33 along the edge of the substrate 21, and may expose some region near the edge of the substrate 21. The edge of the upper insulating layer 37 may be formed to be spaced apart from the connecting portions 35ab by at least 11 μm, and at least 15 μm.

The upper insulating layer 37 may be formed of a single layer of a silicon oxide film or a silicon nitride film, or may be formed of a distributed Bragg reflector having a multilayer structure. The upper insulating layer 37 may also be a distributed Bragg reflector in which the first material layer and the second material layer are alternately stacked similarly to the lower insulating layer 33. For example, the first material layer may be SiO ₂ or MgF ₂ , and the second material layer may be a material layer having a higher refractive index than the first material layer. The second material layer can be, for example, TiO ₂ , Nb ₂ O ₅ or ZrO ₂ . In particular, the upper insulating layer 37 may be formed of a distributed Bragg reflector in which SiO 2 layers / ZrO 2 layers are alternately stacked.

The upper insulating layer 37 may also be patterned by using a photolithography and etching process, and thus

openings

37a and 37b may be formed. These

openings

37a and 37b may also have an offset-shaped sidewall like the

openings

33a and 33b of the lower insulating layer 33.

9A and 9B, a first bump pad 39a and a second bump pad 39b are formed on the upper insulating layer 37.

The first bump pad 39a is electrically connected to the first pad metal layer 35a through the opening 37a of the upper insulating layer 37, and the second bump pad 39b is an opening of the upper insulating layer 37. It is electrically connected to the second pad metal layer 35b through 37b.

The first and

second bump pads

39a and 39b may be formed over the plurality of light emitting cells as shown in FIG. 9A. The upper insulating layer 37 prevents an electrical short between the light emitting cells and the first and

second bump pads

39a and 39b.

After the first and

second bump pads

39a and 39b are formed, the bottom surface of the substrate 21 may be partially removed through grinding and / or lapping to reduce the thickness of the substrate 21. Subsequently, the distribution Bragg reflectors 51 to 59 of FIG. 3A are sequentially formed on the substrate 21 to form a stack of the distribution Bragg reflectors 51 to 59, and the substrate 21 is formed in individual chip units. By dividing, light emitting diodes separated from each other are provided. In this case, the substrate 21 may be separated using a laser scribing technique.

The distribution Bragg reflectors 51 to 59 may be sequentially formed from the Distribution Bragg reflectors 51 close to the substrate 21 by using a photographic and etching process or a lift off technique. That is, the first distributed Bragg reflector 51 is formed, and the second distributed Bragg reflector 53, the third distributed Bragg reflector 55, the fourth distributed Bragg reflector 57 and the fifth distributed Bragg reflector 59 are formed thereon. ) Can be formed one after the other. Alternatively, the first material layer and the second material layer are alternately stacked on the substrate 21 so as to have a reflectance of 90% or more, and then the fifth distributed Bragg reflector 59 is patterned from above, and then, By stacking the fourth distributed Bragg reflector 57, the third distributed Bragg reflector 55, and the second distributed Bragg reflector 53, the laminate of the distributed Bragg reflectors 51 to 59 may be formed.

The distributed

Bragg reflectors

distribution Bragg reflectors

Meanwhile, side surfaces of the distribution Bragg reflectors 51 to 59 formed using an etching process or a lift off technique may have an inclination angle, and the inclination angle may be in a range of about 20 to 70 degrees with respect to the surface of the substrate 21.

Referring to FIG. 10, the light emitting diode according to the present exemplary embodiment is generally similar to the light emitting diode described with reference to FIG. 1, except that all of the distribution Bragg reflectors 51 to 59 are disposed on one side of the substrate 21. There is. For example, the distribution Bragg reflectors 51 to 59 may be stacked such that one side surfaces thereof are side by side. Although the light emitting diode of FIG. 1 has a symmetrical directing pattern as shown in FIG. 2, the light emitting diode according to the present embodiment has an asymmetrical shape of the directing pattern of the emitted light.

In this embodiment, one side of the distribution Bragg reflectors 51 to 59 will be described as being parallel, but the position and shape of the Distribution Bragg reflectors 51 to 59 may be modified in various ways. The directing pattern of the emitted light of the diode can be variously changed.

In the above, various embodiments of the present invention have been described, but the present invention is not limited to these embodiments. In addition, the matters or components described with respect to one embodiment may be applied to other embodiments without departing from the technical spirit of the present invention.

Claims

A semiconductor laminate including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; And

A plurality of distributed Bragg reflectors disposed on one side of the semiconductor laminate,

The plurality of distributed Bragg reflectors are stacked with different areas.
The method according to claim 1,

The plurality of distributed Bragg reflectors have a narrower area as the distance from the semiconductor stack.
The method according to claim 3,

The plurality of distributed Bragg reflectors have the same central axis.
The method according to claim 3,

The plurality of distributed Bragg reflectors are stacked so that one side side by side.
The method according to claim 2,

Wherein each of the distributed Bragg reflectors exhibits a reflectance in the range of 5% to 50%.
The method according to claim 5,

And a reflectance of the region where the distribution Bragg reflectors are most overlapped represents a reflectance of 90% or more with respect to light emitted from the active layer.
The method according to claim 6,

Wherein the reflectance of the region where the distribution Bragg reflectors are least overlapped has a reflectance of 10% or less.
The method according to claim 1,

And a substrate positioned between the semiconductor stack and the plurality of distributed Bragg reflectors.
The method according to claim 8,

A lower insulating layer covering the semiconductor stack and including a first opening exposing the first conductive semiconductor layer of the semiconductor stack; And

And a first metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the first opening of the lower insulating layer.
The method according to claim 9,

An ohmic reflective layer disposed on the second conductive semiconductor layer and ohmic contacting the second conductive semiconductor layer,

The lower insulating layer further includes a second opening exposing the ohmic reflective layer.
The method according to claim 10,

An upper insulating layer covering the first metal layer;

A first bump pad and a second bump pad on the upper insulating layer and electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer of the semiconductor laminate, respectively,

The upper insulating layer includes a first opening exposing the first metal layer,

And the first bump pad is connected to the first metal layer through the first opening.
The method according to claim 9,

The semiconductor laminate includes a plurality of light emitting cells spaced apart from each other,

The first metal layer electrically connects adjacent light emitting cells in series to form a series array of light emitting cells, and a first conductive semiconductor layer of the last light emitting cell disposed at an end of the series array. A light emitting diode comprising a first pad metal layer connected to each other.
The method according to claim 12,

An ohmic reflective layer disposed on the second conductive semiconductor layer of each light emitting cell and ohmic contacting the second conductive semiconductor layer; And

A second pad metal layer disposed on the lower insulating layer and electrically connected to the ohmic reflective layer of the first light emitting cell disposed at the first end of the series array;

The lower insulating layer further includes second openings exposing the ohmic reflective layer on each light emitting cell.

And the second pad metal layer is electrically connected to an ohmic reflective layer on the first light emitting cell through the second opening.
The method according to claim 12,

An upper insulating layer covering the connection portion (s) and the first and second pad metal layers, the upper insulating layer having openings exposing top surfaces of the first and second pad metal layers, respectively; And

And a first bump pad and a second bump pad respectively connected to upper surfaces of the first pad metal layer and the second pad metal layer exposed by the openings of the upper insulating layer.
The method according to claim 14,

The first bump pad and the second bump pad are respectively disposed over an upper region of two or more light emitting cells.
A semiconductor laminate including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; And

A stack of distributed Bragg reflectors disposed on one side of the semiconductor stack,

The stack of distributed Bragg reflectors includes regions of different thicknesses,

Wherein said stack of distributed Bragg reflectors has a higher reflectance in a thicker region.
The method according to claim 16,

Wherein said stack of distributed Bragg reflectors exhibits the highest reflectance in the center and the lowest reflectance near the edge.
The method according to claim 16,

At least a portion of the light generated in the active layer is emitted to the outside through the stack of distributed Bragg reflectors.
The method according to claim 18,

And a substrate disposed between the semiconductor stack and the stack of distributed Bragg reflectors.
The method according to claim 19,

And a first bump pad and a second bump pad disposed on the semiconductor laminate and electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer, respectively.