KR20170091887A - Transient voltage suppressor and manufacturing method thereof - Google Patents

Transient voltage suppressor and manufacturing method thereof Download PDF

Info

Publication number
KR20170091887A
KR20170091887A KR1020160012714A KR20160012714A KR20170091887A KR 20170091887 A KR20170091887 A KR 20170091887A KR 1020160012714 A KR1020160012714 A KR 1020160012714A KR 20160012714 A KR20160012714 A KR 20160012714A KR 20170091887 A KR20170091887 A KR 20170091887A
Authority
KR
South Korea
Prior art keywords
layer
buried
isolation
epitaxial layer
conductivity type
Prior art date
Application number
KR1020160012714A
Other languages
Korean (ko)
Other versions
KR101779588B1 (en
Inventor
장희원
김현식
Original Assignee
주식회사 케이이씨
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 케이이씨 filed Critical 주식회사 케이이씨
Priority to KR1020160012714A priority Critical patent/KR101779588B1/en
Publication of KR20170091887A publication Critical patent/KR20170091887A/en
Application granted granted Critical
Publication of KR101779588B1 publication Critical patent/KR101779588B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

A trench process is applied to form a plurality of isolation layers and a double buried layer of a first buried layer of the second conductivity type and a third buried layer of the first conductivity type is formed to reduce the capacitance and to increase the maximum allowable surge current (Ipp) and lowering a clamping voltage, and a method of manufacturing the same.
As an example, a substrate of a first conductivity type; A first epitaxial layer of a first conductivity type formed on the substrate; A first buried layer of a second conductivity type formed inside the first epitaxial layer and formed in a ring shape; a second buried layer of a first conductivity type formed inside the first buried layer; A second epitaxial layer of a first conductivity type formed on the first epitaxial layer and the first and second buried layers; A third buried layer of the first conductivity type formed in the second epitaxial layer and formed on the first buried layer and the second buried layer; A third epitaxial layer of a first conductivity type formed on top of the second epitaxial layer and the third buried layer; A plurality of isolation layers formed from the surface of the third epitaxial layer toward the substrate; And a second conductive type region formed inward from the surface of the third epitaxial layer, the second conductive type region being spaced apart from each other by the isolation layer.

Description

[0001] Transient voltage suppressor and manufacturing method [0002]

The present invention relates to a transient voltage suppressing element and a method of manufacturing the same.

Referring to FIG. 1, the operation principle and circuit diagram of a conventional transient voltage suppressing element are shown.

A transient voltage suppressing device TVS (for example, varistor, thyristor, diode (rectifier / zener)) is connected in parallel between a power source VG and a load RLOAD as shown in FIG. One side of the transient voltage suppressing element is connected to the ground (GND).

With this configuration, when the transient voltage exceeding the voltage required in the load RLOAD is input, the transient current ITV due to the transient voltage flows to the ground GND via the transient voltage suppressing element TVS, Only the stabilized low voltage is applied to the load RLOAD so that the load RLOAD is safely protected from the transient voltage.

A trench process is applied to form a plurality of isolation layers and a double buried layer of a first buried layer of the second conductivity type and a third buried layer of the first conductivity type is formed to reduce the capacitance and to increase the maximum allowable surge current (Ipp) and lowering the clamping voltage, and a method of manufacturing the same.

A transient voltage suppressor according to the present invention includes: a substrate of a first conductivity type; A first epitaxial layer of a first conductivity type formed on the substrate; A first buried layer of a second conductivity type formed inside the first epitaxial layer and formed in a ring shape; a second buried layer of a first conductivity type formed inside the first buried layer; A second epitaxial layer of a first conductivity type formed on the first epitaxial layer and the first and second buried layers; A third buried layer of the first conductivity type formed in the second epitaxial layer and formed on the first buried layer and the second buried layer; A third epitaxial layer of a first conductivity type formed on top of the second epitaxial layer and the third buried layer; A plurality of isolation layers formed from the surface of the third epitaxial layer toward the substrate; And a second conductive type region formed inward from the surface of the third epitaxial layer and spaced apart from each other by the isolation layer.

The third buried layer may contact the first buried layer and the second buried layer.

Wherein the isolation layer is formed in a circular ring shape and includes a first isolation layer formed at the center, a second isolation layer formed outside the first isolation layer, a third isolation layer formed outside the second isolation layer, And a fourth isolation layer formed outside the third isolation layer.

Wherein the first isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer and the second buried layer and the second isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer and the second buried layer, Wherein the third isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer and the fourth isolation layer is formed from the surface of the third epitaxial layer to the inside of the third epitaxial layer, The third buried layer and the first buried layer.

The second conductive type region may be formed inside the first isolation layer and between the second isolation layer and the third isolation layer.

A first diode may be formed on the junction surface of the second conductive type region and the third epitaxial layer on the inner side of the first isolation layer.

A second diode is formed on a junction surface between the second isolation layer and the third isolation layer, the junction surface of the second conductivity type region and the third epitaxial layer, and a junction between the third and the third isolation layers, And a second zener diode may be formed on a junction surface of the first buried layer and the substrate.

And an upper electrode formed on the third epitaxial layer and electrically connecting the second conductive type region may be further formed.

According to another aspect of the present invention, there is provided a method of fabricating a transient voltage suppressor, including: forming a first epitaxial layer of a first conductivity type on a substrate of a first conductivity type; A first embedding layer forming step of forming a ring-shaped first buried layer of a second conductivity type inside the first epitaxial layer and forming a second buried layer of the first conductivity type inside the first buried layer; A second epitaxial layer forming step of forming a second epitaxial layer of a first conductivity type on the first epitaxial layer and the first and second buried layers; Forming a second buried layer in the second epitaxial layer and forming a third buried layer of the first conductivity type on the first and second buried layers; A third epitaxial layer forming step of forming a third epitaxial layer of the first conductivity type on the second epitaxial layer and the third buried layer; Forming a plurality of spaced apart isolation layers from the surface of the third epitaxial layer toward the substrate; And forming a second conductive type region inwardly from the surface of the third epitaxial layer, the second conductive type region being spaced apart from each other by the isolation layer.

The third buried layer may be formed in contact with the first buried layer and the second buried layer in the second buried layer formation step.

In the isolation layer formation step, the isolation layer is formed in a circular ring shape, and the isolation layer includes a first isolation layer formed at the center, a second isolation layer formed outside the first isolation layer, And a fourth isolation layer formed on the outer side of the third isolation layer.

Wherein the first isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer and the second buried layer and the second isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer and the second buried layer, Wherein the third isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer and the fourth isolation layer is formed from the surface of the third epitaxial layer to the inside of the third epitaxial layer, The third buried layer and the first buried layer.

In the forming of the second conductivity type region, the second conductivity type region may be formed inside the first isolation layer and between the second isolation layer and the third isolation layer.

A first diode may be formed on the junction surface of the second conductive type region and the third epitaxial layer on the inner side of the first isolation layer.

A second diode is formed on a junction surface between the second isolation layer and the third isolation layer, the junction surface of the second conductivity type region and the third epitaxial layer, and a junction between the third and the third isolation layers, And a second zener diode may be formed on a junction surface of the first buried layer and the substrate.

And forming an upper electrode electrically connecting the second conductive type region on the third epitaxial layer after the second conductive type region forming step.

The transient voltage suppressing element and the method of fabricating the same according to the embodiment of the present invention are characterized in that a plurality of isolation layers are formed by applying a trench process, and a first buried layer of the second conductive type and a double layer of the third buried layer of the first conductive type By forming the buried layer, the capacitance can be reduced, the maximum allowable surge current Ipp can be improved, and the clamping voltage can be lowered.

Referring to FIG. 1, the operation principle and circuit diagram of a conventional transient voltage suppressing element are shown.
2 is a flowchart illustrating a method of manufacturing a transient voltage suppressing device according to an embodiment of the present invention.
3A to 3I are sectional views sequentially illustrating a method of manufacturing a transient voltage suppressor according to an embodiment of the present invention.
4 illustrates a transient voltage suppressor according to an embodiment of the present invention and a corresponding equivalent circuit.
5 shows an equivalent circuit using two transient voltage suppressing elements connected in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

Here, parts having similar configurations and operations throughout the specification are denoted by the same reference numerals. In addition, when a part is electrically connected to another part, it includes not only a direct connection but also a case where the other part is connected to the other part in between.

2 is a flowchart illustrating a method of manufacturing a transient voltage suppressing device according to an embodiment of the present invention. 3A to 3I are sectional views sequentially illustrating a method of manufacturing a transient voltage suppressor according to an embodiment of the present invention.

Referring to FIG. 2, a method of fabricating a transient voltage suppressor according to an exemplary embodiment of the present invention includes forming a first epitaxial layer (S1), a first buried layer (S2), a second epitaxial layer The isolation layer formation step S6, the second conductivity type region formation step S7, and the electrode formation step S8 are performed. .

3A, in the first epitaxial layer forming step S1, a substrate 110 of a first conductivity type is prepared, a first epitaxial layer 121 is formed on the substrate 110, . The substrate 110 has a plate shape including an upper surface and a lower surface. The substrate 110 may be, for example, an N + + type semiconductor substrate formed by implanting an impurity such as arsenic (As), phosphorus (P), or antimony (Sb), which is a Group 5 element, into the intrinsic semiconductor at high concentration. Here, the high concentration means that the concentration is relatively higher than the impurity concentration of the epitaxial layer 120 to be described later. On the other hand, the substrate 110 of the first conductivity type may be a P-type in which impurity such as gallium (Ga), indium (In), or boron (B), which is a group III element, is implanted into the intrinsic semiconductor at high concentration. However, in the present invention, it is assumed that the substrate 110 is N-type.

For example, the first epitaxial layer 121 may be formed by depositing a gas such as SiH 4 and a pentavalent element such as arsenic (As), phosphorus (P), or antimony (P) on the upper surface of the substrate 110 at a high temperature of 600 to 2000 ° C. Sb) may be deposited on the surface of the substrate 110 at a low concentration.

3B and 3C, in the first embedding layer forming step S2, a first embedding layer 131 of the second conductivity type and a second embedding layer 131 of the second embedding layer 121 are formed in the first epitaxial layer 121, The second buried layer 132 of the first conductivity type is formed inside the first buried layer 131. After forming the first buried layer 131 of the second conductivity type in the first buried layer forming step S2, a second buried layer 132 of the first conductivity type is formed inside the first buried layer 131 . Here, the first buried layer 131 is formed to have a certain depth from the upper surface of the first epitaxial layer 121 toward the inside thereof, and is formed in the shape of an annular hollow ring. Accordingly, the first buried layer 131 is substantially in the form of a ring connected to each other, but the cross-sectional view thereof seems to be spaced apart from each other, as shown in Fig. 3B. The second buried layer 132 is also formed inside the first buried layer 131 at a predetermined depth from the top surface of the first epitaxial layer 121. That is, the second buried layer 132 is formed in the inner hole of the first buried layer 131.

The first buried layer 131 may be formed by forming an insulating film (not shown) such as a silicon oxide film or a nitrogen oxide film on the upper surface of the first epitaxial layer 121 in a region other than the region where the first buried layer 131 is to be formed , A Group III element such as gallium (Ga), indium (In) or boron (B) may be directly implanted or a thermal diffusion process may be used to form the first buried layer 131 of P + type. The second buried layer 132 may be formed by forming an insulating film (not shown) such as a silicon oxide film or a nitrogen oxide film on the upper surface of the first epitaxial layer 121 in a region other than the region where the second buried layer 132 is formed, An impurity such as arsenic (As), phosphorus (P), or antimony (Sb), which is a Group 5 element, may be directly implanted or a second buried layer 132 of N + type may be formed using a thermal diffusion process.

On the other hand, a bottom insulating film may be formed on the bottom surface of the substrate 110. The insulating film may be formed of any one selected from the group consisting of a silicon oxide film, a nitrogen oxide film, an undoped poly silicon film, a phospho-silicate-glass (PSG) film, a borophosphorosilicate glass (BPSG) However, the present invention is not limited thereto. The insulating layer prevents auto-doping of the first conductive type substrate 110 having a high concentration.

3D, a second epitaxial layer 122 is formed on the first epitaxial layer 121 in the second epitaxial layer forming step S3. For example, at a high temperature of 600 to 2000 ° C., a gas such as SiH 4 and a pentavalent element (As), phosphorus (P), or phosphorus (P) are formed on the first epitaxial layer 121 and the first and second buried layers 131 and 132 So that an N-type second epitaxial layer 122 is deposited on the first epitaxial layer 121 and the first and second buried layers 131 and 132 by flowing a gas containing antimony (Sb) or the like at a low concentration together can do. At this time, the second epitaxial layer 122 is deposited on the surfaces of the first and second buried layers 131 and 132, and the first and second buried layers 131 and 132 are doped into the second epitaxial layer 122 Can be further diffused.

3E, a third buried layer 133 of the first conductivity type is formed in the second epitaxial layer 122 in the second buried layer forming step S4. The third buried layer 133 is formed to have a certain depth from the top surface of the second epitaxial layer 122 toward the inside and is formed on the first and second buried layers 131 and 132. The third buried layer 133 may be formed by forming an insulating film (not shown) such as a silicon oxide film or a nitrogen oxide film on the upper surface of the second epitaxial layer 122 in a region other than the region where the third buried layer 133 is formed Impurity such as arsenic (As), phosphorus (P), or antimony (Sb), which is a Group 5 element, may be directly implanted or a third buried layer 133 of N + type may be formed using a thermal diffusion process.

The third epitaxial layer 123 of the first conductivity type is formed on the second epitaxial layer 122 and the third buried layer 133 in the third epitaxial layer formation step S5 as shown in FIG. Is formed. For example, a gas such as SiH 4 and a pentavalent element such as arsenic (As), phosphorus (P), or antimony (P) are deposited on the second epitaxial layer 122 and the third buried layer 133 at a high temperature of 600 to 2000 ° C. The third epitaxial layer 123 may be deposited on the second epitaxial layer 122 and the third buried layer 133 by flowing a low concentration of the gas including the n-type epitaxial layer 123 and the n-type epitaxial layer 123 together. At this time, the third epitaxial layer 123 is deposited on the surface of the third buried layer 133, and the third buried layer 133 is further diffused into the third epitaxial layer 123 by the doping gases have. As described above, the first, second, and third epitaxial layers 121, 122, and 123 are collectively referred to as an epitaxial layer 120.

The isolation layer 140 is formed from the surface of the third epitaxial layer 123 toward the substrate 110 in the isolation layer formation step S6 as shown in FIG. The isolation layer 140 includes a first isolation layer 141, a second isolation layer 142, a third isolation layer 143, and a fourth isolation layer 144 from the center to the outside. 3G, the isolation layers 140 are spaced apart from each other and a pair of the isolation layers 140 are formed on both sides of the isolation layer 140. However, the isolation layer 140 may be formed in a circular ring shape similar to the first buried layer 131 .

The isolation layer 140 forms a pattern by exposing, for example, a mask (not shown) that primarily determines the position of the isolation layer 140. Then, trenches can be formed through dry etching using mask openings by reactive ion etching. Thereafter, the isolation layer 140 may be formed by implanting an insulating material such as a silicon oxide film or a nitrogen oxide film into the trench. However, the method of forming the isolation layer 140 by this method is not limited.

The first isolation layer 141 is located at the most central position and has a circular ring shape with an empty center. The first isolation layer 141 is formed from the surface of the third epitaxial layer 123 to the inside of the third buried layer 133 and the inside of the second buried layer 132. A second conductive type region 151 to be described later is formed inside the first isolation layer 141.

The second isolation layer 142 has an annular ring shape at the center and is formed outside the first isolation layer 141. The second isolation layer 142 is formed from the surface of the third epitaxial layer 123 to the third buried layer 133 and the first buried layer 131. In particular, the second isolation layer 142 may be formed at a position adjacent to the inside of the first buried layer 131.

The third isolation layer 143 has an annular ring shape having a center and is formed outside the second isolation layer 142. The third isolation layer 143 is formed from the surface of the third epitaxial layer 123 to the inside of the third buried layer 133.

The fourth isolation layer 144 has an annular ring shape at the center and is formed outside the third isolation layer 143. The fourth isolation layer 144 is formed from the surface of the third epitaxial layer 123 to the third buried layer 133 and the first buried layer 131. In addition, the fourth isolation layer 144 may be formed at a position adjacent to the outside of the first buried layer 131.

3H, in the second conductive type region forming step S7, the second conductive type regions 151 and 152 are formed inwardly from the surface of the third epitaxial layer 123. In this case, as shown in FIG.

More specifically, the second conductive type region 151 is formed on the inner side of the first isolation layer 141 and extends inward from the surface of the third epitaxial layer 123 on the second and third buried layers 132 and 133 Ions. The width of the second conductivity type region 151 is equal to the width of the first isolation layer 141. The second conductive type region 151 may be formed by first forming an insulating film (not shown) such as a silicon oxide film or a nitrogen oxide film and then directly forming a Group III element such as gallium (Ga), indium (In), or boron Ion implantation or a thermal diffusion process may be used to form the second conductivity type region 151 of P + type. In addition, the outer periphery of the second conductivity type region 151 is surrounded by the first isolation layer 141. Accordingly, the second conductive type region 151 is separated from the third epitaxial layer 123 outside the second conductive type region 151 by the first isolation layer 141.

The second conductive type region 152 is also formed between the second isolation layer 142 and the third isolation layer 143 and the third epitaxial layer 123 on the first and third buried layers 131 and 133 And ions are implanted inward. The second conductive type region 152 is formed deeper inside the third epitaxial layer 123 than the second conductive type region 151 formed in the first isolation layer 141. The width of the second conductivity type region 152 in the horizontal direction is the same as the width between the second isolation layer 142 and the third isolation layer 143. That is, the inner and outer peripheries of the second conductive type region 152 are surrounded by the second isolation layer 142 and the third isolation layer 143, respectively. The second conductive type region 152 is spaced apart from the third epitaxial layer 123 which is dented inside and outside the second conductive type region 152 by the second and third isolation layers 142 and 143 . That is, the second conductive type region 152 may be formed in a circular ring shape having a hole at the center thereof. The second conductive type region 152 may be formed by first forming an insulating film (not shown) such as a silicon oxide film or a nitrogen oxide film and then directly forming a Group III element such as gallium (Ga), indium (In), or boron Ion implantation or a thermal diffusion process may be used to form the second conductivity type region 152 of P + type.

The second conductivity type regions 151 and 152 between the second isolation layer 142 and the third isolation layer 143 are formed substantially simultaneously in one step.

3I, in the electrode forming step S8, the upper electrode 170 is formed on the second conductive type regions 151 and 152, and the lower electrode 180 is formed on the lower side of the substrate 110. [ . Here, the insulating layer 160 is formed before the upper electrode 170 is formed.

The insulating layer 160 includes a first insulating layer 161 and a second insulating layer 162. The first insulating layer 161 is formed on the third epitaxial layer 123 and the second conductivity type regions 151 and 152 and the upper portion of the first isolation layer 141 and the second isolation layer 142 Respectively. At this time, the first insulating layer 161 exposes a part of the second conductivity type regions 151 and 152 to the outside. The second insulating layer 162 is spaced apart from the first insulating layer 161 and is formed on the third epitaxial layer 123 and the second conductive type region 152, The first isolation layer 143, and the fourth isolation layer 144, respectively. The second insulating layer 162 exposes a portion of the second conductive type region 152 to the outside. The insulating layer 160 may be formed of any one selected from the group consisting of a silicon oxide layer, a nitrogen oxide layer, undoped polysilicon, Phospho-Silicate-Glass (PSG), borophosphorosilicate glass However, the present invention is not limited thereto.

The upper electrode 170 is formed on the upper surface of the second conductivity type regions 151 and 152 exposed to the outside through the insulating layer 160. The upper electrode 170 may be formed by sequentially sputtering or sequentially plating a selected one of molybdenum (Mo), aluminum (Al), nickel (Ni), gold (Au), and the like, But is not limited to.

In addition, the lower electrode 180 may be formed on the lower surface of the substrate 110. The lower electrode 180 may be formed by sequentially sputtering or sequentially plating a selected one of molybdenum (Mo), aluminum (Al), nickel (Ni), gold (Au) But is not limited to.

4 illustrates a transient voltage suppressor according to an embodiment of the present invention and a corresponding equivalent circuit. 5 shows an equivalent circuit using two transient voltage suppressing elements connected in accordance with an embodiment of the present invention.

On the other hand, the P-type and N-type junctions of the transient voltage suppressor have characteristics of a diode and a capacitor. That is, although the junctions of the P-type and N-type are shown as diodes in the drawing, they may be represented by capacitors. In the transient voltage suppressor, the upper electrode 170 and the lower electrode 180 may be used as input / output terminals.

4, the transient voltage suppressor according to the embodiment of the present invention is located inside the first isolation layer 141 and is located between the second conductive type region 151 and the third epitaxial layer 123 A first diode 201 formed on the junction surface and a second diode 202 connected in parallel to the first diode 201. The first diode 201 and the second diode 202 are connected to each other. Here, the second diode 202, the first Zener diode 203, and the second Zener diode 204 are located between the second isolation layer 142 and the third isolation layer 143, Lt; / RTI > The second diode 202 is formed on a junction surface between the second conductive type region 152 and the third epitaxial layer 123 and the first zener diode 203 is formed on the junction between the third buried layer 133 and the third epitaxial layer 123. [ 1 buried layer 131 and the second Zener diode 204 is formed on a junction surface between the first buried layer 131 and the substrate 110. [

Further, as shown in FIG. 5, it is possible to implement a bidirectional transient voltage suppressor having low capacitance by connecting two transient voltage suppressing elements as described above in parallel. In addition, such a bidirectional transient voltage suppressing element can improve the maximum allowable surge current (Ipp) characteristic and realize a low limiting voltage (clamping voltage). For example, the present invention is a bidirectional transient voltage suppressing element of 5V / 0.5 pF class, having an ESD of 30KV or more and an Ipp value of 12A or more.

The transient voltage suppressor according to the present invention has a low capacitance and a high Ipp and a low limiting voltage (Vpp) by forming a first buried layer of the second conductivity type and a third buried layer of the first conductivity type on the first buried layer, (TVS with Clamping Voltage).

It is to be understood that the present invention is not limited to the above-described embodiment, and various modifications and changes may be made by those skilled in the art without departing from the scope of the present invention. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

110: substrate 120: epitaxial layer
121: first epitaxial layer 122: second epitaxial layer
123: third epitaxial layer 131: first buried layer
132: second buried layer 133: third buried layer
140: Isolation layer 151, 152: Second conductive type region
160: insulating film 170: upper electrode
180: lower electrode

Claims (16)

A substrate of a first conductivity type;
A first epitaxial layer of a first conductivity type formed on the substrate;
A first buried layer of a second conductivity type formed inside the first epitaxial layer and formed in a ring shape; a second buried layer of a first conductivity type formed inside the first buried layer;
A second epitaxial layer of a first conductivity type formed on the first epitaxial layer and the first and second buried layers;
A third buried layer of the first conductivity type formed in the second epitaxial layer and formed on the first buried layer and the second buried layer;
A third epitaxial layer of a first conductivity type formed on top of the second epitaxial layer and the third buried layer;
A plurality of isolation layers formed from the surface of the third epitaxial layer toward the substrate; And
And a second conductivity type region formed inward from the surface of the third epitaxial layer and spaced apart from each other by the isolation layer. The method according to claim 1,
And the third buried layer is in contact with the first buried layer and the second buried layer. The method according to claim 1,
Wherein the isolation layer is formed in a circular ring shape,
A second isolation layer formed on the outer side of the first isolation layer, a third isolation layer formed on the outer side of the second isolation layer, and a fourth isolation layer formed on the outer side of the third isolation layer, And wherein the transient voltage suppressing element comprises: The method of claim 3,
The first isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer and the second buried layer,
The second isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer and the first buried layer,
The third isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer,
Wherein the fourth isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer and the first buried layer. 5. The method of claim 4,
And the second conductive type region is formed between the second isolation layer and the third isolation layer, inside the first isolation layer. 5. The method of claim 4,
And a first diode is formed on a junction surface of the second conductivity type region and the third epitaxial layer on the inner side of the first isolation layer. 5. The method of claim 4,
Between the second isolation layer and the third isolation layer,
A second diode is formed on a junction surface between the second conductive type region and the third epitaxial layer, a first Zener diode is formed on a junction surface between the third and the third buried layers, Wherein a second zener diode is formed on a junction surface of the second transistor. The method according to claim 1,
And an upper electrode formed on the third epitaxial layer and electrically connecting the second conductive type region. A first epitaxial layer forming step of forming a first epitaxial layer of a first conductivity type on the substrate of the first conductivity type;
A first embedding layer forming step of forming a ring-shaped first buried layer of a second conductivity type inside the first epitaxial layer and forming a second buried layer of the first conductivity type inside the first buried layer;
A second epitaxial layer forming step of forming a second epitaxial layer of a first conductivity type on the first epitaxial layer and the first and second buried layers;
Forming a second buried layer in the second epitaxial layer and forming a third buried layer of the first conductivity type on the first and second buried layers;
A third epitaxial layer forming step of forming a third epitaxial layer of the first conductivity type on the second epitaxial layer and the third buried layer;
Forming a plurality of spaced apart isolation layers from the surface of the third epitaxial layer toward the substrate; And
And forming a second conductive type region inwardly from the surface of the third epitaxial layer and spaced apart from each other by the isolation layer. 10. The method of claim 9,
Wherein the third buried layer is formed in contact with the first buried layer and the second buried layer in the second buried layer formation step. 10. The method of claim 9,
In the isolation layer formation step, the isolation layer is formed in a circular ring shape,
Wherein the isolation layer comprises a first isolation layer formed at the center, a second isolation layer formed outside the first isolation layer, a third isolation layer formed outside the second isolation layer, and a second isolation layer formed outside the third isolation layer 4 isolating layer. ≪ RTI ID = 0.0 > 5. < / RTI > 12. The method of claim 11,
The first isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer and the second buried layer,
The second isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer and the first buried layer,
The third isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer,
Wherein the fourth isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer and the first buried layer. 13. The method of claim 12,
Wherein the second conductivity type region is formed in the first isolation layer and between the second isolation layer and the third isolation layer in the second conductivity type region formation step. 13. The method of claim 12,
Wherein a first diode is formed on a junction surface of the second conductive type region and the third epitaxial layer on the inner side of the first isolation layer. 13. The method of claim 12,
Between the second isolation layer and the third isolation layer,
A second diode is formed on a junction surface between the second conductive type region and the third epitaxial layer, a first Zener diode is formed on a junction surface between the third and the third buried layers, Wherein a second Zener diode is formed on a junction surface of the second Zener diode. 10. The method of claim 9,
And forming an upper electrode electrically connecting the second conductive type region to the upper portion of the third epitaxial layer after the forming of the second conductive type region. / RTI >
KR1020160012714A 2016-02-02 2016-02-02 Transient voltage suppressor and manufacturing method thereof KR101779588B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020160012714A KR101779588B1 (en) 2016-02-02 2016-02-02 Transient voltage suppressor and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020160012714A KR101779588B1 (en) 2016-02-02 2016-02-02 Transient voltage suppressor and manufacturing method thereof

Publications (2)

Publication Number Publication Date
KR20170091887A true KR20170091887A (en) 2017-08-10
KR101779588B1 KR101779588B1 (en) 2017-09-18

Family

ID=59652212

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020160012714A KR101779588B1 (en) 2016-02-02 2016-02-02 Transient voltage suppressor and manufacturing method thereof

Country Status (1)

Country Link
KR (1) KR101779588B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101951195B1 (en) * 2017-08-22 2019-02-25 주식회사 시지트로닉스 Bi-directional ULC-TVS semiconductor device and manufacturing method thereof
US20230253397A1 (en) * 2022-02-09 2023-08-10 Semiconductor Components Industries, Llc Semiconductor devices and methods of manufacturing semiconductor devices

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007024355B4 (en) 2007-05-24 2011-04-21 Infineon Technologies Ag Method for producing a protective structure
JP2012182381A (en) 2011-03-02 2012-09-20 Panasonic Corp Semiconductor device
KR101570217B1 (en) 2014-07-09 2015-11-18 주식회사 케이이씨 transient voltage suppressor and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101951195B1 (en) * 2017-08-22 2019-02-25 주식회사 시지트로닉스 Bi-directional ULC-TVS semiconductor device and manufacturing method thereof
US20230253397A1 (en) * 2022-02-09 2023-08-10 Semiconductor Components Industries, Llc Semiconductor devices and methods of manufacturing semiconductor devices
US11948933B2 (en) * 2022-02-09 2024-04-02 Semiconductor Components Industries, Llc Semiconductor devices and methods of manufacturing semiconductor devices

Also Published As

Publication number Publication date
KR101779588B1 (en) 2017-09-18

Similar Documents

Publication Publication Date Title
KR101414005B1 (en) Transient voltage suppressor and its manufacturing method
KR101570217B1 (en) transient voltage suppressor and manufacturing method thereof
US9177952B2 (en) ESD protection with asymmetrical bipolar-based device
JP6468631B2 (en) Laminated protective device and manufacturing method thereof
KR101686569B1 (en) Transient Voltage Suppressor and Manufacturing Method thereof
EP2827373B1 (en) Protection device and related fabrication methods
KR100952267B1 (en) Transient voltage suppressor and manufacturing method thereof
KR101779588B1 (en) Transient voltage suppressor and manufacturing method thereof
KR101621145B1 (en) Transient voltage suppressor and Integrated Circuit using the Same
US10629715B2 (en) Unidirectional ESD protection with buried breakdown thyristor device
KR101893673B1 (en) Transient voltage suppressor and manufacturing method thereof
KR101731587B1 (en) Transient voltage suppressor and manufacturing method thereof
KR101686568B1 (en) Transient Voltage Suppressor and Manufacturing Method thereof
KR101850851B1 (en) Transient voltage suppressor and manufacturing method thereof
CN103178121B (en) Pin diode and manufacturing method thereof
KR101607207B1 (en) Transient voltage suppressor and manufacturing method thereof
EP2725615B1 (en) Semiconductor device comprising a diode and a bipolar transistor and method for producing such a device
KR100945626B1 (en) Transient voltage suppressor circuit
KR102187243B1 (en) Uni-directional Transient Voltage Suppressor and manufacturing method thereof
KR102171860B1 (en) Uni-directional Transient Voltage Suppressor Having Snap-Back structure and manufacturing method thereof
KR101657160B1 (en) Transient voltage suppressor and manufacturing method thereof
KR20190027119A (en) Bidirectional Low Clamping Transient Voltage Suppression Device Using Lateral Type Schokley Diodes and manufacturing method thereof
KR102103195B1 (en) Bidirectional Low Clamping Transient Voltage Suppression Device Using Trigger Type Schokley Diodes and manufacturing method thereof
KR102171861B1 (en) Transient voltage suppression device and manufacturing method thereof
KR101955098B1 (en) Transient voltage suppressor and manufacturing method thereof

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant