KR101686569B1 - Transient Voltage Suppressor and Manufacturing Method thereof - Google Patents

Transient Voltage Suppressor and Manufacturing Method thereof Download PDF

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Publication number
KR101686569B1
KR101686569B1 KR1020150086593A KR20150086593A KR101686569B1 KR 101686569 B1 KR101686569 B1 KR 101686569B1 KR 1020150086593 A KR1020150086593 A KR 1020150086593A KR 20150086593 A KR20150086593 A KR 20150086593A KR 101686569 B1 KR101686569 B1 KR 101686569B1
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South Korea
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layer
conductive
conductivity type
epitaxial layer
type region
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KR1020150086593A
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Korean (ko)
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김현식
장희원
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주식회사 케이이씨
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors with potential-jump barrier or surface barrier
    • H01L29/93—Variable capacitance diodes, e.g. varactors

Abstract

According to the present invention, disclosed are a transient voltage suppressing device and a manufacturing method thereof for increasing a maximum current value on the basis of a resistance decrease, and decreasing a capacitance. According to an embodiment of the present invention, the transient voltage suppressing device includes: a first conductive type substrate; a first epitaxial layer having a second conductivity type and formed on an upper part of the substrate; a second conductivity type buried layer formed on an upper part of the first epitaxial layer; a first conductivity type buried layer formed on an upper part of the second conductivity type buried layer; a second epitaxial layer having a second conductivity type and formed on upper parts of the first epitaxial layer, the second conductivity type buried layer and the first conductivity type buried layer; a first conductivity type region and a second conductivity type region spaced apart from each other toward the inside of the second epitaxial layer from a surface thereof; a plurality of isolation layers formed from the surface of the second epitaxial layer towards the substrate, in a region corresponding to peripheries of the first conductivity type region and the second conductivity type region; an isolation layer formed on surfaces of the insulation layer and the second epitaxial layer, in the region corresponding to the peripheries of the first conductivity type region and the second conductivity type region; and an electrode formed on the surface of the first conductivity type region and the second conductivity type region which are exposed through the insulation layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a transient voltage suppressor,

The present invention relates to a transient voltage suppressing element and a method of manufacturing the same.

Referring to FIG. 1, the operation principle and circuit diagram of a conventional transient voltage suppressing element are shown.

A transient voltage suppressing device TVS (for example, varistor, thyristor, diode (rectifier / zener)) is connected in parallel between a power source VG and a load RLOAD as shown in FIG. One side of the transient voltage suppressing element is connected to the ground (GND).

With this configuration, when the transient voltage exceeding the voltage required in the load RLOAD is input, the transient current ITV due to the transient voltage flows to the ground GND via the transient voltage suppressing element TVS, Only the stabilized low voltage is applied to the load RLOAD so that the load RLOAD is safely protected from the transient voltage.

The present invention provides a transient voltage suppressing element and a method of manufacturing the transient voltage suppressing element, which can realize a maximum current value and a capacitance value inside the device at the center and the outside by reducing the resistance deviation at the center and the outside thereof.

A method of manufacturing a transient voltage suppressing device according to the present invention includes: a substrate of a first conductivity type; A first epitaxial layer of a second conductivity type formed on top of the substrate; A second conductive buried layer formed on the first epitaxial layer; A first conductive buried layer formed on the second conductive buried layer; A second epitaxial layer of a second conductivity type formed on the first epitaxial layer, the second conductive buried layer, and the first conductive buried layer; A first conductive type region and a second conductive type region formed so as to be spaced apart from each other in a direction from the surface of the second epitaxial layer toward the inside; A plurality of isolation layers formed from the surface of the second epitaxial layer toward the substrate in regions corresponding to the peripheries of the first conductivity type region and the second conductivity type region; An insulating film formed on a surface of the isolation layer and the second epitaxial layer in a region corresponding to a periphery of the first conductive type region and the second conductive type region; And electrodes formed on the surfaces of the first conductive type region and the second conductive type region exposed through the insulating film.

Here, the second conductive type buried layer may be in contact with the substrate.

The first conductive buried layer may be located in a central region of the second conductive buried layer.

The isolation layer may include a first isolation layer formed from the surface of the second epitaxial layer to the inside of the first conductive type buried layer at the center of the second epitaxial layer; A second isolation layer spaced from the outside of the first isolation layer and extending from the surface of the second epitaxial layer to the inside of the second conductivity type buried layer; And a third isolation layer spaced from the outside of the second isolation layer and extending from the surface of the second epitaxial layer to the inside of the second conductivity type buried layer.

In addition, the second conductivity type region may be formed inside the first isolation layer, inward from the surface of the second epitaxial layer.

In addition, the first conductivity type region may be formed in the region between the second isolation layer and the third isolation layer, from the surface of the second epitaxial layer toward the inside.

Further, a bottom electrode may be further formed on the bottom surface of the substrate.

A method of fabricating a transient voltage suppressing device according to the present invention includes: preparing a substrate of a first conductivity type; A first epitaxial layer forming step of forming a first epitaxial layer of a second conductivity type on the substrate; Forming a second conductive buried layer on the first epitaxial layer; A first conductive buried layer forming step of forming a first conductive buried layer on the second conductive buried layer; A second epitaxial layer forming step of forming a second epitaxial layer of a second conductivity type on the first epitaxial layer, the second conductive buried layer, and the first conductive buried layer; Forming a plurality of spaced apart isolation layers from the surface of the second epitaxial layer toward the substrate; A first and a second conductivity type region forming step of forming a first conductivity type region and a second conductivity type region inward from the surface of the second epitaxial layer inwardly of the respective isolation layers; Forming an insulating layer on the first conductive type region and the second conductive type region to expose a portion of the first conductive type region and the second conductive type region in a region corresponding to the periphery of the first conductive type region and the second conductive type region; And an electrode forming step of forming electrodes on the surfaces of the first conductive type region and the second conductive type region exposed through the insulating film.

Here, the second conductive type buried layer may be formed to be in contact with the substrate.

The first conductive buried layer may be located in a central region of the second conductive buried layer.

The isolation layer may include a first isolation layer formed from the surface of the second epitaxial layer to the inside of the first conductive type buried layer at the center of the second epitaxial layer; A second isolation layer spaced from the outside of the first isolation layer and extending from the surface of the second epitaxial layer to the inside of the second conductivity type buried layer; And a third isolation layer spaced from the outside of the second isolation layer and extending from the surface of the second epitaxial layer to the inside of the second conductivity type buried layer.

In addition, the second conductivity type region may be formed inside the first isolation layer, inward from the surface of the second epitaxial layer.

In addition, the first conductivity type region may be formed in the region between the second isolation layer and the third isolation layer, from the surface of the second epitaxial layer toward the inside.

Further, a bottom electrode may be further formed on the bottom surface of the substrate.

The transient voltage suppressor according to the present invention can realize the same maximum current value and capacitance value inside the device at the center and the outside by reducing the resistance deviation at the center and the outside thereof.

1 is a circuit diagram showing the operation principle of a general transient voltage suppressing element.
2 is a flowchart illustrating a method of manufacturing a transient voltage suppressing device according to an embodiment of the present invention.
3A to 3K are cross-sectional views sequentially illustrating a method of manufacturing a transient voltage suppressor according to an embodiment of the present invention.
4 illustrates a transient voltage suppressor according to an embodiment of the present invention and a corresponding equivalent circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

Hereinafter, a method of manufacturing a transient voltage suppressing device according to an embodiment of the present invention will be described.

2 is a flowchart illustrating a method of manufacturing a transient voltage suppressing device according to an embodiment of the present invention. 3A to 3K are cross-sectional views sequentially illustrating a method of manufacturing a transient voltage suppressor according to an embodiment of the present invention. 4 illustrates a transient voltage suppressor according to an embodiment of the present invention and a corresponding equivalent circuit.

Referring to FIG. 2, a method of fabricating a transient voltage suppressor according to an embodiment of the present invention includes forming a substrate (S10), forming a first epitaxial layer (S20), forming a second conductive buried layer (S30) A second epitaxial layer forming step S50, an isolation layer forming step S60, a first and a second conductivity type region forming step S70, an insulating film forming step S80, a first conductive type buried layer forming step S40, And an electrode forming step (S90).

Referring to FIG. 2 and FIG. 3A, a substrate preparation step S10 is performed to prepare a substantially plate-shaped first conductive semiconductor substrate 110. Although not shown, the substrate 110 may have a substantially circular shape when viewed from above. That is, the substrate 110 is provided to have a disk-like shape.

 The substrate 110 of the first conductivity type may be an N ++ semiconductor substrate formed by implanting N type impurities such as arsenic (As), phosphorus (P), or antimony (Sb), which are pentavalent elements, at a high concentration . Here, the high concentration means that the concentration is relatively higher than the impurity concentration of the epitaxial layer 130 to be described later. The substrate 110 of the first conductivity type may be a P ++ type in which impurity such as gallium (Ga), indium (In), or boron (B), which is a trivalent element, is contained at high concentration in the intrinsic semiconductor. However, for convenience of explanation, it is assumed that the substrate 110 is N-type in the present invention.

Referring to FIGS. 2 and 3B, a first epitaxial layer forming step S20 is performed in which a first epitaxial layer 120 is formed on an upper surface of the substrate 110. FIG. A gas containing SiH4 or the like and a group III element such as gallium (Ga), indium (In), or boron (B) is deposited on the substrate 110 at a high temperature of 600 to 2,000 DEG C at a low concentration Type first epitaxial layer 130 can be deposited on the surface of the substrate 110 by flowing the P-type first epitaxial layer 130 together.

Referring to FIGS. 2 and 3C, a second conductive buried layer forming step S30 is performed to form a second conductive buried layer 130 on the first epitaxial layer 120. Referring to FIG. Here, the second conductive buried layer 130 is formed to have a certain depth from the top surface of the first epitaxial layer 120 toward the inside. In particular, the second conductive buried layer 130 may be formed to have a depth in contact with the substrate 110. The second conductive buried layer 130 may be of the P ++ type doped with an impurity such as gallium (Ga), indium (In) or boron (B), which is a group III element, on the first epitaxial layer 120 . The second conductive type buried layer 130 may be formed by first forming an insulating layer (not shown) such as a silicon oxide layer or a nitrogen oxide layer on the upper surface of the first epitaxial layer 120 to form a second conductive buried layer 130 And then implanting impurities using an ion implantation or a thermal diffusion process.

Referring to FIGS. 2 and 3, a first conductive buried layer forming step S40 is performed to form a first conductive buried layer 140 on the second conductive buried layer 130. Referring to FIG. Here, the first conductive buried layer 140 is formed to have a certain depth from the upper surface of the second conductive buried layer 130 toward the inside. In addition, the first conductive buried layer 140 may be formed in a central region of the second conductive buried layer 130. The first conductive buried layer 140 may be an N ++ type doped with an impurity such as arsenic (As), phosphorus (P), or antimony (Sb), which is a Group 5 element, on the second conductive buried layer 130 . The first conductive buried layer 140 may be formed by first forming an insulating film (not shown) such as a silicon oxide film or a nitrogen oxide film on the upper surface of the substrate 110 in a region other than the buried layer, Can be formed by implanting impurities using a thermal diffusion process.

Referring to FIG. 2 and FIG. 3E, a second epitaxial layer forming step S50 is performed to form a second epitaxial layer 150 on the upper surface of the first epitaxial layer 120. For example, a gas containing SiH 4 or the like and a group III element such as gallium (Ga), indium (In), or boron (B) is formed on the upper surface of the first epitaxial layer 120 at a high temperature of 600 to 2000 ° C. Type second epitaxial layer 150 can be deposited on the surface of the first epitaxial layer 120 by flowing the P-type epitaxial layer 150 at a low concentration. At this time, the second epitaxial layer 150 is deposited on the surface of the first epitaxial layer 120, and the first and second conductive buried layers 140 and 130 are doped with the doping gases, The first and second conductive buried layers 141 and 131 diffused into the epitaxial layer 150 are formed.

Referring to FIGS. 2 and 3F, an isolation layer formation step S60 is performed to form an isolation layer 160 from the surface of the second epitaxial layer 150 toward the substrate 110. FIG. The isolation layer 160 includes a first isolation layer 161, a second isolation layer 162, a third isolation layer 163, and a fourth isolation layer 164 from the center to the outside. In the cross-sectional view of FIG. 3F, the isolation layers 160 are spaced apart from each other and a pair of the isolation layers 160 are formed on both sides of the isolation layer 160. However, the isolation layer 160 is formed in an annular ring shape.

The isolation layer 160 is patterned by exposing the mask (not shown), for example, which primarily determines the position of the isolation layer 160. Then, trenches can be formed through dry etching using mask openings by reactive ion etching. Thereafter, the isolation layer 160 may be formed by implanting an insulating material such as a silicon oxide film or a nitrogen oxide film into the trenches. However, the method of forming the isolation layer 160 by this method is not limited.

The first isolation layer 161 is located at the most central position, and has a circular ring shape with an empty center. The first isolation layer 161 is formed from the surface of the second epitaxial layer 150 to the inside of the first conductive type buried layer 141. A second conductive type region 172 is formed on the inner side of the first isolation layer 161. The first isolation layer 161 includes a second conductive type region 172 and a second epitaxial layer 150 under the second conductive type region 172 and an epitaxial layer 150 outside the second conductive type region 172. [ Physically and electrically separates the textured layer 150.

The second isolation layer 162 has an annular ring shape at the center and is formed outside the first isolation layer 161. The second isolation layer 162 is formed from the surface of the second epitaxial layer 150 to the inside of the second conductive type buried layer 131.

The third isolation layer 163 has an annular ring shape at the center and is formed outside the second isolation layer 162. The third isolation layer 163 is formed from the surface of the second epitaxial layer 150 to the inside of the second conductive type buried layer 131.

The second isolation layer 162 and the third isolation layer 163 correspond to the inner and outer peripheries of the first conductivity type region 171 to be formed later. That is, the first conductivity type region 171 is formed in the region between the second and third isolation layers 162 and 163. The second and third isolation layers 162 and 163 are formed on the first conductive type region 171 and the second epitaxial layer 150 below the first and second conductive type regions 171 and 171, And the second epitaxial layer 150 positioned thereon.

The fourth isolation layer 164 has an annular ring shape at the center and is formed outside the third isolation layer 163. The fourth isolation layer 164 is formed from the surface of the second epitaxial layer 150 to the inside of the substrate 111.

2 and 3G and 3H, first and second conductive regions 171 and 172 are formed inside the isolation layer 160 from the surface of the second epitaxial layer 150 toward the inside thereof The first and second conductivity type region formation steps (S70) are performed.

The first conductivity type region 171 is formed at a high concentration so as to have a certain depth from the surface of the second epitaxial layer 150 to the inside of the second and third isolation layers 162 and 163 . Of course, the high concentration means that the concentration is relatively large compared to the impurity concentration of the epitaxial layers 130 and 150. The first conductive type region 171 may be an N ++ type doped with an impurity such as arsenic (As), phosphorus (P), or antimony (Sb), which is a Group 5 element, on the second epitaxial layer 150 . The first conductive type region 171 may be formed by forming an insulating film (not shown) such as a silicon oxide film or a nitrogen oxide film in a region other than a region in which a conductive type region is to be formed and then using an ion implantation or a thermal diffusion process And may be formed by implanting impurities.

The inner and outer peripheries of the first conductivity type region 171 are surrounded by the second isolation layer 162 and the third isolation layer 163, respectively. Therefore, the first conductive type region 171 is separated from the second epitaxial layer 150 inside and outside the first conductive type region 171 by the second and third isolation layers 162 and 163 do.

Thereafter, the second conductive type region 172 is formed to have a certain depth from the surface of the second epitaxial layer 150 to the inside of the first isolation layer 161. The second conductive type region 172 may be a P + type in which an impurity such as gallium (Ga), indium (In), or boron (B), which is a Group III element, is implanted into the upper portion of the second epitaxial layer 150 . The second conductive type region 172 may be formed by forming an insulating film (not shown) such as a silicon oxide film or a nitrogen oxide film in a region other than a region where a conductive type region is to be formed and then using an ion implantation or a thermal diffusion process And may be formed by implanting impurities.

The outer periphery of the second conductive type region 172 is surrounded by the first isolation layer 161. The second conductive type region 172 may include a second epitaxial layer 150 and a first conductive type region 171 formed outside the second conductive type region 172 by the first isolation layer 161, Respectively.

2 and 3I, a portion of the first and second conductivity type regions 171 and 172 is exposed in regions corresponding to the peripheries of the first conductivity type region 171 and the second conductivity type region 172, (S80) for forming the insulating film 180 is performed. More specifically, the insulating layer 180 is formed on the surfaces of the isolation layer 160 and the second epitaxial layer 150, around the first and second conductive regions 171 and 172. The insulating layer 180 may be formed of any one selected from the group consisting of a silicon oxide layer, a nitrogen oxide layer, undoped polysilicon, Phospho-Silicate-Glass (PSG), borophosphoric-silicate-glass (BPSG) However, the present invention is not limited thereto.

An electrode 191 is formed on the surfaces of the first conductivity type region 171 and the second conductivity type region 172 and the bottom surface of the substrate 191 is formed on the bottom surface of the substrate 110. [ An electrode forming step S90 for forming the electrode 192 is performed.

First, an electrode 191 is formed on the surfaces of the first conductive type region 171 and the second conductive type region 172 exposed through the insulating layer 180. The electrode 191 electrically connects the first and second conductive regions 171 and 172. The electrode 191 may be formed by sequentially sputtering or sequentially plating a selected one of molybdenum (Mo), aluminum (Al), nickel (Ni), gold (Au) It does not.

Thereafter, a bottom electrode 192 is formed on the bottom surface of the substrate 110. The bottom electrode 192 may be electrically connected to the substrate 110. The bottom electrode 192 may be formed by sequentially sputtering or sequentially plating a selected one of molybdenum (Mo), aluminum (Al), nickel (Ni), gold (Au), and the like, But is not limited to.

As described above, the transient voltage suppressing element according to the embodiment of the present invention is completed. The transient voltage suppressing element according to the completed embodiment of the present invention forms an equivalent circuit as shown in FIG.

At this time, the P-type and N-type junctions inside the transient voltage suppressing element in the equivalent circuit have diode characteristics and capacitor characteristics. That is, although the junction of P-type and N-type is shown as a diode in FIG. 4, it may be drawn by a capacitor. Here, the electrode 180 and the bottom electrode 190 may serve as input / output terminals of the transient voltage suppressing element.

4, the transient voltage suppressor according to an embodiment of the present invention includes, in one element, a junction surface between a substrate 110 and a second conductive buried layer 131, a second conductive type The junction surface between the buried layer 131 and the first conductive buried layer 141, the junction surface between the first conductive buried layer 141 and the second epitaxial layer 150, the junction surface between the first conductive type buried layer 141 and the first conductive type buried layer 141, 2 epitaxial layer 150 are formed on the junction surfaces between the P-type and N-type epitaxial layers 150. [ In particular, since the P-type and N-type junctions are connected in series in the central region and the spaced apart region of the transient voltage suppressing element, the transient voltage suppressing element operates in both directions and can realize a low capacitance transient voltage suppressing element.

Further, in the transient voltage suppressor according to the present invention, the N type first conductivity type region 171 is formed in the P type second epitaxial layer 150. Therefore, the P-type and N-type junction surfaces formed between the first conductive type region 171 and the second epitaxial layer 150 are located at a close distance from the electrode 191, and the resistance is minimized. That is, as the resistance decreases, the value of the maximum current Ipp may increase. As a result, it is possible to implement a transient voltage suppressing device having a low capacitance. In addition, the transient voltage suppressor according to the present invention can reduce the resistance variation according to the distance of the PN junctions at the center and the outside thereof. That is, by reducing the resistance variation, the same maximum rated current is realized at the center and the outside.

In addition, since the transient voltage suppressor according to the present invention includes only two epitaxial layers 130 and 150, the process can be further simplified, and therefore, productivity and cost reduction can be achieved.

It is to be understood that the present invention is not limited to the above-described embodiment, and that various modifications and changes may be made by those skilled in the art without departing from the spirit and scope of the present invention. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

110; Substrate 120; The first epitaxial layer
130, 131; A second conductive buried layer 140, 141; The first conductive type buried layer
150; A second epitaxial layer 160; Isolation layer
171; A first conductive type region 172; The second conductivity type region
180; An insulating film 191; electrode
192; Bottom electrode

Claims (14)

A substrate of a first conductivity type;
A first epitaxial layer of a second conductivity type formed on top of the substrate;
A second conductive buried layer formed on the first epitaxial layer;
A first conductive buried layer formed on the second conductive buried layer;
A second epitaxial layer of a second conductivity type formed on the first epitaxial layer, the second conductive buried layer, and the first conductive buried layer;
A first conductive type region and a second conductive type region formed so as to be spaced apart from each other in a direction from the surface of the second epitaxial layer toward the inside;
A plurality of isolation layers formed from the surface of the second epitaxial layer toward the substrate in regions corresponding to the peripheries of the first conductivity type region and the second conductivity type region;
An insulating film formed on a surface of the isolation layer and the second epitaxial layer in a region corresponding to a periphery of the first conductive type region and the second conductive type region; And
And an electrode formed on a surface of the first conductive type region and the second conductive type region exposed through the insulating film. The method according to claim 1,
Wherein the second conductive buried layer is in contact with the substrate. The method according to claim 1,
Wherein the first conductive type buried layer is located in a central region of the second conductive type buried layer. The method according to claim 1,
The isolation layer
A first isolation layer formed from the surface of the second epitaxial layer to the interior of the first conductive buried layer at the center of the second epitaxial layer;
A second isolation layer spaced from the outside of the first isolation layer and extending from the surface of the second epitaxial layer to the inside of the second conductivity type buried layer; And
And a third isolation layer spaced from the outside of the second isolation layer and extending from the surface of the second epitaxial layer to the inside of the second conductivity type buried layer. 5. The method of claim 4,
Wherein the second conductive type region is formed inward from the surface of the second epitaxial layer inside the first isolation layer. 5. The method of claim 4,
Wherein the first conductivity type region is formed in a region between the second isolation layer and the third isolation layer, inwardly from the surface of the second epitaxial layer. The method according to claim 1,
And a bottom electrode is further formed on a bottom surface of the substrate. A substrate preparation step of preparing a substrate of a first conductivity type;
A first epitaxial layer forming step of forming a first epitaxial layer of a second conductivity type on the substrate;
Forming a second conductive buried layer on the first epitaxial layer;
A first conductive buried layer forming step of forming a first conductive buried layer on the second conductive buried layer;
A second epitaxial layer forming step of forming a second epitaxial layer of a second conductivity type on the first epitaxial layer, the second conductive buried layer, and the first conductive buried layer;
Forming a plurality of spaced apart isolation layers from the surface of the second epitaxial layer toward the substrate;
A first and a second conductivity type region forming step of forming a first conductivity type region and a second conductivity type region inward from the surface of the second epitaxial layer inwardly of the respective isolation layers;
Forming an insulating layer on the first conductive type region and the second conductive type region to expose a portion of the first conductive type region and the second conductive type region in a region corresponding to the periphery of the first conductive type region and the second conductive type region; And
And forming an electrode on the surfaces of the first conductive type region and the second conductive type region exposed through the insulating film. 9. The method of claim 8,
Wherein the second conductive buried layer is formed to be in contact with the substrate. 9. The method of claim 8,
Wherein the first conductive type buried layer is located in a central region of the second conductive type buried layer. 9. The method of claim 8,
The isolation layer
A first isolation layer formed from the surface of the second epitaxial layer to the interior of the first conductive buried layer at the center of the second epitaxial layer;
A second isolation layer spaced from the outside of the first isolation layer and extending from the surface of the second epitaxial layer to the inside of the second conductivity type buried layer; And
And a third isolation layer spaced from the outside of the second isolation layer and extending from the surface of the second epitaxial layer to the inside of the second conductivity type buried layer. 12. The method of claim 11,
Wherein the second conductivity type region is formed inside the first isolation layer from the surface of the second epitaxial layer toward the inside thereof. 12. The method of claim 11,
Wherein the first conductivity type region is formed in the region between the second isolation layer and the third isolation layer from the surface of the second epitaxial layer toward the inside thereof. 9. The method of claim 8,
Wherein a bottom electrode is further formed on a bottom surface of the substrate.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101850851B1 (en) 2017-01-23 2018-04-23 주식회사 케이이씨 Transient voltage suppressor and manufacturing method thereof
KR20180086784A (en) * 2017-01-23 2018-08-01 주식회사 케이이씨 Transient voltage suppressor and manufacturing method thereof
CN110021671A (en) * 2017-12-29 2019-07-16 新唐科技股份有限公司 Semiconductor device and its manufacturing method
CN112054050A (en) * 2019-06-06 2020-12-08 无锡华润华晶微电子有限公司 Transient voltage suppression diode structure and manufacturing method thereof

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KR101850851B1 (en) 2017-01-23 2018-04-23 주식회사 케이이씨 Transient voltage suppressor and manufacturing method thereof
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