CN112002767B - Zener diode and method of manufacturing the same - Google Patents
Zener diode and method of manufacturing the same Download PDFInfo
- Publication number
- CN112002767B CN112002767B CN202010804986.3A CN202010804986A CN112002767B CN 112002767 B CN112002767 B CN 112002767B CN 202010804986 A CN202010804986 A CN 202010804986A CN 112002767 B CN112002767 B CN 112002767B
- Authority
- CN
- China
- Prior art keywords
- doped region
- region
- doping
- zener diode
- junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims description 37
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 230000015556 catabolic process Effects 0.000 abstract description 25
- 230000002708 enhancing effect Effects 0.000 abstract description 3
- 230000008569 process Effects 0.000 description 27
- 229910052710 silicon Inorganic materials 0.000 description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 22
- 239000010703 silicon Substances 0.000 description 22
- 229920002120 photoresistant polymer Polymers 0.000 description 20
- 239000004065 semiconductor Substances 0.000 description 12
- 238000005468 ion implantation Methods 0.000 description 10
- 230000001965 increasing effect Effects 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000000087 stabilizing effect Effects 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910021478 group 5 element Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000009827 uniform distribution Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- -1 HfSiN Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66098—Breakdown diodes
- H01L29/66106—Zener diodes
Abstract
The invention discloses a Zener diode and a manufacturing method thereof, wherein the Zener diode comprises: a substrate; a well region of a first doping type formed in the substrate; a first doped region of a second doping type formed in the well region, the first doping type being opposite to the second doping type; and a second doped region formed below the first doped region, wherein a first part of the lower surface of the first doped region is adjacent to the well region to form a first PN junction, a second part of the lower surface of the first doped region is adjacent to the second doped region to form a second PN junction, and the second doped region adopts a hard mask to define a transversely extending boundary, so that the boundary of the second doped region forms a plane and the included angle between the plane and the vertical direction is smaller than or equal to a first angle. The invention can realize the uniform doping of the second doped region, thereby enhancing the stability of the breakdown voltage of the Zener diode and reducing the reverse electric leakage before breakdown.
Description
Technical Field
The invention relates to the technical field of semiconductor processes, in particular to a Zener diode and a manufacturing method thereof.
Background
Silicon free of impurities is referred to as intrinsic silicon. The intrinsic silicon is artificially doped with a specific impurity to form N-type silicon or P-type silicon exhibiting conductive characteristics. N-type silicon is formed by doping intrinsic silicon with group V elements (e.g., phosphorus, arsenic, antimony), and P-type silicon is formed by doping intrinsic silicon with group III elements (e.g., boron).
When P-type silicon and N-type silicon are pressed together by alloying or planar diffusion, an extremely thin special region called a PN junction is formed near the interface between the two. And respectively leading out a metal lead called as a positive electrode and a metal lead called as a negative electrode from the PN junction in the P region and the N region to form a diode.
The positive pole and the negative pole of the diode are respectively connected with external voltage, when the voltage of the positive pole is higher than that of the negative pole, the diode is called as diode forward bias, and otherwise, the diode is called as diode reverse bias. A forward biased diode will produce a forward current that increases with increasing forward voltage, and a reverse biased diode will produce only a very small reverse saturation current. Only when the reverse bias voltage (the difference between the external voltages of the cathode and the anode) of the diode increases to a certain value, the reverse current thereof increases rapidly, this phenomenon is called reverse breakdown of the diode, and the voltage at which the reverse breakdown occurs is called reverse breakdown voltage.
Zener diodes (zeners) are commonly used as voltage regulators and are also a type of crystal diodes. It operates by utilizing the characteristic that the breakdown region of the PN junction has a stable voltage. Voltage regulators find wide application in voltage regulation devices and some electronic circuits. This type of diode is referred to as a zener to distinguish diodes used in rectification, detection and other unidirectional conduction applications. The characteristic of the zener diode is that after breakdown, the voltage across it remains substantially constant. Thus, when the voltage regulator is connected to the circuit, if the voltage of each point in the circuit fluctuates due to the fluctuation of the power voltage or other reasons, the voltage at two ends of the load will be basically kept unchanged. After the voltage-stabilizing tube is in reverse breakdown, although the current changes in a large range, the voltage change at the two ends of the voltage-stabilizing tube is very small. By utilizing the characteristic, the voltage stabilizing tube can play a role of voltage stabilization in the circuit. Because of this characteristic, the regulator tube is mainly used as a regulator or a voltage reference element. The voltage stabilizing diodes can be connected in series to be used at higher voltage, and more stable voltage can be obtained through the series connection.
The core of the Zener diode is a PN junction consisting of a P-region and an N + region, or a P + region and an N-region. In CMOS integrated circuits, such PN junctions are typically fabricated in N-wells or P-wells, which are the most basic structures of the CMOS integrated circuit itself.
In a CMOS integrated circuit, a cross-sectional structure of a conventional zener diode is shown in fig. 1, and fig. 1 shows a schematic diagram of a longitudinal cross-sectional structure of a zener diode according to the prior art, which mainly includes: the semiconductor device includes a substrate 1, a well (e.g., an N-type lightly doped well) 2 formed on the substrate 1, a first doped region 3 formed in the well of the substrate 1, a third doped region (e.g., an N + doped region) 4 located at two sides of the first doped region (e.g., a P + doped region) 3, and a second doped region (e.g., an N-doped region) 5 formed under the first doped region 4. When forming the second doped region 5, a photoresist 6 is mainly used to open a partial region of the upper surface of the first doped region 3, and ions (such as N-type ions) are implanted into the silicon substrate corresponding to the region through self-alignment of field oxygen. However, the photoresist 6 is shrunk in the baking process after exposure and development, so that a ladder-shaped structure with the size of the bottom of the photoresist larger than that of the top is formed, the depth of ion implantation at the edge of the second doped region 5 is correspondingly reduced, the distance between the impurity concentration peak and the P + junction is reduced, and the edge of the first doped region 3, the well region 2 and the second doped region 5 form an arc junction, so that the electric field at the AA region in fig. 1 is increased. The increased electric field causes a severe band-to-band tunneling effect, so that the reverse leakage of the PN junction of the zener diode is increased, and when the reverse voltage is increased, the electric field is increased continuously, which is easy to cause premature breakdown.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a zener diode and a method for manufacturing the same, which can achieve uniform doping of the second doped region, thereby enhancing the stability of breakdown voltage of the zener diode and reducing reverse leakage before breakdown.
According to the present invention, there is provided a zener diode comprising: a substrate; a well region of a first doping type formed in the substrate; a first doped region of a second doping type formed in the well region, the first doping type being opposite to the second doping type; and a second doped region formed below the first doped region, wherein a first part of the lower surface of the first doped region is adjacent to the well region to form a first PN junction, a second part of the lower surface of the first doped region is adjacent to the second doped region to form a second PN junction, and the second doped region adopts a hard mask to define a transversely extending boundary, so that the boundary of the second doped region forms a plane and the included angle between the plane and the vertical direction is smaller than or equal to a first angle.
Preferably, the first angle is set to 10 degrees.
Preferably, the zener diode further comprises: a field oxide region, a boundary of the first doped region being defined by the field oxide region.
Preferably, the zener diode further comprises: a third doped region of the first doping type, a boundary of the third doped region being defined by the field oxygen region and being separated from the first doped region by the field oxygen region.
Preferably, the junction depth of the first doped region is smaller than the junction depth of the field oxide region, and the junction depth of the second doped region is larger than the junction depth of the field oxide region.
Preferably, the doping concentration of the first doping region is greater than the doping concentration of the second doping region.
Preferably, a central axis of the first doped region and a central axis of the second doped region are on the same vertical line.
Preferably, the zener diode further comprises: the first metal electrode is used for leading out the cathode of the Zener diode from the upper surface of the first doped region, and the second metal electrode is used for leading out the anode of the Zener diode from the upper surface of the third doped region.
The invention provides a manufacturing method of a Zener diode, which comprises the following steps: forming a substrate; forming a well region of a first doping type in the substrate; forming a first doped region of a second doping type located in the well region, the second doping type being opposite to the first doping type; and forming a second doped region located below the first doped region,
the first part of the lower surface of the first doping area is abutted with the well area to form a first PN junction, the second part of the lower surface of the first doping area is abutted with the second doping area to form a second PN junction, and the second doping area adopts a hard mask to limit a transversely extending boundary so that the boundary of the second doping area forms a plane and the included angle between the plane and the vertical direction is smaller than or equal to a first angle.
Preferably, the first angle is set to 10 degrees.
Preferably, the method further comprises: forming a field oxide region on the surface of the substrate, wherein the boundary of the first doping region is limited by the field oxide region; a third doped region of the first doping type formed within the well region, a boundary of the third doped region being defined by the field oxide region and being separated from the first doped region by the field oxide region.
Preferably, the junction depth of the first doped region is smaller than the junction depth of the field oxide region, and the junction depth of the second doped region is larger than the junction depth of the field oxide region.
The beneficial effects of the invention are: the invention discloses a Zener diode and a manufacturing method thereof, wherein a hard mask is formed on the surface of a silicon substrate, and forming a hard mask opening on the hard mask, which opens only a portion of the first doped region and has a flat edge side, such that, when the second doping region is formed by ion implantation, since a hard mask is used to define a steep lateral boundary, so that the junction area of the second PN junction can be accurately controlled, namely, when only photoresist is used for light injection, the photoresist shrinks to form a trapezoid structure due to the baking process so that part of ions penetrate through the inclined edge of the photoresist to cause the edge concentration of the second doped region to become shallow, thereby realizing the uniform doping of the second doping region, reducing the reverse leakage condition before the breakdown of the PN junction of the Zener diode, the stability of the breakdown voltage of the Zener diode is enhanced, so that the performance of the device is less influenced by process fluctuation.
The field oxide region is adopted to limit the boundary of the first doped region, so that the junction area of a first PN junction formed by the first doped region and the well region can be accurately controlled, the side wall of the first doped region is prevented from participating in a conductive path, the output noise voltage is small, the discreteness of stable voltage is small, and the stability is high.
And forming a heavily doped third doped region with the same doping type as the well region in the well region as a contact region, so that a planar device can be formed, and the contact resistance between the surface of the well region and an electrode can be reduced when the electrode is led out. Meanwhile, the third doped region is isolated from the first doped region through the field oxide region, so that the voltage withstand voltage can be improved.
The junction depth of the first doped region is smaller than that of the field oxide region, so that voltage withstand voltage can be improved, and the junction depth of the second doped region is larger than that of the field oxide region, so that junction resistance can be reduced.
The center of the first doped region and the center of the second doped region are arranged on the same vertical line, so that the uniform distribution of an electric field at a PN junction of the Zener diode is facilitated, and the voltage stabilizing capability of the Zener diode is enhanced.
And the metal electrodes are respectively led out from the surfaces of the first doped region and the third doped region together, so that the flat device package is favorably formed, and the miniaturization of the device is realized.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic view showing a longitudinal sectional structure of a zener diode according to the related art;
FIG. 2 illustrates a schematic diagram of a longitudinal cross-sectional structure of a Zener diode provided according to an embodiment of the present invention;
figures 3a to 3f show schematic cross-sectional views of stages in a method of manufacturing a zener diode according to an embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, like elements are identified with the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
When a layer, a region, or a region is referred to as being "on" or "over" another layer, another region, or a region may be directly on or over the other layer, the other region, or another layer or a region may be included between the layer and the other layer or the other region. And, if the device is turned over, one layer or region may be "under" or "beneath" another layer or region.
If for the purpose of describing the situation directly above another layer, another region, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In this application, "a is directly in B" means that a is in B and a and B are directly adjacent, rather than a being in a doped region formed in B.
Unless otherwise specified below, various layers or regions of a semiconductor device may be composed of materials well known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as GaAs, InP, GaN, SiC, and group IV semiconductors such as Si, Ge. The gate conductor, electrode layer may be formed of various materials that are electrically conductive, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other electrically conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni 3 Si, Pt, Ru, W, and combinations of the various conductive materials.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed. The term "laterally extending" refers to extending in a direction substantially perpendicular to the depth direction of the trench.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
As described above with reference to fig. 1, in the actual process, when the photoresist 6 is used for ion implantation, the photoresist 6 needs to be baked and shaped after exposure and development, and during baking, moisture in the photoresist 6 evaporates, which causes the photoresist to shrink, so that a ladder-shaped structure with a bottom dimension larger than a top dimension of the photoresist feature occurs. In this case, when the second doping region 5 is ion-implanted, a part of impurities may penetrate through the bevel edge of the photoresist 6, so that the second doping region 5 has a region with a shallow implantation depth, which is closer to the junction surface of the first doping region 3 at the peak of the doping concentration with reference to the AA region in fig. 1, or may easily cause a problem of large reverse leakage, even low breakdown voltage.
Therefore, the structure of the zener diode is improved again, and the zener diode structure as shown in fig. 2 is formed, and a stable and reliable planar PN junction of the zener diode is formed by forming a hard mask opening region through a hard mask and then utilizing a straight hard mask opening region in the manufacturing process without increasing the process cost. Fig. 2 shows a schematic diagram of a longitudinal cross-sectional structure of a zener diode according to an embodiment of the present invention.
As shown in fig. 2, in the present embodiment, the zener diode includes: the semiconductor device includes a substrate 11, a well 12 of a first doping type formed on the substrate 11, a first doping region 14 of a second doping type (the second doping type is opposite to the first doping type) formed in the well 12, and a second doping region 16 of the first doping type formed under the first doping region 14. Wherein, a first portion of the lower surface of the first doped region 14 is adjacent to the well region 12 to form a first PN junction, a second portion of the lower surface of the first doped region 14 is adjacent to the second doped region 16 to form a second PN junction, and the second doped region 16 employs the hard mask 18 to define a laterally extending boundary, so that the boundary of the second doped region 16 forms a plane and an included angle between the plane and the vertical direction is smaller than or equal to a first angle. For example, the first angle is set to 10 degrees.
With reference to fig. 2, it can be understood that, in the process of forming the second doped region 16, the upper surface of the first doped region 14 is partially covered by the hard mask 18, and the hard mask 18 is formed with a hard mask opening at a region where the first doped region 14 is not covered, and the second doped region 16 is formed on the substrate 11 corresponding to the hard mask opening. Wherein the lateral area of the first doped region 14 is larger than the lateral area of the second doped region 16, and the longitudinal junction depth of the first doped region 14 is smaller than the longitudinal junction depth of the second doped region 16.
Furthermore, the hard mask opening is formed by etching the hard mask, so that the side surface of the opening can form a steep structure. Therefore, the side of the second doped region 16 defined based on the hard mask may form a planar structure, and the included angle between the plane and the vertical direction may be as small as possible. That is, after ion implantation is performed based on the hard mask opening, each part of the formed second doped region 16 is uniformly doped, and arc junctions are not formed at the edge of the second doped region 16 due to the shrinkage deformation of the photoresist 17 in the baking process during the ion implantation of the second doped region 16, so that the reverse leakage condition before breakdown at the PN junction of the zener diode is reduced, and the breakdown voltage stability of the zener diode is enhanced.
The zener diode of this embodiment further includes: a field oxide region 13 formed on the surface of the substrate 11. Wherein the boundary of the first doped region 14 is defined by the field oxide region 13. Because the field oxide region 13 is adopted to limit the boundary of the first doping region 14, the junction area of the first PN junction formed by the first doping region 14 and the well region 13 can be accurately controlled, the side wall of the first doping region 14 is prevented from participating in a conductive path, the output noise voltage is reduced, the discreteness of the stable voltage is small, and the stability is high.
Further, the junction depth of the first doped region 14 is smaller than the junction depth of the field oxide region 13 (the distance between the lower surface of the field oxide region 13 and the surface of the substrate 11), so that the voltage withstanding voltage can be improved. And the junction depth of the second doped region 16 is greater than the junction depth of the field oxide region 13, which can reduce the junction resistance.
Further, the zener diode of this embodiment further includes: third doped regions 15 of the first doping type are located on both sides of the first doped region 14. referring to fig. 2, the boundaries of the third doped regions 15 are defined by the field oxide regions 13 and are separated from each other by the field oxide regions 13 and the first doped region 14. And forming a heavily doped third doped region with the same doping type as the well region in the well region as a contact region, so that a planar device can be formed, and the contact resistance between the surface of the well region and an electrode can be reduced when the electrode is led out. Meanwhile, the third doped region is isolated from the first doped region through the field oxide region, so that the voltage withstand voltage can be improved.
In this embodiment, the doping type of the first doped region 14 is opposite to the doping type of the second doped region 16, and the doping type of the third doped region 15 is the same as the doping type of the second doped region 16 and the doping type of the well region 12. Further, the doping concentration of the first doping region 14 is greater than the doping concentration of the second doping region 16. Optionally, in the first embodiment of the present invention, the first doped region 14 is a P + doped region, the third doped region 15 is an N + doped region, and the second doped region 16 is an N-doped region. In the second embodiment of the present invention, the first doped region 14 is an N + doped region, the third doped region 15 is a P + doped region, and the second doped region 16 is a P-doped region. In the drawings of the present invention, for the purpose of illustration of the first embodiment, the substrate 11 is exemplified by a P-type substrate, and the well region 12 is exemplified by an N-type well region, but it should be understood that the present invention is not limited thereto.
In the lateral cross-sectional structure of the zener diode according to the embodiment of the present invention, the cross-sectional shape of each doped region is preferably a ring structure, but may be other conventional structures.
It should be noted that "+" indicates that the relative doping concentration of the doped region is relatively large, and "-" indicates that the relative doping concentration of the doped region is relatively small. "N + and P-" indicate that the N-type doped region is a heavily doped region, the P-type doped region is a lightly doped region, and the doping concentration of the N-type doped region is greater than that of the P-type doped region. Wherein, N +, P + and N-are formed by doping through an ion implantation process, and the dosage and the energy/atomic weight of the ion implantation process respectively determine the doping concentration and the doping depth of each region.
In this embodiment, N-type silicon or N-type doped regions are formed by doping intrinsic silicon with a group V element (e.g., phosphorus, arsenic, antimony), and P-type silicon or P-type doped regions are formed by doping intrinsic silicon with a group III element (e.g., boron).
Further, in this embodiment, the zener diode further includes: a first metal electrode and a second metal electrode. Wherein, the cathode of the zener diode is led out from the upper surface of the first doped region 14 through the first metal electrode, and the anode of the zener diode is led out from the upper surface of the third doped region 15 through the second metal electrode. Since the doping concentration of the well region 12 (e.g., N-type well region) is very low, if the metal electrode is directly led out from the surface of the well region 12, a large contact resistance is generated, in order to reduce the contact resistance between the surface of the well region 12 and the metal electrode, a heavily doped region such as an annular third doped region 15 (e.g., N + doped region) with the same doping type as that of the well region 12 is fabricated at the position of the surface of the well region 12 where the electrode is prepared to be led out, and the contact resistance between the third doped region 15 and the metal electrode is very low due to the relatively high doping concentration.
In order to make the zener diode have better function, in the embodiment, the central axis of the first doped region 14 and the central axis of the second doped region 16 are on the same vertical line, taking fig. 2 as an example, in the longitudinal cross-sectional view, the first doped region 14 and the second doped region 16 are symmetrical left and right along the same vertical line.
The zener diode of this structure is formed by the first doped region 14 (e.g., P + doped region) and the second doped region 16 (e.g., N-doped region) only interfacing within the silicon body, i.e., the second PN junction formed by the second doped region 16 and the first doped region 14 is located entirely within the silicon (substrate) body. A first PN junction comprised of the first doped region 14 and the well region 12 (e.g., an N-type well region) is connected in parallel with a "second PN junction in the silicon body comprised of the first doped region 14 and the second doped region 16". In an actual process, current can pass through the first PN junction and/or the second PN junction during reverse breakdown operation, the output noise voltage is small, the discreteness of stable voltage is small, the stability is high, and meanwhile, the double PN junctions are adopted for conducting current circulation, so that the working performance of the Zener diode is enhanced. Meanwhile, due to the isolation of the field oxide region 13, when current passes through the first PN junction, the current path is under the field oxide region 13, and is less affected by the doping concentration of the substrate surface, and the output noise voltage is low.
When the second doped region 16 is formed, the zener diode according to the present invention performs ion implantation based on the photoresist 17 and the double-blocking structure of the hard mask 18 (having a steep hard mask opening) located on the lower surface of the photoresist 17, so that uniform doping of the second doped region 16 can be achieved, a reverse leakage condition before breakdown at the PN junction can be reduced, and stability of breakdown voltage of the zener diode can be better enhanced.
The zener diode shown in fig. 2 is fabricated through the process steps of fig. 3a to 3f to further improve the voltage stabilizing capability of the breakdown voltage of the zener diode, and the following description of the fabrication method is provided.
Fig. 3a to 3f are schematic cross-sectional views illustrating various stages of a method for fabricating a zener diode according to an embodiment of the present invention, and a process flow of fabricating a transistor structure according to an embodiment of the present invention is described below with reference to fig. 3a to 3 f.
As shown in fig. 3a, a substrate 11 and a well region 12 of a first doping type located on top of the substrate 11 are first formed. A small amount of ions are implanted into the semiconductor substrate 11, and the well is pushed down at a high temperature to form a lightly doped N-type or P-type region, i.e., a well region 12. This step is accomplished using conventional techniques. The substrate 11 is, for example, a silicon substrate.
Further, as shown in fig. 3b, a field oxide region 13 is formed on the surface of the substrate 11. And performing field oxygen isolation on the surface of the substrate 11, namely forming a plurality of mutually isolated field oxygen regions 13. The field oxide region 13 is formed by conventional processes, and the specific processes are not limited in detail. After the step of producing the field oxide is completed, a structure is formed as shown in fig. 3b, wherein the lateral cross-sectional structure of the field oxide region 13 may be a ring structure.
Next, as shown in fig. 3c, a first doped region 14 of the second doping type and a third doped region 15 of the first doping type are formed in the well region 12. The first doping type is opposite to the second doping type, but the doping concentrations of the first doping region 14 and the third doping region 15 are both heavily doped. Illustratively, if the first doped region 14 is a P-type doped region and the third doped region 15 is an N-type doped region, P + implantation is performed in the well region 12 to form the first doped region 14, and N + implantation is performed in the well region 12 to form the third doped region 15. Preferably, the lateral cross-sectional structures of the first doped region 14 and the third doped region 15 are both ring-shaped, and the first doped region 14 and the third doped region 15 are isolated by the field oxide region 13.
Further, the boundary of the first doped region 14 and the boundary of the third doped region 15 are both defined by the field oxide region 13.
Next, as shown in fig. 3d, a hard mask 18 is formed on the upper surface of the substrate 11 and covers the field oxide region 14, the third doped region 15 and the first doped region 14. The hard mask 18 is formed using conventional processes, such as depositing an oxide material on the top surface of the substrate 11 using a Chemical Vapor Deposition (CVD) process to form an oxide layer, or depositing other barrier materials that can block ion penetration. The upper surface of the hard mask 18 should be higher than the upper surface of the field oxide region 13, and the specific thickness may be determined according to actual situations.
Thereafter, as shown in fig. 3e, a hard mask opening is formed by etching to open a portion of the first doped region 14. The hard mask opening is formed using conventional processes, such as providing a photoresist of a predetermined shape on the upper surface of the hard mask 18, and etching on the hard mask 18 corresponding to a portion of the first doped region 14 by photolithography or chemical etching to open a portion of the first doped region 14. Preferably, the hard mask opening is formed as a straight opening.
Finally, as shown in fig. 3f, a second doped region 16 is formed below the first doped region 14. This step is accomplished using conventional processes such as ion implantation using a self-aligned process. Wherein, the lateral area of the first doping region 14 is larger than the lateral area of the second doping region 16, and the longitudinal junction depth of the first doping region 14 is smaller than the longitudinal junction depth of the second doping region 16. A first portion of the lower surface of the first doped region 14 is adjacent to the well region 13 to form a first PN junction, and a second portion of the lower surface of the first doped region 14 is adjacent to the second doped region 16 to form a second PN junction.
Further, the junction depth of the first doped region 14 is smaller than that of the field oxide region 13 to improve the voltage withstanding voltage. And the junction depth of the second doped region 16 is greater than the junction depth of the field oxide region 13 to reduce the junction resistance.
Further, the doping concentration of the first doping region 14 is greater than the doping concentration of the second doping region 16, and the doping type of the first doping region 14 is opposite to the doping type of the second doping region 16. For example, in the first embodiment of the present invention, the first doped region 14 is a P + doped region, the third doped region 15 is an N + doped region, and the second doped region 16 is an N-doped region. In the second embodiment of the present invention, the first doped region 14 is an N + doped region, the third doped region 15 is a P + doped region, and the second doped region 16 is a P-doped region.
Preferably, the central axis of the first doped region 14 and the central axis of the second doped region 16 are formed on the same vertical line. Therefore, the uniform distribution of the electric field at the PN junction of the Zener diode is facilitated, and the voltage stabilizing capability of the Zener diode is further enhanced.
The zener diode manufactured based on the above method can make the second doped region 16 smaller than the lateral area of the first doped region 14, which helps to eliminate the arc junction at the edge of the first doped region 14. On the other hand, the hard mask is used to define the boundary of the laterally extended second doped region 16, so that the boundary of the second doped region 16 forms a plane, and an included angle between the plane and the vertical direction is smaller than or equal to a first angle (for example, 10 degrees), thereby avoiding the problem that the impurity concentration at the edge of the second doped region 16 becomes shallow due to the fact that the photoresist 17 shrinks to form a trapezoid with a large lower part and a small upper part in the baking process, so that the doping concentration of the second doped region 16 is uniform, the reverse leakage before the breakdown of the zener diode is reduced, and the stability of breakdown voltage of the zener diode is enhanced. The boundary of the second doped region 16 forms a plane, and the smaller the included angle between the plane and the vertical direction is, the smaller the reverse leakage before the zener diode breaks down is, and the stronger the stability of the breakdown voltage of the zener diode is.
It is obvious that the zener diode comprises other steps in the manufacturing process, but they are not described here because they are not relevant to the present invention and the process is well known.
It should be noted that, the field oxide region in the embodiment of the present invention is formed by using a local silicon oxide isolation (Locos) process, but the present invention is also applicable to an STI (shallow trench isolation) process.
In summary, the hard mask is formed on the surface of the silicon substrate, and the hard mask opening which only opens part of the first doped region and has a smooth edge side is formed on the hard mask, so that when ion implantation is performed to form the second doped region, the edge side of the formed second doped region is also smooth due to the blocking effect of the hard mask, that is, the situation that when only photoresist is used for light implantation, the photoresist shrinks to form a trapezoidal structure due to the baking process, and then part of ions punch through the bevel edge of the photoresist to cause the edge concentration of the second doped region to become shallow can be avoided, thereby realizing uniform doping of the second doped region, reducing the reverse leakage condition before breakdown at the PN junction of the zener diode, and enhancing the stability of breakdown voltage of the zener diode.
It should be noted that, in this document, the contained terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.
Claims (10)
1. A zener diode, comprising:
a substrate;
a well region of a first doping type formed in the substrate;
a first doped region of a second doping type formed in the well region, the first doping type being opposite to the second doping type;
a second doped region formed below the first doped region;
a field oxide region, a boundary of the first doped region being defined by the field oxide region,
the first part of the lower surface of the first doping area is adjacent to the well area to form a first PN junction, the second part of the lower surface of the first doping area is adjacent to the second doping area to form a second PN junction, and the second doping area adopts a hard mask to limit a transversely extending boundary, so that the boundary of the second doping area forms a plane, and an included angle between the plane and the vertical direction is smaller than or equal to a first angle.
2. The zener diode of claim 1, wherein the first angle is set to 10 degrees.
3. The zener diode of claim 2, further comprising:
a third doped region of the first doping type, a boundary of the third doped region being defined by the field oxygen region and being separated from the first doped region by the field oxygen region.
4. The zener diode of claim 3 wherein the junction depth of the first doped region is less than the junction depth of the field oxide region and the junction depth of the second doped region is greater than the junction depth of the field oxide region; and
the doping concentration of the first doping area is greater than that of the second doping area.
5. The zener diode of claim 1, wherein a central axis of the first doped region is on a same vertical line as a central axis of the second doped region.
6. The zener diode of claim 3, further comprising: a first metal electrode and a second metal electrode,
the first metal electrode is used for leading out a cathode of the Zener diode from the upper surface of the first doping area,
the second metal electrode is used for leading out an anode of the Zener diode from the upper surface of the third doped region.
7. A method of fabricating a zener diode, comprising:
forming a substrate;
forming a well region of a first doping type in the substrate;
forming a first doped region of a second doping type located in the well region, the second doping type being opposite to the first doping type;
forming a second doped region located below the first doped region;
forming a field oxide region on the surface of the substrate, the boundary of the first doped region being defined by the field oxide region,
the first part of the lower surface of the first doping area is adjacent to the well area to form a first PN junction, the second part of the lower surface of the first doping area is adjacent to the second doping area to form a second PN junction, and the second doping area adopts a hard mask to limit a transversely extending boundary, so that the boundary of the second doping area forms a plane, and an included angle between the plane and the vertical direction is smaller than or equal to a first angle.
8. The method of manufacturing a zener diode according to claim 7, wherein the first angle is set to 10 degrees.
9. The method of manufacturing a zener diode of claim 7, further comprising:
a third doped region of the first doping type formed within the well region, a boundary of the third doped region being defined by the field oxygen region and being separated from the first doped region by the field oxygen region.
10. The method of claim 9, wherein the junction depth of the first doped region is less than the junction depth of the field oxide region, and the junction depth of the second doped region is greater than the junction depth of the field oxide region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010804986.3A CN112002767B (en) | 2020-08-12 | 2020-08-12 | Zener diode and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010804986.3A CN112002767B (en) | 2020-08-12 | 2020-08-12 | Zener diode and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112002767A CN112002767A (en) | 2020-11-27 |
| CN112002767B true CN112002767B (en) | 2022-08-23 |
Family
ID=73463543
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010804986.3A Active CN112002767B (en) | 2020-08-12 | 2020-08-12 | Zener diode and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112002767B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115548129A (en) * | 2021-06-30 | 2022-12-30 | 无锡华润上华科技有限公司 | Zener diode and manufacturing method thereof |
| CN113380787B (en) * | 2021-08-13 | 2022-02-25 | 上海维安半导体有限公司 | Bidirectional transient voltage suppression device and preparation method thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3472476B2 (en) * | 1998-04-17 | 2003-12-02 | 松下電器産業株式会社 | Semiconductor device and driving method thereof |
| DE10122364B4 (en) * | 2001-05-09 | 2006-10-19 | Infineon Technologies Ag | Compensation component, circuit arrangement and method |
| CN102280495B (en) * | 2010-06-10 | 2014-04-09 | 北大方正集团有限公司 | Zener diode and manufacturing method thereof |
| US9768160B2 (en) * | 2013-08-09 | 2017-09-19 | Infineon Technologies Austria Ag | Semiconductor device, electronic circuit and method for switching high voltages |
| TWI613708B (en) * | 2015-04-28 | 2018-02-01 | 新唐科技股份有限公司 | Semiconductor device and method of fabricating the same |
-
2020
- 2020-08-12 CN CN202010804986.3A patent/CN112002767B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN112002767A (en) | 2020-11-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20080135970A1 (en) | High Voltage Shottky Diodes | |
| US20110227187A1 (en) | Schottky barrier semiconductor device | |
| US20060237813A1 (en) | Junction barrier schottky with low forward drop and improved reverse block voltage | |
| KR101444081B1 (en) | Vertical trench igbt and method for manufacturing the same | |
| US20200020798A1 (en) | Power mosfet with an integrated pseudo-schottky diode in source contact trench | |
| US10923563B2 (en) | Power device | |
| US8350289B2 (en) | Semiconductor device | |
| US10847660B2 (en) | Trench semiconductor device having multiple active trench depths and method | |
| CN111710729B (en) | Zener diode and method of manufacturing the same | |
| CN112002767B (en) | Zener diode and method of manufacturing the same | |
| US11094779B2 (en) | Semiconductor device having an edge termination region comprising a first edge termination region of a second conductivity type adjacent to a second edge termination region of a first conductivity type | |
| US6459133B1 (en) | Enhanced flux semiconductor device with mesa and method of manufacturing same | |
| US4929563A (en) | Method of manufacturing semiconductor device with overvoltage self-protection | |
| CN111199970B (en) | Transistor structure for electrostatic protection and manufacturing method thereof | |
| US11652098B2 (en) | Transistor structure for electrostatic protection and method for manufacturing same | |
| CN111192871B (en) | Transistor structure for electrostatic protection and manufacturing method thereof | |
| US7019379B2 (en) | Semiconductor device comprising voltage regulator element | |
| US8237239B2 (en) | Schottky diode device and method for fabricating the same | |
| US7291899B2 (en) | Power semiconductor component | |
| CN111326589A (en) | Diode structure and preparation method thereof | |
| CN114122151B (en) | Semiconductor device and method for manufacturing the same | |
| EP4322208A1 (en) | Mesa device with stack thin film passivation | |
| CN111180421B (en) | Transistor structure for electrostatic protection and manufacturing method thereof | |
| CN116314270A (en) | Trench gate control diode and manufacturing method thereof | |
| US20120061803A1 (en) | Asymmetrical bidirectional protection component |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province, 310030 Applicant after: Jiehuate Microelectronics Co.,Ltd. Address before: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province, 310030 Applicant before: JOULWATT TECHNOLOGY Inc.,Ltd. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |