CN111326589A - Diode structure and preparation method thereof - Google Patents
Diode structure and preparation method thereof Download PDFInfo
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- CN111326589A CN111326589A CN201811542384.4A CN201811542384A CN111326589A CN 111326589 A CN111326589 A CN 111326589A CN 201811542384 A CN201811542384 A CN 201811542384A CN 111326589 A CN111326589 A CN 111326589A
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- 238000002360 preparation method Methods 0.000 title description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 122
- 229920005591 polysilicon Polymers 0.000 claims abstract description 110
- 239000000758 substrate Substances 0.000 claims abstract description 79
- 239000004065 semiconductor Substances 0.000 claims abstract description 54
- 239000002184 metal Substances 0.000 claims description 47
- 229910021332 silicide Inorganic materials 0.000 claims description 33
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 17
- 239000002019 doping agent Substances 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 156
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
Abstract
The present application relates to a diode structure and a method of manufacturing the same, the diode structure comprising a semiconductor substrate; a well region having a first conductivity type and formed in the semiconductor substrate; the grid region comprises a grid oxide layer formed on part of the well region and a polycrystalline silicon grid layer formed on the grid oxide layer, the polycrystalline silicon grid layer has a second conduction type, and the distance between the Fermi level of the polycrystalline silicon grid layer and the energy band of the forbidden band center of the semiconductor substrate is less than or equal to 0.3 eV; and an N-type region and a P-type region respectively formed in the well region at two sides of the gate region. By controlling the work function of the polysilicon gate layer, the Fermi level of the polysilicon gate layer is positioned near the center of a forbidden band of the semiconductor substrate, so that the work function difference between the polysilicon gate layer and a well region below the polysilicon gate layer is reduced, the contact potential between the polysilicon gate layer and the well region is reduced, and the problems of leakage current, unstable voltage resistance and the like can be solved.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a diode structure and a preparation method of the diode structure.
Background
The P-type region and the N-type region in the transverse diode structure are both formed on the top layer of the semiconductor substrate, wherein the P-type region and the N-type region form a PN junction. In order to enhance the withstand voltage of the PN junction, the N-type region and the P-type region are arranged at intervals, and an isolation structure is arranged between the N-type region and the P-type region to improve the withstand voltage of the PN junction. However, after the isolation structure is disposed between the N-type region and the P-type region, the leakage current of the diode structure is large, and the reverse breakdown voltage is unstable, which results in the instability of the diode structure. In special application occasions such as high temperature, high humidity and space radiation, the performance of the diode is rapidly degraded, the reliability is reduced, and finally the diode fails.
Disclosure of Invention
In view of the above, it is necessary to provide a new diode structure for addressing at least one of the above technical problems.
A diode structure, comprising:
a semiconductor substrate;
the well region is provided with a first conduction type and is formed in the semiconductor substrate;
a gate region including a gate oxide layer formed on a portion of the well region and a polysilicon gate layer formed on the gate oxide layer, the polysilicon gate layer having a second conductivity type, a fermi level of the polysilicon gate layer being less than or equal to 0.3eV from an energy band distance of a forbidden band center of the semiconductor substrate; and
and the N-type region and the P-type region are respectively formed in the well regions at two sides of the gate region.
According to the diode structure, the N-type region and the P-type region are formed in the well region, the N-type region and the P-type region form the PN junction, the grid region is formed on the well region between the N-type region and the P-type region, and distribution of well region current carriers between the P-type region and the N-type region can be regulated and controlled through the grid region, so that the withstand voltage of the PN junction is improved. Wherein, the well region has a first conduction type, the polysilicon gate layer has a second conduction type, the Fermi level of the well region is positioned at one side of the forbidden band center of the semiconductor substrate, the Fermi level of the polysilicon gate layer is positioned at the other side of the forbidden band center of the semiconductor substrate, the Fermi level of the polysilicon gate layer is adjusted to be positioned near the forbidden band center of the semiconductor substrate, the Fermi level of the polysilicon gate layer and the energy band distance of the forbidden band center of the semiconductor substrate are smaller than or equal to 0.3eV, the work function difference between the polysilicon gate layer and the well region below the polysilicon gate layer is smaller, the contact potential between the polysilicon gate layer and the well region is smaller, the function of forming an inversion layer by the well region between the P-type region and the N-type region is smaller, the PN junction withstand voltage is improved by the gate region control, and the leakage current between the N-type region and the P-type region is smaller, the voltage resistance of the diode structure is more stable, and the reliability of the diode structure is improved.
In one embodiment, the semiconductor substrate comprises a bottom substrate, a top substrate and an isolation layer formed between the bottom substrate and the top substrate, and the well region is formed in the top substrate.
In one embodiment, a first metal silicide is formed on the polysilicon gate layer, a second metal silicide is formed on the P-type region, a third metal silicide is formed on the N-type region, a gate is formed on the first metal silicide, an anode of the diode structure is formed on the second metal silicide, and a cathode of the diode structure is formed on the third metal silicide.
In one embodiment, the doping dose of the polysilicon gate layer is in the order of magnitude range of 1013cm-2-1014cm-2。
In one embodiment, the well region has a dopant dose on the order of 1012cm-2The doping dose of the N-type region and the P-type region is 1015cm-2。
In one embodiment, the dielectric constant of the polysilicon gate layer is in a range of 8 to 10.
In one embodiment, the energy band distance between the Fermi level of the polysilicon gate layer and the forbidden band center of the semiconductor substrate is greater than or equal to 0.1 eV.
The application also provides a preparation method of the novel diode structure.
A diode structure preparation method comprises the following steps:
providing a semiconductor substrate, and doping the first conductive type of the semiconductor substrate to form a well region;
forming a gate oxide layer on part of the well region, forming a polysilicon layer on the gate oxide layer, doping the polysilicon layer with a second conductivity type to form a polysilicon gate layer, wherein the gate oxide layer and the polysilicon gate layer form a gate region, and the energy band distance between the Fermi level of the polysilicon gate layer and the center of the forbidden band of the semiconductor substrate is less than or equal to 0.3 eV; and
and carrying out N-type doping on the well region on one side of the gate region to form an N-type region, and carrying out P-type doping on the well region on the other side of the gate region to form a P-type region.
According to the preparation method of the diode structure, the N-type region and the P-type region are formed in the well region, the gate oxide layer and the polycrystalline silicon gate layer are formed on the well region between the N-type region and the P-type region, the distance between the Fermi level of the polycrystalline silicon gate layer and the energy band of the forbidden band center of the semiconductor substrate is smaller than or equal to 0.3eV, the N-type region and the P-type region form a PN junction, and the withstand voltage of the PN junction can be adjusted through the polycrystalline silicon gate layer. In the present application, a semiconductor substrate is doped with a first conductivity type to form a well region, and a polysilicon layer is doped with a second conductivity type to form a polysilicon gate layer, i.e., the well region has the first conductivity type and the polysilicon gate layer has the second conductivity type. The Fermi level of the well region is positioned on one side of the center of a forbidden band of the semiconductor substrate, the Fermi level of the polysilicon gate layer is positioned on the other side of the center of the forbidden band of the semiconductor substrate, the Fermi level of the polysilicon gate layer is adjusted to enable the Fermi level of the polysilicon gate layer to be positioned near the center of the forbidden band of the semiconductor substrate, the energy band distance between the Fermi level of the polysilicon gate layer and the center of the forbidden band of the semiconductor substrate is less than or equal to 0.3eV, within the range, the work function difference between the polysilicon gate layer and the well region below the polysilicon gate layer is small, so that the contact potential between the polysilicon gate layer and the well region is small, the effect of forming an inversion layer in the well region between a P-type region and an N-type region is small, therefore, when the PN withstand voltage is controlled by the gate region, the leakage current between the N-type region and the P, thereby improving the reliability of the diode structure.
In one embodiment, the second conductivity type doping of the polysilicon layer is in an order of magnitude range of 1013cm-2-1014cm-2。
In one embodiment, the semiconductor substrate is doped with a dopant in an amount on the order of 1012cm-2The doping dose for N-type doping of the well region on one side of the gate region and P-type doping of the well region on the other side of the gate region is of the order of magnitude of 1015cm-2。
Drawings
Fig. 1 is a schematic structural diagram of a diode structure according to an embodiment of the present application;
FIG. 2 is a schematic energy band diagram of a diode structure according to an embodiment of the present application;
FIG. 3 is a flowchart illustrating steps of a method for fabricating a diode structure according to an embodiment of the present disclosure;
fig. 4a to 4e are structural state diagrams corresponding to steps of a diode structure manufacturing method according to an embodiment of the present application.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, the diode structure includes a semiconductor substrate 100 and a well region 131 formed in the semiconductor substrate, the well region 131 has a first conductivity type, a gate region is formed on the well region 131, the gate region is formed on a middle region of the well region 131, the gate region includes a gate oxide layer 200 formed on the well region 131 and a polysilicon gate layer 300 formed on the gate oxide layer 200, the polysilicon gate layer 300 has a second conductivity type doping, that is, the polysilicon gate layer 300 has a second conductivity type, a P-type region 132 and an N-type region 133 are formed in the well region 131 on both sides of the gate region, and the P-type region 132 and the N-type region 133 form a PN junction.
A gate region is formed on the well region between the P-type region 132 and the N-type region 133, by which the withstand voltage of the PN junction can be adjusted. Since the well region 131 has the first conductivity type and the polysilicon gate layer 300 has the second conductivity type, the fermi level of the well region 131 is located at one side of the center of the semiconductor substrate forbidden band, the fermi level of the polysilicon gate layer 300 is located at the other side of the center of the semiconductor substrate forbidden band, and the work function difference between the polysilicon gate layer 300 and the well region 131 is the energy band spacing of the fermi levels. Because the work function difference between the polysilicon gate layer and the well region is large, the contact potential between the polysilicon gate layer and the well region is high, and an inversion layer is easily formed in the well region between the P-type region and the N-type region, so that the leakage current of a PN junction is caused, and the withstand voltage of the PN junction is influenced. In the application, the fermi level of the polysilicon gate layer 300 is adjusted to enable the energy band distance between the fermi level of the polysilicon gate layer 300 and the forbidden band center of the semiconductor substrate to be less than or equal to 0.3eV, namely the fermi level of the polysilicon gate layer 300 is positioned near the forbidden band center of the semiconductor substrate, in the range, the work function difference between the polysilicon gate layer 300 and the well region 131 is small, the contact potential between the polysilicon gate layer 300 and the well region 131 is small, the effect of the inversion layer formed by the well region 131 below the polysilicon gate layer 300 is small, so that the leakage current of a PN junction is small, the voltage resistance of the PN junction is stable, and the reliability of a diode structure is improved. In the present application, by providing the gate region between the P-type region 132 and the N-type region 133 to adjust the withstand voltage of the PN junction, the diode structure is suitable for the process technology of 0.18 μm or less, has better compatibility with the CMOS process, and can be used in an integrated circuit with higher integration level.
The first conductive type may be a P type, the second conductive type may be an N type, or the first conductive type may be an N type, and the second conductive type may be a P type. In one embodiment, the first conductivity type is N-type, i.e., the well 131 is an N-type well, and the second conductivity type is P-type, i.e., the doping type of the polysilicon gate layer is P-type. Referring to fig. 2, the fermi level E of the well 131 with N-type dopingF1Higher than the forbidden band center EiI.e. the fermi level E of the well region 131F1At the center E of the forbidden bandiAnd the bottom of the guide belt ECW1 ═ E of well regionO-EF1Wherein E isOIs the vacuum electron energy level. Fermi level E of polysilicon gate layer 300 with P-type dopingF2Lower than the center E of the forbidden bandiI.e. the fermi level E of the polysilicon gate layer 300F2At the center E of the forbidden bandiAnd valence band top EVIn between, the work function W2 ═ E of the polysilicon gate layer 300O-EF2The work function difference W' between the polysilicon gate layer 300 and the well 131 is EF1-EF2. If a Fermi level E is chosenF3Is a polysilicon gate layer, assume EF3If the thickness is larger than 0.5eV, the work function between the polysilicon gate layer and the well region is large, which easily causes the problems of unstable leakage current and withstand voltage. In the present embodiment, the fermi level E of the polysilicon gate layer 300 is adjustedF2And forbidden band center EiIs less than or equal to 0.3eV even though the fermi level E of the polysilicon gate layer 300F2Closer to the center of the forbidden band EiIn this range, the work function difference between the polysilicon gate layer 300 and the well region 131 is small, the contact barrier between the polysilicon gate layer 300 and the well region 131 is small, the leakage current of the PN junction is reduced to be small, and the PN junction withstand voltage is more stable.
In an embodiment, with continued reference to fig. 1, the semiconductor substrate 100 includes a bottom substrate 110, a top substrate 130, and an isolation layer 120 formed between the bottom substrate 110 and the top substrate 130, wherein the isolation layer 120 may be a buried oxide layer, and the well region 131 is specifically formed in the top substrate 130. In one embodiment, the material of the bottom substrate 110 and the top substrate 130 is Silicon, and the isolation layer 120 is Silicon oxide, which is actually Silicon-On-Insulator (SOI) as the semiconductor substrate 100. In an embodiment, the bottom substrate 110 and the top substrate 120 have a second conductivity type.
In one embodiment, the polysilicon gate layer 300 is doped with a second conductivity type dopant in an amount on the order of 1013cm-2-1014cm-2. Typically, the dopant dose for polysilicon gates in power devices is in the order of 1015cm-2-1016cm-2The doping concentration is higher. In the embodiment, by controlling the doping concentration of the polysilicon gate layer 300, the work function between the polysilicon gate layer 300 and the well region 131 is reduced, so that the contact potential between the polysilicon gate layer 300 and the well region 131 is reduced, the leakage current is reduced, and the PN junction withstand voltage is more stable. It should be noted that although the doping concentration of the polysilicon gate layer 300 is low, the polysilicon gate layer still has a certain conductivity, and the formed diode can be used as an electrostatic protection device, and is fully compatible with the existing CMOS process, so that the integration level is high, and the chip area is saved. In one embodiment, to ensure a certain conductivity of the polysilicon gate layer 300, the polysilicon gate layer 300 has a certain doping concentration, and the distance between the fermi level of the polysilicon gate layer 300 and the energy band of the center of the forbidden band of the semiconductor is greater than or equal to 0.1 eV. In a specific embodiment, when the distance between the fermi level of the polysilicon gate layer 300 and the energy band at the center of the semiconductor forbidden band is equal to 0.15eV, the polysilicon gate layer 300 has better conductivity, the leakage current of the PN junction is very small and can be basically ignored, and the performance of the diode structure is optimal.
In one embodiment, the polysilicon gate layer 300 has a thickness ranging from 100nm to 200nm, a refractive index ranging from 1.4 to 1.6, and a dielectric constant ranging from 8 to 10. In one embodiment, the gate oxide layer 200 has a thickness in the range of
To
The voltage can be specifically adjusted according to the voltage specification.
In one embodiment, the doping dose of well 131 is on the order of 1012cm-2The dopant levels of P-type region 132 and N-type region 133 are on the order of 1015cm-2. That is, the well region 131 is lightly doped, the P-type region and the N-type region are heavily doped, and the P-type region and the N-type region form a PN junction in the well region 131.
In an embodiment, with reference to fig. 1, a first metal silicide 410 is formed on the polysilicon gate layer 300, a second metal silicide 420 is formed on the P-type region 132, a third metal silicide 430 is formed on the N-type region, an interlayer dielectric layer 500 is formed above the formed metal silicide, and a metal contact hole is formed in the interlayer dielectric layer 500, wherein a first metal contact hole 610 is formed on the first metal silicide 410, a gate is led out through the first metal contact hole 610, a second metal contact hole 620 is formed on the second metal silicide 420, an anode of the diode structure is led out through the second metal contact hole 620, a third metal contact hole 630 is formed on the third metal silicide 430, and a cathode of the diode structure is led out through the third metal contact hole 630.
In one embodiment, an oxygen-rich silicon layer may be formed on the well region between the P-type region and the N-type region in the diode structure, and the thickness of the oxygen-rich silicon layer may be in a range
To
The method can be adjusted according to different processes. Metal silicides are formed in the P-type area and the N-type area, the oxygen-rich silicon layer can be used as a metal silicide blocking layer, the well region between the P-type area and the N-type area can be shielded through the oxygen-rich silicon layer, and the metal silicides cannot be formed in the well region between the P-type area and the N-type area when the metal silicides are formed on the P-type area and the N-type area, so that the P-type area and the N-type area are isolated. The surface state defect of the oxygen-enriched silicon layer in contact with the well region is small, the work function difference between the oxygen-enriched silicon layer and the well region is small, and the problems of leakage current, unstable voltage resistance and the like of a diode structure can be avoided。
The application also relates to a diode structure preparation method, as shown in fig. 3, the preparation method comprises the following steps:
step S100: providing a semiconductor substrate, and doping the semiconductor substrate with a first conductive type to form a well region.
As shown in fig. 4a, a semiconductor substrate 100 is provided, and a well region 131 is formed by doping the semiconductor substrate 100 with a first conductivity type, wherein the first conductivity type doping has a dopant amount of the order of 1012cm-2That is, the semiconductor substrate 100 is lightly doped to form the lightly doped well region 131, and in an embodiment, the step of forming the well region 131 specifically includes: the surface of the semiconductor substrate 100 is implanted with first conductive type ions, and a rapid thermal process is performed to activate the impurity ions, so as to form a first conductive type well region, wherein the time of the thermal process may be 10S, which ensures that the first conductive type impurity ions are activated. In an embodiment, the semiconductor substrate includes a bottom substrate 110, a top substrate 130, and an isolation layer 120 formed between the bottom substrate 110 and the top substrate 130, wherein the isolation layer 120 may be a buried oxide layer, and the well region 131 is specifically formed in the top substrate 130. In one embodiment, the material of the bottom substrate 110 and the top substrate 130 is Silicon, and the isolation layer 120 is Silicon oxide, which is actually Silicon-On-Insulator (SOI) as the semiconductor substrate 100. In an embodiment, the bottom substrate 110 and the top substrate 120 have a second conductivity type.
Step S200: and forming a gate oxide layer on part of the well region, forming a polysilicon layer on the gate oxide layer, doping the polysilicon layer with a second conductivity type to form a polysilicon gate layer, wherein the gate oxide layer and the polysilicon gate layer form a gate region, and the distance between the Fermi level of the polysilicon gate layer and the energy band of the forbidden band center of the semiconductor substrate is less than or equal to 0.3 eV.
In one embodiment, the steps of forming a gate oxide layer over a portion of the well region and forming a polysilicon gate layer over the gate oxide layer sequentially include: forming a gate oxide layer 200 on the surface of the well region 131, specifically forming the gate oxide layer 200 on the surface of the well region 131 by thermal oxidation process, wherein the thickness of the gate oxide layer 200 is within the range of
To
The voltage can be adjusted according to voltage specifications; forming a polysilicon layer on the gate oxide layer 200; specifically, a polysilicon layer can be deposited on the gate oxide layer by a deposition process; doping the polysilicon layer with the second conductivity type to form a polysilicon gate layer 300, wherein the second conductivity type doping is performed on the polysilicon layer with a doping dose in the order of magnitude range of 1013cm-2-1014cm-2The polysilicon gate layer 300 has a thickness ranging from 100nm to 200nm, a refractive index ranging from 1.4 to 1.6, and a dielectric constant ranging from 8 to 10; etching part of the polysilicon gate layer and reserving the polysilicon gate layer 300 on the middle area of the well region, specifically forming a mask layer on the polysilicon gate layer through a photoetching process, and etching after defining an etching window through the mask layer; and etching the gate oxide layer by using the polysilicon gate layer as a mask and reserving the gate oxide layer 200 below the polysilicon gate layer 300.
Step S300: and carrying out N-type doping on the well region on one side of the gate region to form an N-type region, and carrying out P-type doping on the well region on the other side of the gate region to form a P-type region.
The well region 131 on one side of the gate region is doped P-type to form a P-type region 132, and the well region 131 on the other side of the gate region is doped N-type to form an N-type region 133, i.e., the P-type region 132 and the N-type region 133 are respectively located on two sides of the gate region. In one embodiment, as shown in fig. 4c and 4d, the step of forming the P-type region and the N-type region specifically includes: forming a first mask layer 710 on the well region 131 and the polysilicon gate layer 300 by a first photolithography process, defining a P-type region doping window through the first mask layer 710, injecting P-type doping ions to form a P-type region 132, and removing the first mask layer 710; forming a second mask layer 720 on the well region 131, the P-type region 132 and the polysilicon gate layer 300 by a second photolithography process, defining an N-type region doping window through the second mask layer 720, implanting N-type doping ions to form an N-type region 133, and removing the second mask layer 720, thereby forming a PN junction. In one embodiment, the dopant levels of P-type region 132 and N-type region 133 are on the order of 1015cm-2. I.e. the well region 131 are lightly doped, the P-type and N-type regions are heavily doped, and the P-type and N-type regions form a PN junction in the well region 131.
According to the preparation method of the diode structure, the Fermi level of the polycrystalline silicon gate layer 300 is controlled in the process of forming the polycrystalline silicon gate layer 300, the energy band distance of the Fermi level of the polycrystalline silicon gate layer 300, which is positioned at the center of a forbidden band of a semiconductor substrate, is smaller than or equal to 0.3eV, in the range, the work function difference between the polycrystalline silicon gate layer 300 and a well region 131 is smaller, the contact potential of the polycrystalline silicon gate layer and the well region is smaller, the effect of forming an inversion layer by the well region 131 below the polycrystalline silicon gate layer 300 is smaller, so that the leakage current of a PN junction is smaller, the withstand voltage of the PN junction is more stable, and the reliability of the diode. The problem of the diode structure is solved by controlling the work function of the polysilicon gate layer, and a new structure is not required to be added, so that an additional preparation process is not required to be added, and the method is simpler and has better effect.
The first conductive type may be a P type, the second conductive type may be an N type, or the first conductive type may be an N type, and the second conductive type may be a P type. In one embodiment, the first conductivity type is N-type, i.e., the well 131 is an N-type well, and the second conductivity type is P-type, i.e., the doping type of the polysilicon gate layer is P-type.
In one embodiment, as shown in fig. 4e, after forming the P-type region 132 and the N-type region 133, a step of forming a metal silicide on the P-type region 132, the N-type region 133 and the polysilicon gate layer 300 may be further included, specifically, a layer of metal silicide may be deposited downward through a deposition process, wherein a first metal silicide 410 is formed on the polysilicon gate layer 300, a second metal silicide 420 is formed on the P-type region 132, and a third metal silicide 430 is formed on the N-type region 133. After the metal silicide is formed, the interlayer dielectric layer 500 is deposited on the metal silicide, metal contact holes are formed in the interlayer dielectric layer 500, wherein a first metal contact hole 610 is formed in the first metal silicide 410, a grid electrode is led out through the first metal contact hole 610, a second metal contact hole 620 is formed in the second metal silicide 420, an anode of the diode structure is led out through the second metal contact hole 620, a third metal contact hole 630 is formed in the third metal silicide 430, and a cathode of the diode structure is led out through the third metal contact hole 630.
The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A diode structure, comprising:
a semiconductor substrate;
the well region is provided with a first conduction type and is formed in the semiconductor substrate;
a gate region including a gate oxide layer formed on a portion of the well region and a polysilicon gate layer formed on the gate oxide layer, the polysilicon gate layer having a second conductivity type, a fermi level of the polysilicon gate layer being less than or equal to 0.3eV from an energy band distance of a forbidden band center of the semiconductor substrate; and
and the N-type region and the P-type region are respectively formed in the well regions at two sides of the gate region.
2. The diode structure of claim 1, wherein the semiconductor substrate comprises a bottom substrate, a top substrate, and an isolation layer formed between the bottom substrate and the top substrate, the well region being formed within the top substrate.
3. The diode structure of claim 1, wherein the polysilicon gate layer has a first metal silicide formed thereon, the P-type region has a second metal silicide formed thereon, the N-type region has a third metal silicide formed thereon, the first metal silicide has a gate formed thereon, the second metal silicide has an anode of the diode structure formed thereon, and the third metal silicide has a cathode of the diode structure formed thereon.
4. The diode structure of claim 1 wherein said polysilicon gate layer has a dopant level in the range of 1013cm-2-1014cm-2。
5. The diode structure of claim 1 wherein said well region has a dopant dose on the order of 1012cm-2The doping dose of the N-type region and the P-type region is 1015cm-2。
6. The diode structure of claim 1, wherein the polysilicon gate layer has a dielectric constant in the range of 8 to 10.
7. The diode structure of claim 1, wherein a fermi level of the polysilicon gate layer is spaced from an energy band of a center of a forbidden band of the semiconductor substrate by an energy band distance of greater than or equal to 0.1 eV.
8. A method for preparing a diode structure is characterized by comprising the following steps:
providing a semiconductor substrate, and doping the first conductive type of the semiconductor substrate to form a well region;
forming a gate oxide layer on part of the well region, forming a polysilicon layer on the gate oxide layer, doping the polysilicon layer with a second conductivity type to form a polysilicon gate layer, wherein the gate oxide layer and the polysilicon gate layer form a gate region, and the energy band distance between the Fermi level of the polysilicon gate layer and the center of the forbidden band of the semiconductor substrate is less than or equal to 0.3 eV; and
and carrying out N-type doping on the well region on one side of the gate region to form an N-type region, and carrying out P-type doping on the well region on the other side of the gate region to form a P-type region.
9. The method of claim 8, wherein the polysilicon layer is doped with a second conductivity type dopant in an amount that is sufficient to form a second conductivity type diodeIn the order of magnitude of 1013cm-2-1014cm-2。
10. The method of claim 8, wherein the semiconductor substrate is doped with a dopant on the order of 1012cm-2The doping dose for N-type doping of the well region on one side of the gate region and P-type doping of the well region on the other side of the gate region is of the order of magnitude of 1015cm-2。
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| CN114122151A (en) * | 2020-08-28 | 2022-03-01 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
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