CN102082144A - Electro-static discharge (ESD) protection structure in silicon-on-insulator (SOI) circuit and manufacturing method thereof - Google Patents

Electro-static discharge (ESD) protection structure in silicon-on-insulator (SOI) circuit and manufacturing method thereof Download PDF

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Publication number
CN102082144A
CN102082144A CN 201010532715 CN201010532715A CN102082144A CN 102082144 A CN102082144 A CN 102082144A CN 201010532715 CN201010532715 CN 201010532715 CN 201010532715 A CN201010532715 A CN 201010532715A CN 102082144 A CN102082144 A CN 102082144A
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esd protection
gate control
protection device
type
control diode
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CN102082144B (en
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黄晓橹
魏星
程新红
陈静
张苗
王曦
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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Priority to CN 201010532715 priority Critical patent/CN102082144B/en
Priority to US13/002,303 priority patent/US8461651B2/en
Priority to PCT/CN2010/079847 priority patent/WO2012058840A1/en
Publication of CN102082144A publication Critical patent/CN102082144A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

The invention discloses an ESD protection structure in an SOI circuit and a manufacturing method thereof. The structure comprises an SOI substrate and a gate controlled diode ESD protection element positioned on the SOI substrate, wherein the gate controlled diode ESD protection element comprises a positive pole, a negative pole, a channel, a gate dielectric layer ad a gate; the positive pole and the negative pole are positioned at the two ends of the channel respectively, and the gate dielectric layer and the gate are positioned on the channel in turn; and the channel consists of an N-type area and a P-type area, and the N-type area and the P-type area form a longitudinal PN junction structure. In the invention, ion implantation is adopted to form a longitudinal large-area PN junction for ESD design, so the area of the PN junction is increased, the heavy-current release capacity is improved, integrity which compares with that of a bulk silicon ESD circuit is realized, and the robustness of the ESD in the SOI circuit is improved. The cost of the manufacturing process of the structure is low, and the structure is completely compatible with the conventional SOI circuit.

Description

Esd protection structure and manufacture method in a kind of SOI circuit
Technical field
The present invention relates to a kind of semiconductor device, relate in particular to a kind of esd protection structure that is used for silicon-on-insulator (SOI) circuit and preparation method thereof, belong to technical field of manufacturing semiconductors.
Background technology
CMOS is for lower power and higher speed and adopt silicon-on-insulator (Silicon On Insulator, SOI) substrate.In order to improve the reliability of device, the design of circuit must be considered static discharge (Electro-Static discharge, ESD) protection problem with application.Similar to the ESD design in the body silicon circuit, the diode network structure is also adopted in ESD design in the SOI circuit usually, the mixed-voltage interface (MVI, Mixed Voltage Interface) that constitutes as double diode structure, single diode structure, diode string network etc.
Yet; the SOI circuit is because the existence of buried oxidation layer (BOX) causes device channel region and substrate isolation; the existence in BOX district has a significant impact ESD failure mode and mechanism in the circuit; therefore in the SOI circuit, generally all adopt body to draw the mode that forms transverse diode at present and carry out ESD design, gate control diode esd protection structure for example shown in Figure 1.Mainly there is following shortcoming in this ESD design of carrying out in the transverse diode mode: there is the junction area smaller defect in (1), and junction area is less to have influenced big electric current releasability, causes ESD to lose efficacy when serious; (2) as increasing junction area, can only realize, increase the area of domain so greatly by the width that increases the ESD device.
ESD method for designing in a kind of new SOI circuit has been proposed: form a window by technologies such as photoetching etchings, top layer silicon and oxygen buried layer are etched away, expose SOI substrate tagma in the patent of application number 200910201331.0; Carry out side wall technology then; By technologies such as extension and planarizations SOI substrate tagma is drawn out to the same plane of top layer silicon at last.Preparation ESD device and circuit in epitaxial loayer are to reach vertical diode network structure ESD effect of conventional bulk silicon.Though this New type of S OI circuit ESD method for designing efficiently solves SOI traditional E SD limitation of design, its complex process, the cost height is because the existence of side wall also greatly reduces integrated level.
Given this, the present invention will propose the limitation that esd protection circuit that a kind of new design makes making can overcome conventional ESD design in the above-mentioned SOI circuit.
Summary of the invention
The technical problem to be solved in the present invention is to provide esd protection structure in a kind of SOI circuit and preparation method thereof.
In order to solve the problems of the technologies described above, the present invention adopts following technical scheme:
Esd protection structure in a kind of SOI circuit comprises the SOI substrate and is positioned at gate control diode esd protection device on the SOI substrate, it is characterized in that:
Described gate control diode esd protection device comprises: positive pole, negative pole, raceway groove, gate dielectric layer and grid; Described positive pole and negative pole lay respectively at the raceway groove two ends, and described gate dielectric layer and grid are positioned on the raceway groove successively; Described raceway groove is made up of N type district and p type island region, and described N type district and p type island region form PN junction structure longitudinally; Wherein, the p type island region of described raceway groove is positioned at and forms P type gate control diode esd protection device on the N type district, and perhaps the N type district of described raceway groove is positioned at and forms N type gate control diode esd protection device on the p type island region.
Preferably, be provided with the side wall isolation structure around described gate dielectric layer and the grid.
Preferably, be provided with fleet plough groove isolation structure around the described gate control diode esd protection device.
As one of preferred version of the present invention, the esd protection structure in this SOI circuit comprises a P type gate control diode esd protection device; Wherein, the negative pole of this P type gate control diode esd protection device connects the esd protection node in the SOI circuit, and positive pole is connected V with grid SS(device working power negative pole or ground connection), thus constitute the single diode esd protection circuit of grid-control.
As one of preferred version of the present invention, the esd protection structure in this SOI circuit comprises a N type gate control diode esd protection device; Wherein, the negative pole of this N type gate control diode esd protection device connects the esd protection node in the SOI circuit, the anodal V that connects SS(device working power negative pole or ground connection), grid connects V DD(device working power positive pole), thus constitute the single diode esd protection circuit of grid-control.
As one of preferred version of the present invention, the esd protection structure in this SOI circuit comprises a plurality of gate control diode esd protection devices.Further preferably, comprise a N type gate control diode esd protection device and a P type gate control diode esd protection device; Wherein, N type gate control diode esd protection device is connected with P type gate control diode esd protection device, and the negative pole of N type gate control diode esd protection device is connected V with grid DD, the positive pole of P type gate control diode esd protection device is connected V with grid SS, the positive pole of N type gate control diode esd protection device and the negative pole of P type gate control diode esd protection device are connected the esd protection node in the SOI circuit jointly, thereby constitute grid-control double diode esd protection circuit.
In addition; the present invention also provides the manufacture method of the esd protection structure in a kind of SOI circuit: when making described gate control diode esd protection device; on the SOI substrate, make N type district and p type island region by photoetching and ion implantation technology; form longitudinal P N knot, thereby form the raceway groove of described gate control diode esd protection device.
Beneficial effect of the present invention is:
The present invention inject to form vertical large tracts of land PN junction by ion and carries out the ESD design, increases the PN junction area greatly, improves big electric current releasability, realizes the integrated level that compares favourably with body silicon ESD circuit, improves the robustness of ESD in the SOI circuit.Its manufacturing process cost is low, and is compatible fully with the traditional SOI circuit.
Description of drawings
Fig. 1 is a gate control diode esd protection structure schematic diagram traditional in the background technology;
Fig. 2 is the esd protection structure schematic diagram among the embodiment one;
Fig. 3 is the esd protection structure schematic diagram among the embodiment two;
Fig. 4 a is the esd protection structure schematic diagram among the embodiment three;
Fig. 4 b is the principle schematic of the esd protection circuit among the embodiment three;
Fig. 5 a-5d is the making schematic flow sheet of the esd protection structure among the embodiment three.
Embodiment
Further specify esd protection structure in the SOI circuit provided by the invention below in conjunction with accompanying drawing, for the accompanying drawing that makes things convenient for that illustrates is proportionally drawn.
Embodiment one
Present embodiment is an example with the single diode esd protection circuit of P type grid-control, and the esd protection structure in a kind of SOI circuit is provided, and as shown in Figure 2, it comprises the SOI substrate and is positioned at a P type gate control diode esd protection device 10 on the SOI substrate.The SOI substrate is made up of bottom silicon Si, insulating buried layer BOX and top layer silicon Si.Preparation has a plurality of PMOS pipes and NMOS pipe on the SOI substrate, is used to connect into the SOI circuit, and each element is isolated by fleet plough groove isolation structure (STI) usually, and only draw here a PMOS pipe and a NMOS pipe are as signal.
Described P type gate control diode esd protection device 10 comprises: anodal (P+ zone) 11, negative pole (N+ zone) 12, raceway groove, gate dielectric layer 13 and grid 14; Described anodal 11 and negative pole 12 lay respectively at the raceway groove two ends, described gate dielectric layer 13 and grid 14 are positioned on the raceway groove successively; Described raceway groove is made up of N type district 16 and p type island region 15, and described N type district 16 forms PN junction structure longitudinally with p type island region 15, and wherein, p type island region 15 is positioned on the N type district 16.
Preferably, around described gate dielectric layer 13 and grid 14, be provided with side wall isolation structure 17; Be provided with fleet plough groove isolation structure 18 around the described gate control diode esd protection device 10.
This P type gate control diode esd protection device 10 and traditional P type raceway groove grid-control diode-like are seemingly; but because its raceway groove is a longitudinal P N junction structure; this device has increased the PN junction area of whole gate control diode greatly on the basis that keeps original device area; can improve big electric current releasability as the esd protection device, and not influence the integrated level of esd protection circuit.
With the esd protection node in the negative pole connection SOI circuit of this P type gate control diode esd protection device 10, positive pole is connected V with grid by metal interconnecting wires SS(device working power negative pole or ground connection) can constitute the single diode esd protection circuit of grid-control, and the SOI circuit is played the esd protection effect.
Embodiment two
Present embodiment is an example with the single diode esd protection circuit of N type grid-control, and the esd protection structure in a kind of SOI circuit is provided, and as shown in Figure 3, it comprises the SOI substrate and is positioned at a N type gate control diode esd protection device 20 on the SOI substrate.Described N type gate control diode esd protection device 2O comprises: positive pole 21, negative pole 22, raceway groove, gate dielectric layer 23 and grid 24; Described anodal 21 and negative pole 22 lay respectively at the raceway groove two ends, described gate dielectric layer 23 and grid 24 are positioned on the raceway groove successively; Described raceway groove is made up of N type district 26 and p type island region 25, and described N type district 26 forms PN junction structure longitudinally with p type island region 25, and wherein, N type district 26 is positioned on the p type island region 25.
Preferably, around described gate dielectric layer 23 and grid 24, be provided with side wall isolation structure 27; Be provided with fleet plough groove isolation structure 28 around the described gate control diode esd protection device 20.
This N type gate control diode esd protection device 20 and traditional N type raceway groove grid-control diode-like are seemingly; but because its raceway groove is a longitudinal P N junction structure; this device has increased the PN junction area of whole gate control diode greatly on the basis that keeps original device area; can improve big electric current releasability as the esd protection device, and not influence the integrated level of esd protection circuit.
With the esd protection node in the negative pole 22 connection SOI circuit of this N type gate control diode esd protection device 20, anodal 21 connect V by metal interconnecting wires SS(device working power negative pole or ground connection), grid 24 connects V DD(device working power positive pole), thus constitute the single diode esd protection circuit of grid-control.
Embodiment three
Present embodiment is an example with grid-control double diode esd protection circuit; esd protection structure in a kind of SOI circuit is provided; shown in Fig. 4 a, it comprises the S0I substrate and is positioned at a P type gate control diode esd protection device 10 ' and a N type gate control diode esd protection device 20 ' on the SOI substrate.
Wherein, N type gate control diode esd protection device 20 ' is connected with P type gate control diode esd protection device 10 ', and the negative pole of N type gate control diode esd protection device 20 ' is connected V with grid DD, the positive pole of P type gate control diode esd protection device 10 ' is connected V with grid SS, the positive pole of N type gate control diode esd protection device 20 ' and the negative pole of P type gate control diode esd protection device 10 ' are connected the esd protection node in the SOI circuit jointly, thereby constitute grid-control double diode esd protection circuit.Wherein the circuit theory diagrams of this grid-control double diode esd protection circuit are shown in Fig. 4 b.
It should be noted that at this esd protection structure in SOI circuit of the present invention is not limited only to above-mentioned three kinds of embodiment, for example can also comprise more multiple-grid control diode esd protection device and other esd protection devices, thereby can constitute various esd protection circuits.
Referring to Fig. 5 a-5d, the method for making embodiment three described esd protection structures may further comprise the steps:
At first, shown in Fig. 5 a, can utilize traditional SOI technology on the SOI substrate, to make fleet plough groove isolation structure (STI).
Then; utilize photoetching process to apply photoresist making on the SOI substrate of fleet plough groove isolation structure, and exposure, develop, offer window at the assigned address of esd protection device; in the top layer silicon of SOI substrate, form p type island region and N type district by ion implantation technology, thereby form longitudinal P N knot.For example, make N type gate control diode esd protection device and P type gate control diode esd protection device respectively, the longitudinal P N that longitudinal P N ties and P goes up under the N that then utilizes technologies such as photoetching and ion injection to form respectively under the last P of N ties, shown in Fig. 5 b and Fig. 5 c.
SOI circuit technology with traditional is identical afterwards, and longitudinal P N under P on N knot two ends make P+ district and N+ district respectively as positive pole and negative pole, at this longitudinal P N side of tying making gate dielectric layer and grid, thus formation N type gate control diode esd protection device.Same can form P type gate control diode esd protection device on the basis of the knot of the longitudinal P N under the N on the P.And make SOI circuit required device, finish embodiment three described esd protection structures by metal interconnecting wires at last.
Embodiment one is similar with the manufacture method and the above-mentioned processing step of embodiment two described esd protection structures, so give unnecessary details no longer one by one.
The other technologies that relate among the present invention belong to the category that those skilled in the art are familiar with, and do not repeat them here.The foregoing description is the unrestricted technical scheme of the present invention in order to explanation only.Any technical scheme that does not break away from spirit and scope of the invention all should be encompassed in the middle of the patent claim of the present invention.

Claims (8)

1. the esd protection structure in the SOI circuit comprises the SOI substrate and is positioned at gate control diode esd protection device on the SOI substrate, it is characterized in that:
Described gate control diode esd protection device comprises: positive pole, negative pole, raceway groove, gate dielectric layer and grid; Described positive pole and negative pole lay respectively at the raceway groove two ends, and described gate dielectric layer and grid are positioned on the raceway groove successively; Described raceway groove is made up of N type district and p type island region, and described N type district and p type island region form PN junction structure longitudinally; Wherein, the p type island region of described raceway groove is positioned at and forms P type gate control diode esd protection device on the N type district, and perhaps the N type district of described raceway groove is positioned at and forms N type gate control diode esd protection device on the p type island region.
2. according to the esd protection structure in the described a kind of SOI circuit of claim 1, it is characterized in that: be provided with the side wall isolation structure around described gate dielectric layer and the grid.
3. according to the esd protection structure in the described a kind of SOI circuit of claim 1, it is characterized in that: be provided with fleet plough groove isolation structure around the described gate control diode esd protection device.
4. according to the esd protection structure in the described a kind of SOI circuit of claim 1, it is characterized in that: comprise a P type gate control diode esd protection device; Wherein, the negative pole of this P type gate control diode esd protection device connects the esd protection node in the SOI circuit, and positive pole is connected V with grid SSThereby, constitute the single diode esd protection circuit of grid-control, V SSBe meant device working power negative pole or ground connection.
5. according to the esd protection structure in the described a kind of SOI circuit of claim 1, it is characterized in that: comprise a N type gate control diode esd protection device; Wherein, the negative pole of this N type gate control diode esd protection device connects the esd protection node in the SOI circuit, the anodal V that connects SS, grid connects V DDThereby, constitute the single diode esd protection circuit of grid-control, V SSBe meant device working power negative pole or ground connection, V DDBe meant device working power positive pole.
6. according to the esd protection structure in the described a kind of SOI circuit of claim 1, it is characterized in that: comprise a plurality of gate control diode esd protection devices.
7. according to the esd protection structure in the described a kind of SOI circuit of claim 6, it is characterized in that: comprise a N type gate control diode esd protection device and a P type gate control diode esd protection device; Wherein, N type gate control diode esd protection device is connected with P type gate control diode esd protection device, and the negative pole of N type gate control diode esd protection device is connected V with grid DD, the positive pole of P type gate control diode esd protection device is connected V with grid SS, the positive pole of N type gate control diode esd protection device and the negative pole of P type gate control diode esd protection device are connected the esd protection node in the SOI circuit jointly, thereby constitute grid-control double diode esd protection circuit, V SSBe meant device working power negative pole or ground connection, V DDBe meant device working power positive pole.
8. manufacture method as the esd protection structure in each described SOI circuit among the claim 1-7; it is characterized in that: when making described gate control diode esd protection device; on the SOI substrate, make N type district and p type island region by photoetching and ion implantation technology; form longitudinal P N knot, thereby form the raceway groove of described gate control diode esd protection device.
CN 201010532715 2010-11-04 2010-11-04 Electro-static discharge (ESD) protection structure in silicon-on-insulator (SOI) circuit and manufacturing method thereof Expired - Fee Related CN102082144B (en)

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Application Number Priority Date Filing Date Title
CN 201010532715 CN102082144B (en) 2010-11-04 2010-11-04 Electro-static discharge (ESD) protection structure in silicon-on-insulator (SOI) circuit and manufacturing method thereof
US13/002,303 US8461651B2 (en) 2010-11-04 2010-12-16 ESD protection devices for SOI integrated circuit and manufacturing method thereof
PCT/CN2010/079847 WO2012058840A1 (en) 2010-11-04 2010-12-16 Esd protection structure in soi circuit and method for making the same

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CN102364687A (en) * 2011-11-03 2012-02-29 中国电子科技集团公司第五十八研究所 Electrostatic discharge (ESD) protection structure between silicon-on-insulator (SOI)/CMOS integrated circuit power supply and ground
CN102779819A (en) * 2012-08-17 2012-11-14 中国电子科技集团公司第五十八研究所 ESD (Electronic Static Discharge) protection structure based on partial depletion mode SOI (Silicon on Insulator) process
CN106129056A (en) * 2016-07-01 2016-11-16 中国电子科技集团公司第五十八研究所 The export structure of high ESD tolerance based on PD SOI technology
CN107492569A (en) * 2016-06-12 2017-12-19 中芯国际集成电路制造(上海)有限公司 Gate control diode and forming method thereof
CN111326589A (en) * 2018-12-17 2020-06-23 无锡华润微电子有限公司 Diode structure and preparation method thereof

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CN1851923A (en) * 2006-05-24 2006-10-25 杭州电子科技大学 SOI LIGBT device unit of integrated ESD diode
CN101276788A (en) * 2007-03-28 2008-10-01 中国科学院微电子研究所 Method for improving electrostatic discharge protection performance of silicon circuit on insulator

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US6855981B2 (en) * 2001-08-29 2005-02-15 Denso Corporation Silicon carbide power device having protective diode
US6858900B2 (en) * 2001-10-08 2005-02-22 Winbond Electronics Corp ESD protection devices and methods to reduce trigger voltage
JP5295603B2 (en) * 2008-03-27 2013-09-18 ラピスセミコンダクタ株式会社 ESD protection element and manufacturing method thereof

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US20020109153A1 (en) * 2001-02-15 2002-08-15 Ming-Dou Ker Silicon-on-insulator diodes and ESD protection circuits
CN1851923A (en) * 2006-05-24 2006-10-25 杭州电子科技大学 SOI LIGBT device unit of integrated ESD diode
CN101276788A (en) * 2007-03-28 2008-10-01 中国科学院微电子研究所 Method for improving electrostatic discharge protection performance of silicon circuit on insulator

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102364687A (en) * 2011-11-03 2012-02-29 中国电子科技集团公司第五十八研究所 Electrostatic discharge (ESD) protection structure between silicon-on-insulator (SOI)/CMOS integrated circuit power supply and ground
CN102779819A (en) * 2012-08-17 2012-11-14 中国电子科技集团公司第五十八研究所 ESD (Electronic Static Discharge) protection structure based on partial depletion mode SOI (Silicon on Insulator) process
CN102779819B (en) * 2012-08-17 2014-12-03 中国电子科技集团公司第五十八研究所 ESD (Electronic Static Discharge) protection structure based on partial depletion mode SOI (Silicon on Insulator) process
CN107492569A (en) * 2016-06-12 2017-12-19 中芯国际集成电路制造(上海)有限公司 Gate control diode and forming method thereof
CN106129056A (en) * 2016-07-01 2016-11-16 中国电子科技集团公司第五十八研究所 The export structure of high ESD tolerance based on PD SOI technology
CN111326589A (en) * 2018-12-17 2020-06-23 无锡华润微电子有限公司 Diode structure and preparation method thereof
CN111326589B (en) * 2018-12-17 2023-08-25 无锡华润微电子有限公司 Diode structure and preparation method thereof

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