CN106129056A - The export structure of high ESD tolerance based on PD SOI technology - Google Patents

The export structure of high ESD tolerance based on PD SOI technology Download PDF

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Publication number
CN106129056A
CN106129056A CN201610518318.8A CN201610518318A CN106129056A CN 106129056 A CN106129056 A CN 106129056A CN 201610518318 A CN201610518318 A CN 201610518318A CN 106129056 A CN106129056 A CN 106129056A
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CN
China
Prior art keywords
nmos tube
source
pmos
export
diffusion region
Prior art date
Application number
CN201610518318.8A
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Chinese (zh)
Inventor
高国平
周晓彬
贺凌炜
罗静
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中国电子科技集团公司第五十八研究所
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Priority to CN201610518318.8A priority Critical patent/CN106129056A/en
Publication of CN106129056A publication Critical patent/CN106129056A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

Abstract

The present invention relates to the export structure of high ESD tolerance based on PD SOI technology, including the first NMOS tube N1, second NMOS tube N2 and PMOS P1, when export structure is used in output port, the drain terminal of the first NMOS tube N1 is connected with output port with the drain terminal of PMOS P1, the source of PMOS P1 is connected with power supply, the source of the first NMOS tube N1 is connected with the drain terminal of the second NMOS tube N2, the source of the second NMOS tube N2 is connected to the ground, PMOS P1, the substrate of the first NMOS tube N1 and the second NMOS tube N2 is connected with respective source respectively, the grid of NMOS tube drives biasing by prime.The present invention uses NMOS tube common in SOI technology, uses the ESD protective device leakage currents such as gate control diode when ESD arrives, exports NMOS tube not easy damaged, improves the ability of the ESD protection of circuit output.

Description

The export structure of high ESD tolerance based on PD-SOI technique

Technical field

The invention belongs to SOI technology ESD design protection technical field, relate to a kind of based on PD-SOI (part depletion type SOI) export structure of the high ESD tolerance of technique.

Background technology

SOI technology refers to be formed on the insulating layer to be had the material of certain thickness single crystal semiconductor silicon membrane layer and prepares Technology and manufacture the Technology of semiconductor device on thin layer.This technology can realize medium isolation completely, and with P-N The body silicon device of junction isolation is compared, have without breech lock, at high speed, low-power consumption, the advantage such as high, high temperature resistant, the radiation hardness of integrated level.

According to SOI silicon film thickness, SOI device can be divided into thick devices and thin-film device.For thick film SOI device Speech, when SOI silicon film thickness is more than when being maximally depleted width of twice, is referred to as part depletion device;For Thin film SOI device Speech, when SOI silicon film thickness is less than when being maximally depleted width, is referred to as fully-depleted device.

In SOI technology, device is fabricated in the silicon fiml that top layer is the thinnest, is buried oxide layer by one layer between device and substrate Separate.The most this structure makes SOI/MOS device have many merits low in energy consumption of Denging, compared with traditional body silicon MOS technique, It is more suitable for high performance ULSI and VLSI circuit.Its advantage specifically includes that

1, without latch-up.Due to the existence of dielectric isolation structure in SOI/MOS device, the most do not arrive the electric current of substrate Passage, the path of latch-up is cut off, and between each device physically and the most mutually isolated, and improve circuit can By property.

2, simple in construction, technique is simple, and integration density is high.SOI/MOS device architecture is simple, it is not necessary to prepare Bulk CMOS The complicated isolation technology such as the trap of circuit, device minimum interval is dependent only on the restriction of photoetching and lithographic technique, and integration density is big Width improves.SOI/MOS device is also particularly suitable for integrated high voltage and low-voltage circuit on the same chip, therefore has the highest chip Area utilization and cost performance.

3, parasitic capacitance is little, and operating rate is fast.The main electric capacity of body silicon MOS device is pipe source-drain area and source/drain expansion Dissipating the electric capacity between region and substrate, it increases with the doping content of substrate and increases, and this is by the load capacitance of increasing circuit, shadow Ring the operating rate of circuit;In SOI/MOS device, P-N cannot be formed owing to burying the existence of oxide layer, source-drain area and substrate Knot, P-N junction parasitic capacitance disappears, the substitute is buried oxidation layer electric capacity, and the dielectric that this electric capacity is proportional to capacitance material is normal Number, its value is much smaller than the P-N junction parasitic capacitance of source-drain area in body silicon with substrate, and is not affected by scaled down.

4, low-power consumption.The power consumption of SOI/MOS device is made up of quiescent dissipation and two parts of dynamic power consumption, and SOI device has Having steep sub-threshold slope, close to desirable level, therefore leakage current is the least, and quiescent dissipation is the lowest;Due to SOI/MOS device Having the junction capacity less than body silicon device and wire capacitances, under the most same operating rate, dynamic power consumption is greatly reduced.

Analyze from ESD protection, owing to SOI technology MOS device is burying what oxide layer was formed, compared with body silicon, reduce The heat dissipating mass of device, so the ESD protective capability of device weakens significantly, especially exports NMOS tube.

ESD to SOI technology circuit protects and uses two ways more the most in the world: 1, utilize gate control diode to carry out ESD protects, the characteristic of the main forward conduction using gate control diode.2, use the metal-oxide-semiconductor dynamically opened, mainly use MOS Pipe and parasitic gate control diode simultaneously turn on.Both the above mode is difficult to meet the demand that input/output end port is various.

Summary of the invention

The technical problem to be solved in the present invention is to overcome existing defect, it is provided that a kind of high ESD based on PD-SOI technique The export structure of tolerance, uses metal-oxide-semiconductor common in SOI technology, uses the ESD such as gate control diode to protect when ESD arrives Protect device leakage current, export NMOS tube not easy damaged, improve the ability of the ESD protection of circuit.

In order to solve above-mentioned technical problem, the invention provides following technical scheme:

The export structure of the present invention high ESD tolerance based on PD-SOI technique, this export structure includes a NMOS Pipe N1, the second NMOS tube N2 and PMOS P1, when export structure is used in output port, the drain terminal of the first NMOS tube N1 and PMOS The drain terminal of pipe P1 is connected with output port, and the source of PMOS P1 is connected with power supply, the source of the first NMOS tube N1 and second The drain terminal of NMOS tube N2 is connected, and the source of the second NMOS tube N2 is connected to the ground, PMOS P1, the first NMOS tube N1 and the 2nd NMOS The substrate of pipe N2 is connected with respective source respectively, and the grid of the first NMOS tube N1 and the second NMOS tube N2 is connected and and PMOS The grid of P1 all drives biasing by prime.

Further, output port includes the first gate control diode D1, the second gate control diode D2 and output pressure welding point, the The negative pole of one gate control diode D1 is connected with power vd D, the positive pole of the first gate control diode D1, the second gate control diode D2 negative Pole, the drain terminal of the first NMOS tube N1, PMOS P1 drain terminal with output pressure welding point be connected, the positive pole of the second gate control diode D2 and Ground GND is connected.

Further, in export structure, the first NMOS tube N1 and the second NMOS tube N2 are P type substrate NMOS tube, this p-type Substrate NMOS tube includes that poly grid, diffusion region, N+ source, N+ leakage diffusion region, p-well, silicon dioxide isolation area, BOX bury oxide layer and silicon Substrate, p-well is between diffusion region, N+ source and N+ leakage diffusion region, and BOX buries oxide layer and is positioned on silicon substrate, diffusion region, N+ source, N + leakage diffusion region, p-well, silicon dioxide isolation area are positioned at BOX and bury on oxide layer, and poly grid are positioned on p-well, silicon dioxide every Surround diffusion region, N+ source from district and N+ leaks diffusion region.

Beneficial effects of the present invention: use metal-oxide-semiconductor common in SOI technology, uses gate control diode etc. when ESD arrives ESD protective device leakage current, exports NMOS tube not easy damaged;This structure utilizes series connection NMOS tube to improve the resistance to of NMOS tube entirety Pressure, improves the ESD tolerance of output.

Accompanying drawing explanation

Fig. 1 is the circuit diagram of the present invention;

Fig. 2 be the present invention for output port circuit figure;

Fig. 3 be the present invention for the nmos device profile between output port and GND.

Detailed description of the invention

Embodiment cited by the present invention, is only intended to help and understands the present invention, should not be construed as the present invention is protected model The restriction enclosed, for those skilled in the art, without departing from the inventive concept of the premise, it is also possible to right The present invention makes improvements and modifications, and these improve and modification also falls in the range of the claims in the present invention protection.

As it is shown in figure 1, the export structure of high ESD tolerance based on PD-SOI technique, including the first NMOS tube N1, Two NMOS tube N2 and PMOS P1, when export structure is used in output port 3, the drain terminal 8 of the first NMOS tube N1 and PMOS P1 Drain terminal 7 be connected with output port 3 by semiconductor alloy aluminum, the source 6 of PMOS P1 is by semiconductor alloy aluminum and power supply 1 Being connected, the source 9 of the first NMOS tube N1 is connected by the drain terminal 10 of semiconductor alloy aluminum and the second NMOS tube N2, the second NMOS tube The source 11 of N2 is connected with ground 2 by semiconductor alloy aluminum, PMOS P1, the first NMOS tube N1 and the substrate of the second NMOS tube N2 Being connected with respective source by semiconductor alloy aluminum respectively, the grid 5 of the first NMOS tube N1 and the second NMOS tube N2 is connected.

As in figure 2 it is shown, output port 3 includes the first gate control diode D1, the second gate control diode D2 and output pressure welding point 20, the negative pole of the first gate control diode D1 is connected with power vd D, the positive pole of the first gate control diode D1, the second gate control diode The negative pole of D2, the drain terminal 8 of the first NMOS tube N1, the drain terminal 7 of PMOS P1 are connected with output pressure welding point 20, the second gate control diode The positive pole of D2 is connected with ground GND.When the second gate control diode D2 is used in output pressure welding point 20 and ground GND, the first gate control diode D1 is used in output pressure welding point 20 and time power vd D carries out ESD protection, and the drain terminal 8 of the first NMOS tube N1 is by semiconductor alloy aluminum Connecting output pressure welding point 20, the drain electrode 7 of PMOS P1 connects output pressure welding point 20, the first NMOS tube N1 by semiconductor alloy aluminum Source connect the drain terminal of the second NMOS tube N2 also by semiconductor alloy aluminum, the source of the second NMOS tube N2 is by quasiconductor gold Belong to aluminum and connect ground, the first NMOS tube N1 and the second NMOS tube N2 grid connection pre-driver circuitry 19, and drive electricity by prime Road 19 biases, and the grid 4 of PMOS P1 also connects pre-driver circuitry 19.

As it is shown on figure 3, the first NMOS tube N1 and the second NMOS tube N2 are P type substrate NMOS tube in this export structure, this P Type substrate NMOS tube includes that poly grid 18, diffusion region, N+ source 14, N+ leak diffusion region 15, p-well 16, silicon dioxide isolation area 17, BOX Burying oxide layer 13 and silicon substrate 12, p-well 16 is between leakage diffusion region 15, diffusion region, N+ source 14 and N+, and BOX buries oxide layer 13 On silicon substrate 12, diffusion region, N+ source 14, N+ leakage diffusion region 15, p-well 16, silicon dioxide isolation area 17 are positioned at BOX and bury oxidation On layer 13, poly grid 18 are positioned on p-well 16, and silicon dioxide isolation area 17 surrounds diffusion region, N+ source 14 and N+ and leaks diffusion region 15。

The operation principle of the present invention is as follows: first, and output pressure welding point 20 voltage raises, and ESD electric current passes through the first grid-control two Pole pipe D1 leakage current, when reaching the second gate control diode D2 breakdown voltage, the second gate control diode D2 punctures, along with ESD Electric current is gradually increased, and the voltage of output pressure welding point 20 raises further, owing to the first NMOS tube N1 and the second NMOS tube N2 are connected, The drain terminal of the first NMOS tube N1 over the ground 2 breakdown voltage be the twice of single NMOS tube, if thus the electricity of output pressure welding point 20 Pressure, less than the twice of NMOS tube breakdown voltage, exports the first NMOS tube N1 and the second NMOS tube N2, will not be breakdown, will not damage Wound, substantially increases the ESD ability of output port 3.

Present invention advantage compared with prior art: use NMOS tube common in SOI technology, uses when ESD arrives The ESD protective device leakage currents such as gate control diode, output NMOS tube is difficult to puncture, thus not easy damaged, improve circuit defeated The ability of the ESD protection gone out;This export structure based on PD-SOI technique compared with traditional SOI technology export structure, device Simply, it is easy to promote, applied range, as power supply-between inside weak structure, mixed-voltage compatible port, Ke Yiyou Effect improves the ESD tolerance level of integrated circuit.

Claims (3)

1. the export structure of high ESD tolerance based on PD-SOI technique, it is characterised in that: described export structure includes first NMOS tube N1, the second NMOS tube N2 and PMOS P1, when described export structure is used in output port (3), the first NMOS tube N1 Drain terminal (8) be connected with output port (3) with the drain terminal (7) of PMOS P1, the source (6) of PMOS P1 is connected with power supply (1), The source (9) of the first NMOS tube N1 is connected with the drain terminal (10) of the second NMOS tube N2, the source (11) of the second NMOS tube N2 and ground (2) being connected, the substrate of PMOS P1, the first NMOS tube N1 and the second NMOS tube N2 is connected with respective source respectively, and first The grid (5) of NMOS tube N1 and the second NMOS tube N2 is connected and all drives (19) inclined by prime with the grid (4) of PMOS P1 Put.
The export structure of high ESD tolerance based on PD-SOI technique the most according to claim 1, it is characterised in that: Described output port (3) includes the first gate control diode D1, the second gate control diode D2 and output pressure welding point (20), the first grid-control The negative pole of diode D1 is connected with power vd D, the positive pole of the first gate control diode D1, the negative pole of the second gate control diode D2, The drain terminal (8) of one NMOS tube N1, the drain terminal (7) of PMOS P1 are connected with output pressure welding point (20), the second gate control diode D2's Positive pole is connected with ground GND.
The export structure of high ESD tolerance based on PD-SOI technique the most according to claim 1, it is characterised in that: In described export structure, the first NMOS tube N1 and the second NMOS tube N2 are P type substrate NMOS tube, and this P type substrate NMOS tube includes Poly grid (18), diffusion region, N+ source (14), N+ leakage diffusion region (15), p-well (16), silicon dioxide isolation area (17), BOX bury oxidation Layer (13) and silicon substrate (12), p-well (16) is positioned between diffusion region, N+ source (14) and N+ leakage diffusion region (15), and BOX buries oxide layer (13) it is positioned on silicon substrate (12), diffusion region, N+ source (14), N+ leakage diffusion region (15), p-well (16), silicon dioxide isolation area (17) being positioned at BOX and bury on oxide layer (13), poly grid (18) are positioned on p-well (16), and silicon dioxide isolation area (17) surround N Diffusion region ,+source (14) and N+ leakage diffusion region (15).
CN201610518318.8A 2016-07-01 2016-07-01 The export structure of high ESD tolerance based on PD SOI technology CN106129056A (en)

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1658388A (en) * 2004-02-18 2005-08-24 富士通株式会社 Electrostatic discharge protection circuit
CN1914731A (en) * 2004-02-07 2007-02-14 三星电子株式会社 Buffer circuit having electrostatic discharge protection
TW200711252A (en) * 2005-09-08 2007-03-16 Realtek Semiconductor Corp Schmitt trigger with electrostatic discharge (ESD) protection
CN101355357A (en) * 2008-09-04 2009-01-28 中国电子科技集团公司第五十八研究所 ESD protection structure for output buffer of SOI/CMOS integrated circuit
CN102082144A (en) * 2010-11-04 2011-06-01 中国科学院上海微系统与信息技术研究所 Electro-static discharge (ESD) protection structure in silicon-on-insulator (SOI) circuit and manufacturing method thereof
CN102779819A (en) * 2012-08-17 2012-11-14 中国电子科技集团公司第五十八研究所 ESD (Electronic Static Discharge) protection structure based on partial depletion mode SOI (Silicon on Insulator) process
US20130077196A1 (en) * 2011-09-28 2013-03-28 Texas Instruments Incorporated ESD Robust Level Shifter
CN103022996A (en) * 2011-09-21 2013-04-03 中芯国际集成电路制造(北京)有限公司 Electronic static discharge protection circuit and electronic static discharge protection method
CN104733520A (en) * 2015-03-18 2015-06-24 单毅 Thyristor for electrostatic protection

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1914731A (en) * 2004-02-07 2007-02-14 三星电子株式会社 Buffer circuit having electrostatic discharge protection
CN1658388A (en) * 2004-02-18 2005-08-24 富士通株式会社 Electrostatic discharge protection circuit
TW200711252A (en) * 2005-09-08 2007-03-16 Realtek Semiconductor Corp Schmitt trigger with electrostatic discharge (ESD) protection
CN101355357A (en) * 2008-09-04 2009-01-28 中国电子科技集团公司第五十八研究所 ESD protection structure for output buffer of SOI/CMOS integrated circuit
CN102082144A (en) * 2010-11-04 2011-06-01 中国科学院上海微系统与信息技术研究所 Electro-static discharge (ESD) protection structure in silicon-on-insulator (SOI) circuit and manufacturing method thereof
CN103022996A (en) * 2011-09-21 2013-04-03 中芯国际集成电路制造(北京)有限公司 Electronic static discharge protection circuit and electronic static discharge protection method
US20130077196A1 (en) * 2011-09-28 2013-03-28 Texas Instruments Incorporated ESD Robust Level Shifter
CN102779819A (en) * 2012-08-17 2012-11-14 中国电子科技集团公司第五十八研究所 ESD (Electronic Static Discharge) protection structure based on partial depletion mode SOI (Silicon on Insulator) process
CN104733520A (en) * 2015-03-18 2015-06-24 单毅 Thyristor for electrostatic protection

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Application publication date: 20161116