KR101850851B1 - Transient voltage suppressor and manufacturing method thereof - Google Patents

Abstract

Various embodiments of the present invention relate to a transient voltage suppressing device and a manufacturing method thereof. The purpose of the present invention is to provide the transient voltage suppressing device in which circumferential device regions having a rectifier diode and a zener diode are formed to be radially arranged when viewed in plane with a central device region, having a diode, as a center, so as not to increase the area of the circumferential device regions to extend a current passage while maintaining a low capacitance, thereby improving current properties (Ipp), and the manufacturing method thereof. For this purpose, the transient voltage suppressing device of the present invention comprises: a substrate of a first conductive type; a pair of embedded layers of a second conductive type embedded in the substrate and spaced in a horizontal direction; an epitaxial layer of the first conductive type formed on the substrate and on the pair of embedded layers; the central device region having a well region of the second conductive type formed on a surface of the epitaxial layer between the pair of embedded layers such that the central diode is formed in a vertical direction; and the circumferential device regions having regions of the first conductive type formed on the surface of the epitaxial layer overlapping each of the pair of embedded layers so that the rectifier diode and the zener diode are formed in the vertical direction, wherein the circumferential device regions are radially arranged with the central device region as a center when viewed in plane.

Description

[0001] Transient voltage suppressor and manufacturing method [0002]

Various embodiments of the present invention are directed to transient voltage suppression devices and methods of making the same.

Referring to FIG. 1, the operation principle and circuit diagram of a conventional transient voltage suppressing element are shown.

As shown in FIG. 1, a transient voltage suppressing device TVS (for example, varistor, thyristor, diode (rectifier / zener)) is connected in parallel between a power source V _G and a load R _LOAD , And one side of the transient voltage suppressing element is connected to the ground (GND).

With this arrangement, when an excessive voltage exceeding the voltage required by the load R _LOAD is input, the transient current I _TV caused by the transient voltage flows toward the ground GND via the transient voltage suppressing element TVS , by applying a low voltage is clamped to stabilize only the load (R _lOAD), the load (R _lOAD) is protected from excess voltage.

The above-described information disclosed in the background of the present invention is only for improving the understanding of the background of the present invention, and thus may include information not constituting the prior art.

Various embodiments of the present invention provide a transient voltage suppression element and a method of manufacturing the same. That is, in various embodiments of the present invention, the peripheral element region having the rectifying diode and the zener diode is arranged to be arranged in a radial direction when viewed from the plane, with the center of the central element region having the diode, so that the area of the peripheral element region is not increased, The present invention provides a transient voltage suppressing element and a method of manufacturing the transient voltage suppressing element that can improve the current characteristics Ipp by expanding the current path while maintaining a low capacitance.

A transient voltage suppressor according to various embodiments of the present invention includes: a substrate of a first conductivity type; A pair of second conductive buried layers buried in the substrate and horizontally spaced apart; An epitaxial layer of a first conductivity type formed over the substrate and the pair of buried layers; A central element region in which a well region of a second conductivity type is formed on a surface of the epitaxial layer between the pair of buried layers to form a center diode in a vertical direction; And a peripheral element region in which a first conductive type region is formed on a surface of the epitaxial layer superimposed on each of the pair of buried layers to form a rectifying diode and a zener diode in a vertical direction, The peripheral element region may be arranged radially around the region.

And the peripheral element region may be formed symmetrically with respect to the central element region.

The peripheral element region may extend in a horizontal direction away from the central element region about the central element region.

A first isolation line in the form of an arc, the first isolation line having a boundary with the central element region; A second isolation line extending radially outwardly from the central element region; A third isolation line extending radially outward from the central element region and spaced apart from the second isolation line; And a fourth isolation line connecting ends of the second isolation line and the third isolation line opposite to the first isolation line.

The length of the fourth isolation line may be longer than the length of the first isolation line.

The length of the second and third isolation lines may be longer than the length of the first and fourth isolation lines.

The epitaxial layer may be interposed between the radially arranged peripheral element regions.

The buried layer and the first conductivity type region may be arranged radially about the central element region when viewed in plan view.

When viewed in plan, the buried layer is formed in a circular shape around the central element region, and the first conductive type region can be arranged radially.

A method of fabricating a transient voltage suppression device according to various embodiments of the present invention includes: preparing a substrate of a first conductivity type; Forming a pair of horizontally spaced second conductive buried layers in the substrate; Forming an epitaxial layer of a first conductivity type over the substrate and the buried layer; Forming a central diode region in a vertical direction by forming a well region of a second conductivity type on the surface of the epitaxial layer between the pair of the buried layers; And a peripheral element region forming step of forming a rectifying diode and a zener diode in a vertical direction by forming a first conductive type region on the surface of the epitaxial layer superimposed on each of the pair of buried layers, The peripheral element region about the central element region may be arranged radially.

The buried layer and the first conductivity type region may be arranged radially about the central element region when viewed in plan view.

When viewed in plan, the buried layer is formed in a circular shape around the central element region, and the first conductive type region can be arranged radially.

Various embodiments of the present invention provide a transient voltage suppression element and a method of manufacturing the same. That is, in various embodiments of the present invention, the peripheral element region having the rectifying diode and the zener diode is arranged to be arranged in a radial direction when viewed from the plane, with the center of the central element region having the diode, so that the area of the peripheral element region is not increased, The present invention provides a transient voltage suppressing element and a method of manufacturing the transient voltage suppressing element, which can improve the current characteristics while maintaining the capacitance while enlarging the current path.

1 is a circuit diagram showing the operation principle of a general transient voltage suppressing element.
FIG. 2A is a plan view showing a transient voltage suppressing element according to an embodiment of the present invention, and FIGS. 2B and 2C are sectional views of lines 2b-2b and 2c-2c, respectively, of FIG.
3 is a flowchart illustrating a method of manufacturing a transient voltage suppressor according to an embodiment of the present invention.
4A to 4G are cross-sectional views illustrating a method of manufacturing a transient voltage suppressing device according to an embodiment of the present invention.
5 shows an example of an equivalent circuit of a transient voltage suppressing element according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are described in order to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified into various other forms, It is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be more faithful and complete, and will fully convey the scope of the invention to those skilled in the art.

In the following drawings, thickness and size of each layer are exaggerated for convenience and clarity of description, and the same reference numerals denote the same elements in the drawings. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items. In the present specification, the term " connected "means not only the case where the A member and the B member are directly connected but also the case where the C member is interposed between the A member and the B member and the A member and the B member are indirectly connected do.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" include singular forms unless the context clearly dictates otherwise. Also, " comprise, " and / or "comprising, " when used in this specification, are intended to be interchangeable with the said forms, numbers, steps, operations, elements, elements and / And does not preclude the presence or addition of one or more other features, integers, operations, elements, elements, and / or groups.

Although the terms first, second, etc. are used herein to describe various elements, components, regions, layers and / or portions, these members, components, regions, layers and / It is obvious that no. These terms are only used to distinguish one member, component, region, layer or section from another region, layer or section. Thus, a first member, component, region, layer or section described below may refer to a second member, component, region, layer or section without departing from the teachings of the present invention.

It is to be understood that the terms related to space such as "beneath," "below," "lower," "above, But may be utilized for an easy understanding of other elements or features. Terms related to such a space are for easy understanding of the present invention depending on various process states or use conditions of the present invention, and are not intended to limit the present invention. For example, if an element or feature of the drawing is inverted, the element or feature described as "lower" or "below" will be "upper" or "above." Thus, "lower" is a concept encompassing "upper" or "lower ".

FIG. 2A is a plan view showing a transient voltage suppressing element 100 according to an embodiment of the present invention, and FIGS. 2B and 2C are sectional views of lines 2b-2b and 2c-2c, respectively, of FIG.

2A, 2B and 2C, a transient voltage suppressor 100 according to an embodiment of the present invention includes a substrate 110, a buried layer 120, an epitaxial layer 130, A central element region 140, a peripheral element region 150, and an upper electrode 140.

The substrate 110 may be a semiconductor of the first conductivity type. That is, the substrate 110 may be a plate-like shape including a substantially flat upper surface and a substantially flat lower surface. The substrate 110 may be, for example, but not limited to, an N ++ type semiconductor formed by implanting an impurity such as arsenic (As), phosphorus (P), or antimony (Sb) Substrate. Here, the high concentration means that the concentration is relatively higher than the impurity concentration of the first conductivity type region 152, which will be described later.

The buried layer 120 may be a semiconductor of the second conductivity type. In addition, the buried layer 120 may be buried in the substrate 110 and be horizontally spaced from each other. Substantially, the buried layer 120 may be formed in a shape that is separated from each other in a horizontal direction when viewed in cross section, or in a circular shape or a radial shape when viewed in plan view. The buried layer 120 may be formed by implanting or diffusing a P + type semiconductor, such as, for example, an impurity such as gallium (Ga), indium (In), or boron (B) (110).

The epitaxial layer 130 may be a semiconductor of the first conductivity type. That is, the epitaxial layer 130 may be formed by depositing an N-type semiconductor on the substrate 110 and the pair of buried layers 120. Here, the pair of buried layers 120 are diffused together with the substrate 110 as well as the epitaxial layer 130.

A central isolation region 141 is formed from the epitaxial layer 130 between the pair of the buried layers 120 to the substrate 110 and the epitaxial layer 130 corresponding to the pair of the buried layers 120 To the buried layer 120 is formed. The central isolation region 141 and the peripheral isolation region 151 may be formed by inserting an insulator into the trench after each trench is formed. A central element region 140 is formed on the inner side of the central isolation region 141 and a peripheral element region 150 is formed on the inner side of the peripheral isolation region 151.

The central element region 140 is formed by forming a well region 142 of a second conductivity type on the surface of the epitaxial layer 130 between the pair of the buried layers 120 to form a central diode in the vertical direction. That is, the well region 142 of the second conductivity type is formed from the surface of the central epitaxial layer 130 toward the inside. More specifically, as the inside of the central isolation region 141, a well region 142 may be formed by ion-implanting a high concentration P + -type impurity inward from the surface of the epitaxial layer 130 between the pair of the buried layers 120 . The width of the well region 142 in the horizontal direction may be the same as the width in the inner horizontal direction of the central isolation region 141. The well region 142 is formed by first forming an insulating film (not shown) such as a silicon oxide film or a nitrogen oxide film and then directly implanting gallium (Ga), indium (In) or boron (B) By using the thermal diffusion process, the well region 142 of the second conductivity type, which is P + type, can be formed. A center diode (i.e., a rectification diode) is formed in the vertical direction by the well region 142 of the second conductivity type, the epitaxial layer 130 of the first conductivity type, and the substrate 110 of the first conductivity type And the central element region 140 is provided by this structure.

In the peripheral device region 150, a first conductive type region 152 is formed on the surface of the epitaxial layer 130 overlapping each of the pair of the buried layers 120 to form a rectifying diode and a zener diode in the vertical direction . That is, the first conductive type region 152 is formed from the surface of the peripheral epitaxial layer 130 toward the inside. More specifically, the N + type impurity is ion-implanted inwardly from the surface of the epitaxial layer 130 which overlaps with the pair of buried layers 120 as the inside of the peripheral isolation region 151 to form the first conductive type region 152 . The width in the horizontal direction of the first conductivity type region 152 may be equal to the width in the inner horizontal direction of the circumference isolation region 151. The first conductive type region 152 is formed by forming an insulating film (not shown) such as a silicon oxide film or a nitrogen oxide film and then directly implanting arsenic (As), phosphorus (P), or antimony (Sb) Or by using a thermal diffusion process, the N + type high concentration first conductivity type region 152 can be formed. Here, the high concentration means that the concentration is relatively large in comparison with the impurity concentration of the epitaxial layer 130.

The rectifying diodes in the vertical direction are formed by the first conductive type region 152 and the second conductive type buried layer 120 and the second conductive type buried layer 120 is formed on the first conductive type substrate 110 A zener diode is formed in a vertical direction, and the peripheral device region 150 is provided by this structure.

On the other hand, when the transient voltage suppressing element 100 is viewed from a plane (see FIG. 2A), a substantially rectangular peripheral element region 140 (that is, a well region 142 of the second conductivity type) The device region 150 (i.e., the first conductive type region 152 and / or the buried layer 120) may be arranged radially.

When the transient voltage suppressing element 100 is viewed in cross section (see FIG. 2B), the peripheral element region 150 is formed symmetrically about the center element region 140. That is, the left and right peripheral element regions 150 are formed in the same shape with respect to the center element region 140.

When the transient voltage suppressing element 100 is viewed from a plane / cross-sectional view, the peripheral element region 150 extends in the horizontal direction away from the central element region 140 by a predetermined length .

2A), the substantially circular central element region 140 is isolated by the approximately circular ring-shaped central isolation region 141, and the substantially rectangular peripheral element region 140 is surrounded by the substantially rectangular ring- The element region 150 is isolated by the substantially rectangular-line-shaped peripheral insulated region 151. [

In particular, the peripheral isolation region 151 isolating the peripheral element region 150 (or the first conductive type region 152 and / or the buried layer 120) includes an arc-shaped element A second isolation line 151b extending radially outwardly from the central element region 140 and a second isolation line 151b extending radially outward from the central element region 140, And a fourth isolation line 151d connecting the ends of the second isolation line 152b and the third isolation line 152c and spaced apart from the first isolation line 151a, .

Here, the length of the fourth isolation line 151d may be longer than the length of the first isolation line 151a. That is, the peripheral element region 150 (or the first conductive type region 152 and / or the buried layer 120) may gradually become wider as the distance from the central element region 140 increases.

Also, the lengths of the second and third isolation lines 151b and 151c may be longer than the lengths of the first and fourth isolation lines 151a and 151d. That is, the peripheral element region 150 (or the first conductive type region 152 and / or the buried layer 120) may be relatively long and approximately rectangular in shape as it moves away from the central element region 140.

Here, when the transient voltage suppressing element 100 is viewed in a plan view, the buried layer 120 and the first conductive type region 152 are arranged radially around the central element region 140, or the transient voltage suppressing element 100 The buried layer 120 is formed in the form of a circular ring around the central element region 140 and the first conductive type regions 152 can be separated and arranged radially.

In addition, as shown in FIGS. 2A and 2B, since the epitaxial layer 130 can be directly interposed between the peripheral element regions 150 arranged in a radial direction, current does not flow through this portion .

The upper electrode 160 is formed on the central element region 140 (that is, the second conductive type well region 142) and the peripheral element region 150 (i.e., the first conductive type region 152) And a lower electrode (not shown) is formed on the lower surface of the substrate 110. [ Of course, the insulating film 170 is interposed between the central insulating region 141 and the peripheral insulating region 151, and the insulating film 170 is also formed on the outer side of the peripheral insulating region 151, And does not directly contact the epitaxial layer 130.

Thus, in various embodiments of the present invention, the peripheral element region 150 having the rectifying diode and the zener diode is formed to be arranged radially when viewed from the plane, with the center element region 140 having the diode as a center, The present invention provides a transient voltage suppressing element 100 that can improve the current characteristics Ipp by enlarging the current path while maintaining the low capacitance without increasing the area of the region 150. [

3 is a flowchart showing a method of manufacturing the transient voltage suppressing device 100 according to an embodiment of the present invention.

3, the method for manufacturing the transient voltage suppressing device 100 according to the present invention includes a substrate preparation step S1, a buried layer forming step S2, an epitaxial layer forming step S3, Forming step S4, a well region forming step S5, a first conductivity type region forming step S6, and an electrode forming step S7. Here, the order of the well region formation step (S5) and the first conductivity type region formation step (S6) may be mutually changed.

4A to 4G are cross-sectional views illustrating a method of manufacturing the transient voltage suppressing element 100 according to an embodiment of the present invention. Here, referring to FIG. 3 together, a method of manufacturing the transient voltage suppressing element 100 will be described.

As shown in FIG. 4A, in the substrate preparation step S1, a substrate 110 of the first conductivity type is prepared. The substrate 110 may be in the form of a plate including an upper surface and a lower surface. The substrate 110 may be, for example, an N ++ type semiconductor substrate formed by implanting an impurity such as arsenic (As), phosphorus (P), or antimony (Sb), which is a Group 5 element, into the intrinsic semiconductor at high concentration. Here, the high concentration means that the concentration is relatively higher than the impurity concentration of the first conductivity type region 152, which will be described later. On the other hand, the substrate 110 of the first conductivity type may be of the P ++ type in which impurity such as gallium (Ga), indium (In), or boron (B), which is a group III element, is implanted into the intrinsic semiconductor at high concentration. However, in the present invention, it is assumed that the substrate 110 is of the N ++ type.

As shown in FIG. 4B, in the buried layer forming step S2, a buried layer 120 of a second conductive type spaced horizontally on the upper surface of the substrate 110 is formed. Here, the buried layer 120 is formed to have a certain depth from the upper surface of the substrate 110 toward the inside. In addition, the buried layers 120 may be spaced apart from each other by a certain distance.

The buried layer 120 is formed by first forming an insulating film (not shown) such as a silicon oxide film or a nitrogen oxide film on the upper surface of the substrate 110 in a region other than the region where the buried layer 120 is formed and then forming a gallium ), Indium (In), boron (B), or the like can be directly implanted or a thermal diffusion process can be used to form the buried layer 120 of high concentration P + type.

On the other hand, a bottom insulating film may be formed on the bottom surface of the substrate 110. The insulating film may be formed of any one selected from the group consisting of a silicon oxide film, a nitrogen oxide film, undoped polysilicon, Phospho-Silicate-Glass (PSG), Borophosphoric Silicate-Glass (BPSG) However, the present invention is not limited thereto. The insulating layer prevents auto-doping of the first conductivity type substrate 110 having a high concentration.

As shown in FIG. 4C, in the epitaxial layer forming step S3, the epitaxial layer 130 may be formed on the upper surface of the substrate 110. FIG. For example, at the high temperature of 600 to 2000 ° C, SiH ₄ (P) or antimony (Sb), which are pentavalent elements such as As, P, or Sb, are flowed together at a low concentration to form N-type impurities on the surface of the substrate 110 and the buried layer 120 Of epitaxial layer 130 may be deposited. At this time, the epitaxial layer 130 is deposited on the surface of the buried layer 120, and the buried layer 120 forms an approximately elliptical buried layer 120 diffused into the epitaxial layer 130 by the doping gases.

4D, in the isolation region forming step S4, the central isolation region 141 and the peripheral isolation region 151 are formed.

The central isolation region 141 is formed by forming a trench from the epitaxial layer 130 to the substrate 110 between a pair of the buried layers 120 which are spaced apart from each other and then filling the trench with an insulating material. A central element region 140 is formed later in the central isolation region 141.

The peripheral isolation region 151 is formed by forming a trench to the epitaxial layer 130 and the buried layer 120 under the epitaxial layer 130, and filling the trench with an insulating material. The peripheral device region 150 is formed later in the peripheral region 151.

Here, the central isolation region 141 and the peripheral isolation region 151 are exposed, for example, leaving only a mask (not shown) defining the position of the trench first, so that a pattern is formed in the epitaxial layer 130. [ And then a trench is formed through reactive ion etching or dry etching or the like using a mask opening. Then, the central isolation region 141 and the peripheral isolation region 151 are formed by filling the trench with an insulating material such as a silicon oxide film or a nitrogen oxide film. However, the method of forming the center and peripheral isolation regions 141 and 151 is not limited in the present invention, and various methods not described herein are possible.

4E, in the well region formation step S5, the well region 142 of the second conductivity type is formed from the surface of the epitaxial layer 130 toward the inside. More specifically, as the inside of the central isolation region 141, the well region 142 is formed by ion implantation from the surface of the epitaxial layer 130 between the pair of the buried layers 120 to the inside. The width of the well region 142 in the horizontal direction is equal to the width in the horizontal direction of the center of the central isolation region 141. The well region 142 is formed by first forming an insulating film (not shown) such as a silicon oxide film or a nitrogen oxide film and then directly implanting gallium (Ga), indium (In) or boron (B) The well region 142 of the second conductivity type which is P + type can be formed by using the thermal diffusion process. This well region 142 is a component of the central element region 140.

As shown in FIG. 4F, in the first conductive type region forming step S6, the first conductive type region 152 is formed from the surface of the epitaxial layer 130 toward the inside thereof.

More specifically, the first conductive type region 152 is formed by ion implantation inward from the surface of the epitaxial layer 130 on the buried layer 120 as the inside of the peripheral isolation region 151. The width in the horizontal direction of the first conductivity type region 152 is equal to the width in the inner horizontal direction of the surrounding region 151. [ The first conductive type region 152 may be formed by forming an insulating film (not shown) such as a silicon oxide film or a nitrogen oxide film and then depositing arsenic (As), phosphorus (P), or antimony (Sb) The N + type high concentration first conductivity type region 152 can be formed by implanting or using a thermal diffusion process. Here, the high concentration means that the concentration is relatively large in comparison with the impurity concentration of the epitaxial layer 130. This first conductive type region 152 becomes a component of the peripheral element region 150. [

4G, the upper electrode 160 is formed on the upper surface of the central element region 140 and the peripheral element region 150 in the electrode formation step S7, and the upper electrode 160 is formed on the lower surface of the substrate 110 An electrode (not shown) is formed. In this manner, the upper electrode 160 electrically connects the central element region 140 and the peripheral element region 150. That is, the upper electrode 160 electrically connects the second conductive type well region 142 of the central element region 140 and the first conductive type region 152 of the peripheral element region 150 to each other.

Here, the upper electrode 160 and the lower electrode may be formed by sequentially sputtering or sequentially plating one selected from molybdenum (Mo), aluminum (Al), nickel (Ni), gold (Au) The present invention is not limited thereto.

An insulating film 170 may be formed between the central element region 140 and the peripheral element region 150 and outside the peripheral element region 150. This may be a silicon oxide film, a nitrogen oxide film, an undoped polysilicon undoped polysilicon, phospho-silicate-glass (PSG), borophosphoric-silicate-glass (BPSG), or equivalents thereof. However, the present invention is not limited thereto.

5 shows an example of an equivalent circuit of the transient voltage suppressing element 100 according to an embodiment of the present invention.

5, the first conductive type epitaxial layer 130 and the first conductive type substrate 110 are formed on the second conductive type well region 142 of the central element region 140, Thereby forming a rectifying diode. 5, a rectifying diode is formed by the first conductive type region 152 and the second conductive type buried layer 120 in the peripheral device region 150 and the second conductive type buried layer 120 is formed by the second conductive type buried layer 120, A zener diode is formed between the first conductive type substrate 110 and the first conductive type substrate 110. Here, the cathode of the rectifying diode at the center and the anode of the rectifying diode around the electrode are electrically connected by the upper electrode 160, and the anode of the rectifying diode at the center and the anode of the Zener diode at the periphery are electrically connected by the lower electrode . Therefore, this diode connection structure operates as the transient voltage suppressing element 100. [

Here, it can be seen that one central element region including the central diode is formed, and the number of the peripheral element regions having the rectifier diodes and the zener diodes connected in series between the peripheries is eight (see FIG. 2A). Further, it can be seen that eight peripheral element regions are connected in a radial fashion around one central element region in parallel.

Thus, the various embodiments of the present invention are arranged such that the peripheral element regions having the rectifying diodes and the zener diodes around the central element region having the diodes are arranged radially when viewed in plan, so that the area of the peripheral element region is not increased, The present invention provides a transient voltage suppressing element 100 capable of improving current (Ipp) characteristics while maintaining a capacitance while enlarging a current path and a method of manufacturing the same.

For example, in the conventional 5V 0.5pF class bi-directional transient voltage suppressor, the current (Ipp) was 5A. However, in the case of the 5V 0.5pF class bi-directional transient voltage suppressor employing the above structure, It can be seen that the transient voltage suppressor according to the embodiment of the present invention has an Ipp which shows a current characteristic while having a low capacitance as in the prior art by about 30%.

It is to be understood that the present invention is not limited to the above-described embodiment, and various modifications may be made without departing from the scope of the present invention as set forth in the following claims It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

100; The transient voltage suppressor < RTI ID = 0.0 >
110; Substrate 120; Buried layer
130; An epitaxial layer 140; Central element region
141; A central isolation region 142; Well region
150; A peripheral element region 151; Circumferential isolation region
152; A first conductive type region 160; The upper electrode
170; Insulating film

Claims (12)

A substrate of a first conductivity type;
A pair of second conductive buried layers buried in the substrate and horizontally spaced apart;
An epitaxial layer of a first conductivity type formed over the substrate and the pair of buried layers;
A central element region in which a well region of a second conductivity type is formed on a surface of the epitaxial layer between the pair of buried layers to form a center diode in a vertical direction; And
And a peripheral element region in which a first conductive type region is formed on a surface of the epitaxial layer superimposed on each of the pair of buried layers to form a rectifying diode and a zener diode in a vertical direction,
Wherein the peripheral element region is arranged radially with respect to the central element region when viewed in plan. The method according to claim 1,
Wherein the peripheral element region is formed symmetrically with respect to the central element region. The method according to claim 1,
And the peripheral element region extends in a horizontal direction away from the central element region, with the center element region being the center. The method according to claim 1,
When viewed in plan, the peripheral element region
A first isolation line in the form of an arc bordering the central element region;
A second isolation line extending radially outwardly from the central element region;
A third isolation line extending radially outward from the central element region and spaced apart from the second isolation line; And
And a fourth isolation line connecting the ends of the second isolation line and the third isolation line opposite to the first isolation line. 5. The method of claim 4,
Wherein a length of the fourth isolation line is longer than a length of the first isolation line. 5. The method of claim 4,
Wherein a length of the second and third isolation lines is longer than a length of the first and fourth isolation lines. The method according to claim 1,
And wherein the epitaxial layer is interposed between the peripheral element regions arranged in the radial direction. The method according to claim 1,
Wherein said buried layer and said first conductivity type region are arranged radially about said central element region when viewed in plan. The method according to claim 1,
Wherein said buried layer is formed in a circular shape with respect to said central element region when viewed in plan, and said first conductivity type region is arranged radially. Preparing a substrate of a first conductivity type;
Forming a pair of horizontally spaced second conductive buried layers in the substrate;
Forming an epitaxial layer of a first conductivity type over the substrate and the buried layer;
Forming a central diode region in a vertical direction by forming a well region of a second conductivity type on the surface of the epitaxial layer between the pair of the buried layers; And
And forming a rectifying diode and a zener diode in a vertical direction by forming a first conductive type region on a surface of the epitaxial layer overlapped with each of the pair of buried layers,
Wherein the peripheral element region is arranged radially with respect to the central element region when viewed in plan. 11. The method of claim 10,
Wherein the buried layer and the first conductive type region are arranged radially with respect to the central element region when viewed in plan. 11. The method of claim 10,
Wherein the buried layer is formed in a circular shape with respect to the central element region when viewed in a plane, and the first conductive type region is arranged radially.

Images