KR20180086784A - Transient voltage suppressor and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a transient voltage suppressor, which forms a first buried layer of a second conductive type, and a second buried layer of a first conductive type on an upper portion of the first buried layer, forms a third buried layer of the second conductive type on the outside the second buried layer, and applies a trench process to form a plurality of isolation layers, such that a capacitance can be reduced, a maximum allowable surge current can be improved, and a clamping voltage can be reduced, and to a manufacturing method thereof. According to an embodiment of the present invention, the transient voltage suppressor comprises: a first conductive type substrate; a first epitaxial layer of a first conductive type, formed on an upper portion of the substrate; a first buried layer of a second conductive type, formed inside the first epitaxial layer; a second epitaxial layer of the first conductive type, formed on an upper portion of the first epitaxial layer and the first buried layer; a second buried layer of the first conductive type, formed inside the second epitaxial layer, and formed on the upper portion of the first buried layer; a third buried layer of the second conductive type, formed in a ring shape the outside the second buried layer; a third epitaxial layer of the first conductive type, formed on upper portions of the second epitaxial layer and the second and third buried layers; a plurality of isolation layers formed from a surface of the third epitaxial layer toward the substrate; first and second conductive regions spaced apart from each other toward the inside thereof from the surface of the third epitaxial layer; and electrode formed on surfaces of the first and second conductive regions.

Description

[0001] Transient voltage suppressor and manufacturing method [0002]

The present invention relates to a transient voltage suppressing element and a method of manufacturing the same.

Referring to FIG. 1, the operation principle and circuit diagram of a conventional transient voltage suppressing element are shown.

As shown in FIG. 1, a transient voltage suppressing device TVS (for example, varistor, thyristor, diode (rectifier / zener)) is connected in parallel between a power source V _G and a load R _LOAD , And one side of the transient voltage suppressing element is connected to the ground (GND).

With this configuration, when an excessive voltage exceeding a voltage required by the load R _LOAD is input, the transient current ITV due to the transient voltage flows to the ground GND through the transient voltage suppressing element TVS, by being applied to a load (R _lOAD) it is a stabilized low-voltage clamping only, and the load (R _lOAD) is protected from excess voltage.

The present invention provides a transient voltage suppressing element capable of reducing capacitance, improving a maximum allowable surge current (Ipp) and lowering a clamping voltage, and a method of manufacturing the same.

A transient voltage suppressor according to the present invention includes: a substrate of a first conductivity type; A first epitaxial layer of a first conductivity type formed on the substrate; A first buried layer of a second conductivity type formed in the first epitaxial layer; A second epitaxial layer of a first conductivity type formed on the first epitaxial layer and the first buried layer; A second buried layer of a first conductivity type formed inside the second epitaxial layer and formed on an upper portion of the first buried layer; a third buried layer of a second conductivity type formed in the form of a ring outside the second buried layer; A third epitaxial layer of a first conductivity type formed on top of the second epitaxial layer and the second and third buried layers; A plurality of isolation layers formed from the surface of the third epitaxial layer toward the substrate; A first conductive type region and a second conductive type region formed so as to be spaced apart from the surface of the third epitaxial layer inwardly; And electrodes formed on the surfaces of the first conductive type region and the second conductive type region.

The second buried layer and the third buried layer may contact the first buried layer.

Wherein the isolation layer is formed in a circular ring shape and includes a first isolation layer formed at the center, a second isolation layer formed outside the first isolation layer, a third isolation layer formed outside the second isolation layer, And a fourth isolation layer formed outside the third isolation layer.

The first isolation layer is formed from the surface of the third epitaxial layer to the inside of the second buried layer and the second isolation layer is formed from the surface of the third epitaxial layer to the inside of the second buried layer and the inside of the first buried layer The third isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer and the first buried layer, and the fourth isolation layer is formed from the surface of the third epitaxial layer to the inside of the third epitaxial layer, The third buried layer and the first buried layer.

The first conductive type region may be formed between the third isolation layer and the fourth isolation layer.

The second conductive type region may be formed between the first isolation layer and the second isolation layer.

A first diode may be formed on a junction surface of the second conductive type region and the third epitaxial layer.

A second diode may be formed between the third isolation layer and the fourth isolation layer on the junction surface of the third epitaxial layer and the third buried layer.

On the inner side of the first isolation layer, a zener diode may be formed on the bonding surfaces of the first and second buried layers.

According to another aspect of the present invention, there is provided a method of fabricating a transient voltage suppressor, including: forming a first epitaxial layer of a first conductivity type on a substrate of a first conductivity type; A first embedding layer forming step of forming a first embedding layer of a second conductivity type inside the first epitaxial layer; A second epitaxial layer forming step of forming a second epitaxial layer of a first conductivity type on the first epitaxial layer and the first buried layer; Forming a second buried layer of the first conductivity type inside the second epitaxial layer and overlying the first buried layer and forming a ring-shaped third buried layer of the second conductivity type on the outer side of the second buried layer; Forming a second buried layer; A third epitaxial layer forming step of forming a third epitaxial layer of the first conductivity type on the second epitaxial layer and the second and third buried layers; Forming a plurality of spaced apart isolation layers from the surface of the third epitaxial layer toward the substrate; Forming a first conductive type region and a second conductive type region from the surface of the third epitaxial layer toward the substrate and spaced apart from each other; And an electrode forming step of forming electrodes on the surfaces of the first conductive type region and the second conductive type region.

In the forming the second buried layer, the second buried layer and the third buried layer may be formed to contact the first buried layer.

In the isolation layer formation step, the isolation layer is formed in a circular ring shape, and the isolation layer includes a first isolation layer formed at the center, a second isolation layer formed outside the first isolation layer, And a fourth isolation layer formed on the outer side of the third isolation layer.

The first isolation layer is formed from the surface of the third epitaxial layer to the inside of the second buried layer and the second isolation layer is formed from the surface of the third epitaxial layer to the inside of the second buried layer and the inside of the first buried layer The third isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer and the first buried layer, and the fourth isolation layer is formed from the surface of the third epitaxial layer to the inside of the third epitaxial layer, The third buried layer and the first buried layer.

In the first and second conductivity type regions, the first conductivity type region may be formed between the third and fourth isolation layers.

In the first and second conductivity type regions, the second conductivity type region may be formed between the first and second isolation layers.

A first diode may be formed on a junction surface of the second conductive type region and the third epitaxial layer.

A second diode may be formed between the third isolation layer and the fourth isolation layer on the junction surface of the third epitaxial layer and the third buried layer.

On the inner side of the first isolation layer, a zener diode may be formed on the bonding surfaces of the first and second buried layers.

The transient voltage suppressing element and the method of fabricating the same according to an embodiment of the present invention include forming a first buried layer of the second conductivity type and a second buried layer of the first conductivity type on the first buried layer, A third buried layer of the second conductivity type is formed on the outer side and a plurality of isolation layers are formed by applying a trench process to reduce the capacitance and improve the maximum allowable surge current Ipp, Voltage can be lowered.

Referring to FIG. 1, the operation principle and circuit diagram of a conventional transient voltage suppressing element are shown.
2 is a flowchart illustrating a method of manufacturing a transient voltage suppressing device according to an embodiment of the present invention.
3A to 3I are sectional views sequentially illustrating a method of manufacturing a transient voltage suppressor according to an embodiment of the present invention.
4 illustrates a transient voltage suppressor according to an embodiment of the present invention and a corresponding equivalent circuit.
5 shows an example of an equivalent circuit of the transient voltage suppressing element according to the embodiment of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

Here, parts having similar configurations and operations throughout the specification are denoted by the same reference numerals. In addition, when a part is electrically connected to another part, it includes not only a direct connection but also a case where the other part is connected to the other part in between.

2 is a flowchart illustrating a method of manufacturing a transient voltage suppressing device according to an embodiment of the present invention. 3A to 3I are sectional views sequentially illustrating a method of manufacturing a transient voltage suppressor according to an embodiment of the present invention.

Referring to FIG. 2, a method of fabricating a transient voltage suppressor according to an exemplary embodiment of the present invention includes forming a first epitaxial layer (S1), a first buried layer (S2), a second epitaxial layer A second epitaxial layer forming step S5, an isolating layer forming step S6, a first and a second conductivity type region forming step S7, and an electrode forming step S4, S8).

3A, in the first epitaxial layer forming step S1, a substrate 110 of a first conductivity type is prepared, a first epitaxial layer 121 is formed on the substrate 110, . The substrate 110 has a plate shape including an upper surface and a lower surface. The substrate 110 may be, for example, an N + + type semiconductor substrate formed by implanting an impurity such as arsenic (As), phosphorus (P), or antimony (Sb), which is a Group 5 element, into the intrinsic semiconductor at high concentration. Here, the high concentration means that the concentration is relatively higher than the impurity concentration of the epitaxial layer 120 to be described later. On the other hand, the substrate 110 of the first conductivity type may be a P-type in which impurity such as gallium (Ga), indium (In), or boron (B), which is a group III element, is implanted into the intrinsic semiconductor at high concentration. However, in the present invention, it is assumed that the substrate 110 is N-type.

For example, the first epitaxial layer 121 may be formed by depositing a gas such as SiH ₄ and a pentavalent element such as arsenic (As), phosphorus (P), or antimony (P) on the upper surface of the substrate 110 at a high temperature of 600 to 2000 ° C. Sb) may be deposited on the surface of the substrate 110 at a low concentration.

As shown in FIG. 3B, a first buried layer 131 of the second conductivity type is formed in the first epitaxial layer 121 in the first buried layer forming step S2. The first buried layer 131 is formed to have a certain depth from the top surface of the first epitaxial layer 121 toward the inside thereof. The first buried layer 131 may be formed by forming an insulating film (not shown) such as a silicon oxide film or a nitrogen oxide film on the upper surface of the first epitaxial layer 121 in a region other than the region where the first buried layer 131 is to be formed , A Group III element such as gallium (Ga), indium (In) or boron (B) may be directly implanted or a thermal diffusion process may be used to form the first buried layer 131 of P + type.

On the other hand, a bottom insulating film may be formed on the bottom surface of the substrate 110. The insulating film may be formed of any one selected from the group consisting of a silicon oxide film, a nitrogen oxide film, undoped polysilicon, Phospho-Silicate-Glass (PSG), Borophosphoric Silicate-Glass (BPSG) However, the present invention is not limited thereto. The insulating layer prevents auto-doping of the first conductive type substrate 110 having a high concentration.

3C, a second epitaxial layer 122 is formed on the first epitaxial layer 121 in the second epitaxial layer forming step S3. For example, at a high temperature of 600 to 2000 ° C., a gas such as SiH ₄ and a pentavalent element such as arsenic (As), phosphorus (P), or antimony (P) are formed on the first epitaxial layer 121 and the first buried layer 131 The second epitaxial layer 122 may be deposited on the first epitaxial layer 121 and the first buried layer 131 by flowing a low concentration of the gases including the first epitaxial layer 121 and the Sb. At this time, the second epitaxial layer 122 is deposited on the surface of the first buried layer 131, and the first buried layer 131 may be further diffused into the second epitaxial layer 122 by doping gases have.

As shown in FIGS. 3D and 3E, the second buried layer 132 of the first conductivity type and the second buried layer 132 of the first conductivity type are formed in the second epitaxial layer 122, A third buried layer 133 of the second conductivity type is formed outside the buried layer 132. The second buried layer 133 of the second conductivity type is formed on the outer side of the second buried layer 132 after the second buried layer 132 of the first conductivity type is formed in the second buried layer formation step S4 . The second buried layer 132 and the third buried layer 133 are formed on the first buried layer 131. The second buried layer 132 is formed to have a certain depth from the upper surface of the second epitaxial layer 122 toward the inside. The third buried layer 133 is formed to have a predetermined depth from the top surface of the second epitaxial layer 122 to the inside thereof and formed in a ring shape outside the second buried layer 132. Therefore, the third buried layer 133 is substantially in the form of a ring connected to each other, but the sectional view thereof seems to be spaced apart from each other as shown in Fig. 3E.

The second buried layer 132 may be formed by forming an insulating film (not shown) such as a silicon oxide film or a nitrogen oxide film on the upper surface of the second epitaxial layer 122 in a region other than the region where the second buried layer 132 is formed Impurities such as arsenic (As), phosphorus (P), and antimony (Sb), which are Group 5 elements, may be directly implanted or a second buried layer 132 of N + type may be formed using a thermal diffusion process. The third buried layer 133 may be formed by forming an insulating film (not shown) such as a silicon oxide film or a nitrogen oxide film on the upper surface of the second epitaxial layer 122 in a region other than the region where the third buried layer 133 is formed, An impurity such as gallium (Ga), indium (In) or boron (B), which is a group III element, can be directly ion-implanted or a third buried layer 133 of P + type can be formed by a thermal diffusion process.

3F, in the third epitaxial layer forming step S5, a third epitaxial layer of the first conductivity type is formed on the second epitaxial layer 122 and the second and third buried layers 132 and 133 A textured layer 123 is formed. For example, at a high temperature of 600 to 2000 ° C., a gas such as SiH ₄ and arsenic (As), phosphorus (P) and the like, which are pentavalent elements, are formed on the second epitaxial layer 122 and the second and third buried layers 132 and 133, ) Or antimony (Sb) are flowed together at a low concentration so that an N-type third epitaxial layer 123 (123) is formed on the second epitaxial layer 122 and the second and third buried layers 132 and 133 Can be deposited. Although not shown in the drawing, the third epitaxial layer 123 is deposited on the surfaces of the second and third buried layers 132 and 133, and the second and third buried layers 132 and 133 are doped with doping gases Can be further diffused into the epitaxial layer 123. As described above, the first, second, and third epitaxial layers 121, 122, and 123 are collectively referred to as an epitaxial layer 120.

The isolation layer 140 is formed from the surface of the third epitaxial layer 123 toward the substrate 110 in the isolation layer formation step S6 as shown in FIG. The isolation layer 140 includes a first isolation layer 141, a second isolation layer 142, a third isolation layer 143 and a fourth isolation layer 144 from the center toward the outside. In the cross-sectional view of FIG. 3G, the isolation layers 140 are spaced apart from each other and a pair of the isolation layers 140 are formed on both sides. However, the isolation layer 140 may have a circular ring shape .

The isolation layer 140 forms a pattern by exposing, for example, a mask (not shown) that primarily determines the position of the isolation layer 140. Then, trenches can be formed through dry etching using mask openings by reactive ion etching. Thereafter, the isolation layer 140 may be formed by implanting an insulating material such as a silicon oxide film or a nitrogen oxide film into the trench. However, the method of forming the isolation layer 140 by this method is not limited.

The first isolation layer 141 is located on the innermost side and has a circular ring shape with an empty center. The first isolation layer 141 is formed from the surface of the third epitaxial layer 123 to the inside of the second buried layer 132.

The second isolation layer 142 has an annular ring shape at the center and is formed outside the first isolation layer 141. The second isolation layer 142 is formed from the surface of the third epitaxial layer 123 to the inside of the second buried layer 132 and the first buried layer 131.

The third isolation layer 143 has an annular ring shape having a center and is formed outside the second isolation layer 142. The third isolation layer 143 is formed from the surface of the third epitaxial layer 123 to the inside of the third buried layer 133 and the first buried layer 131. In addition, the third isolation layer 143 may be formed at a position adjacent to the inside of the third buried layer 133.

The fourth isolation layer 144 has an annular ring shape at the center and is formed outside the third isolation layer 143. The fourth isolation layer 144 is formed from the surface of the third epitaxial layer 123 to the third buried layer 133 and the first buried layer 131. In addition, the fourth isolation layer 144 may be formed at a position adjacent to the outside of the third buried layer 133.

As shown in FIG. 3H, in the first and second conductivity type region formation step S7, the first conductive type region 151 and the second conductive type region 151 are formed inward from the surface of the third epitaxial layer 123, Regions 152 are formed.

More specifically, the first conductive type region 151 is formed between the third isolation layer 143 and the fourth isolation layer 144, and the third epitaxial layer 151, Is formed by implanting ions from the surface of the textured layer 123 inward. The width of the first conductivity type region 151 in the horizontal direction is the same as the width between the third isolation layer 143 and the fourth isolation layer 144. That is, the inner and outer peripheries of the first conductive type region 151 are surrounded by the third isolation layer 143 and the fourth isolation layer 144, respectively. Therefore, the first conductive type region 151 is separated from the third epitaxial layer 123 located inside and outside the first conductive type region 151 by the third and fourth isolation layers 133 and 134 do. That is, the first conductivity type region 151 may be formed in a circular ring shape having a hole at the center thereof. The first conductive type region 151 may be formed by first forming an insulating film such as a silicon oxide film or a nitrogen oxide film or the like and then removing an impurity such as arsenic (As), phosphorus (P), or antimony (Sb) Can be directly ion implanted or a thermal diffusion process can be used to form a first conductivity type region that is N + type.

The second conductive type region 152 may be formed between the first isolation layer 141 and the second isolation layer 142 and may include a third epitaxial layer on the first and second buried layers 131 and 132, And ions are implanted inwardly from the surface of the substrate 123. The width of the second conductivity type region 152 in the horizontal direction is the same as the width between the first isolation layer 141 and the second isolation layer 142. That is, the inner and outer peripheries of the second conductivity type region 152 are surrounded by the first isolation layer 141 and the second isolation layer 142, respectively. Therefore, the second conductive type region 152 is separated from the third epitaxial layer 123 located inside and outside the second conductive type region 152 by the first and second isolation layers 141 and 142 do. That is, the second conductive type region 152 may be formed in a circular ring shape having a hole at the center thereof. In addition, the second conductive type region 152 is located inside the first conductive type region 151. The second conductive type region 152 may be formed by forming an insulating film (not shown) such as a silicon oxide film or a nitrogen oxide film and then directly implanting gallium (Ga), indium (In), or boron (B) Or a second conduction type region 152 of P + type can be formed by using a thermal diffusion process.

3I, in the electrode formation step S8, the electrode 170 is formed on the first and second conductivity type regions 151 and 152. [ Here, the insulating film 160 is formed before the electrode 170 is formed.

The insulating layer 160 includes a first insulating layer 161, a second insulating layer 162, and a third insulating layer 163. The first insulating layer 161 is formed on the third epitaxial layer 123 and the second conductive type region 152 and covers the top of the first isolation layer 141. At this time, the first insulating layer 161 exposes a part of the second conductive type region 152 to the outside. The second insulating layer 162 is spaced apart from the first insulating layer 161 and is formed on the third epitaxial layer 123 and the first and second conductive regions 151 and 152, , 3 isolation layers (142, 143). The second insulating layer 162 exposes a portion of the first and second conductivity type regions 151 and 152 to the outside. The third insulating layer 163 is spaced apart from the second insulating layer 162 and is formed on the third epitaxial layer 123 and the first conductive type region 151. The fourth insulating layer 144, As shown in FIG. The third insulating layer 163 exposes a portion of the first conductive type region 151 to the outside. The insulating layer 160 may be formed of any one selected from the group consisting of a silicon oxide layer, a nitrogen oxide layer, undoped polysilicon, Phospho-Silicate-Glass (PSG), borophosphorosilicate glass However, the present invention is not limited thereto.

The electrodes 170 are formed on the first conductive type region 151 and the second conductive type region 152 exposed to the outside through the insulating layer 160. That is, the electrode 170 is formed to contact both the first conductive type region 151 and the second conductive type region 152. The electrode 170 may be formed by sequentially sputtering or sequentially plating a selected one of molybdenum (Mo), aluminum (Al), nickel (Ni), gold (Au) It does not.

4 illustrates a transient voltage suppressor according to an embodiment of the present invention and a corresponding equivalent circuit. 5 shows an example of an equivalent circuit of the transient voltage suppressing element according to the embodiment of the present invention.

On the other hand, the P-type and N-type junctions of the transient voltage suppressor have characteristics of a diode and a capacitor. That is, although the junctions of the P-type and N-type are shown as diodes in the drawing, they may be represented by capacitors.

4, the transient voltage suppressor according to an exemplary embodiment of the present invention is disposed between the first isolation layer 141 and the second isolation layer 142 and includes a second conductive type region 152 and a second conductive type region 152. [ A third epitaxial layer 123 located between the third isolation layer 143 and the fourth isolation layer 144 and a second diode A and B formed on the junction surface between the second epitaxial layer 123 and the third epitaxial layer 123, The first and second buried layers 131 and 132 are formed on the first and second buried layers 131 and 132 and the second and third buried layers 133 and 133, And a zener diode (E) formed on the surface.

5, the transient voltage suppressor according to an embodiment of the present invention has a structure in which an NPNP type Shockley diode and a PNPN type Shockley diode are connected in parallel. Such a transient voltage suppressing element can realize a bi-directional TVS having a low capacitance. In addition, the transient voltage suppressor according to the present invention can improve the maximum allowable surge current (Ipp) characteristic and realize a low limiting voltage (clamping voltage). For example, the transient voltage suppressor according to the present invention may have a limiting voltage (clamping voltage) of 8V and a maximum allowable surge current (Ipp) of 8A.

As described above, the transient voltage suppressor according to one embodiment of the present invention includes the first buried layer 131 of the second conductivity type and the second buried layer 132 of the first conductivity type on the first buried layer 131 And the third buried layer 133 of the second conductivity type is formed on the outer side of the second buried layer 132 to realize a TVS having a low capacitance, a high Ipp, and a low clamping voltage.

It is to be understood that the present invention is not limited to the above-described embodiment, and various modifications and changes may be made by those skilled in the art without departing from the scope of the present invention. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

110: substrate 120: epitaxial layer
121: first epitaxial layer 122: second epitaxial layer
123: third epitaxial layer 131: first buried layer
132: second buried layer 133: third buried layer
140: Isolation layer 141: First isolation layer
142: second isolation layer 143: third isolation layer
144: fourth isolation layer 151: first conductivity type region
152: second conductivity type region 160: insulating film
170: electrode

Claims (18)

A substrate of a first conductivity type;
A first epitaxial layer of a first conductivity type formed on the substrate;
A first buried layer of a second conductivity type formed in the first epitaxial layer;
A second epitaxial layer of a first conductivity type formed on the first epitaxial layer and the first buried layer;
A second buried layer of a first conductivity type formed inside the second epitaxial layer and formed on an upper portion of the first buried layer; a third buried layer of a second conductivity type formed in the form of a ring outside the second buried layer;
A third epitaxial layer of a first conductivity type formed on top of the second epitaxial layer and the second and third buried layers;
A plurality of isolation layers formed from the surface of the third epitaxial layer toward the substrate;
A first conductive type region and a second conductive type region formed so as to be spaced apart from the surface of the third epitaxial layer inwardly; And
And an electrode formed on a surface of the first conductive type region and the second conductive type region. The method according to claim 1,
Wherein the second buried layer and the third buried layer are in contact with the first buried layer. The method according to claim 1,
Wherein the isolation layer is formed in a circular ring shape,
A second isolation layer formed on the outer side of the first isolation layer, a third isolation layer formed on the outer side of the second isolation layer, and a fourth isolation layer formed on the outer side of the third isolation layer, And wherein the transient voltage suppressing element comprises: The method of claim 3,
The first isolation layer is formed from the surface of the third epitaxial layer to the inside of the second buried layer,
The second isolation layer is formed from the surface of the third epitaxial layer to the inside of the second buried layer and the first buried layer,
The third isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer and the first buried layer,
Wherein the fourth isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer and the first buried layer. 5. The method of claim 4,
Wherein the first conductive type region is formed between the third isolation layer and the fourth isolation layer. 5. The method of claim 4,
And the second conductive type region is formed between the first isolation layer and the second isolation layer. 5. The method of claim 4,
And a first diode is formed on a junction surface of the second conductive type region and the third epitaxial layer. 5. The method of claim 4,
And a second diode is formed between the third isolation layer and the fourth isolation layer at a junction surface between the third epitaxial layer and the third buried layer. 5. The method of claim 4,
Wherein a zener diode is formed on a junction surface between the first and second buried layers on the inner side of the first isolation layer. A first epitaxial layer forming step of forming a first epitaxial layer of a first conductivity type on the substrate of the first conductivity type;
A first embedding layer forming step of forming a first embedding layer of a second conductivity type inside the first epitaxial layer;
A second epitaxial layer forming step of forming a second epitaxial layer of a first conductivity type on the first epitaxial layer and the first buried layer;
Forming a second buried layer of the first conductivity type inside the second epitaxial layer and overlying the first buried layer and forming a ring-shaped third buried layer of the second conductivity type on the outer side of the second buried layer; Forming a second buried layer;
A third epitaxial layer forming step of forming a third epitaxial layer of the first conductivity type on the second epitaxial layer and the second and third buried layers;
Forming a plurality of spaced apart isolation layers from the surface of the third epitaxial layer toward the substrate;
Forming a first conductive type region and a second conductive type region from the surface of the third epitaxial layer toward the substrate and spaced apart from each other; And
And forming an electrode on the surfaces of the first conductive type region and the second conductive type region. 11. The method of claim 10,
Wherein the second buried layer and the third buried layer are formed in contact with the first buried layer in the second buried layer formation step. 11. The method of claim 10,
In the isolation layer formation step, the isolation layer is formed in a circular ring shape,
Wherein the isolation layer comprises a first isolation layer formed at the center, a second isolation layer formed outside the first isolation layer, a third isolation layer formed outside the second isolation layer, and a second isolation layer formed outside the third isolation layer 4 isolating layer. ≪ RTI ID = 0.0 > 5. < / RTI > 13. The method of claim 12,
The first isolation layer is formed from the surface of the third epitaxial layer to the inside of the second buried layer,
The second isolation layer is formed from the surface of the third epitaxial layer to the inside of the second buried layer and the first buried layer,
The third isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer and the first buried layer,
Wherein the fourth isolation layer is formed from the surface of the third epitaxial layer to the inside of the third buried layer and the first buried layer. 14. The method of claim 13,
Wherein the first conductive type region is formed between the third isolation layer and the fourth isolation layer in the first and second conductivity type region formation steps. 14. The method of claim 13,
Wherein the second conductivity type region is formed between the first isolation layer and the second isolation layer in the first and second conductivity type region formation steps. 14. The method of claim 13,
And a first diode is formed on a junction surface of the second conductive type region and the third epitaxial layer. 14. The method of claim 13,
And a second diode is formed between the third isolation layer and the fourth isolation layer, and a junction between the third epitaxial layer and the third buried layer is formed on the junction surface. 14. The method of claim 13,
Wherein a zener diode is formed on a junction surface between the first buried layer and the second buried layer on the inner side of the first isolation layer.

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