KR20170075423A - Resistor element and board having the same mounted thereon - Google Patents

Abstract

A resistive element according to an embodiment of the present invention includes a base substrate; A resistive layer disposed on one surface of the base substrate; First and second terminals arranged to be separated from each other on the resistive layer and connected to the resistive layer; And a third terminal disposed between the first and second terminals, the third terminal having a first surface in contact with the resistive layer and a second surface having a width less than the width of the first surface.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistive element,

The present invention relates to a resistive element and a mounting substrate thereof.

The chip-shaped resistive element is suitable for realizing a precision resistor, and it can serve to regulate the current in the circuit and to drop the voltage.

In a circuit design using a resistor, if a resistor is damaged by external shock (surge, static electricity, etc.) and a fault (short circuit) occurs, all the current of the power supply flows to the IC, have.

In order to prevent such a phenomenon, a circuit may be designed by using a plurality of resistors when designing a circuit. However, such a circuit design has a problem in that the space use of the substrate is inevitably increased.

Particularly, in the case of a mobile device which is getting smaller and more precise, it is not desirable to increase the space usage of the substrate for the stability of the circuit as described above. Therefore, it is necessary to study the resistance element which can control the current flowing in the circuit more effectively It is true.

U.S. Published Patent Application No. 2010-0117783

According to an embodiment of the present invention, a resistive element and a mounting substrate thereof, which are excellent in space efficiency and capable of stable connection with a printed circuit board, can be provided.

A resistive element according to an embodiment of the present invention includes a base substrate; A resistive layer disposed on one side of the base; First and second terminals arranged to be separated from each other on the resistive layer and connected to the resistive layer; And a third terminal disposed between the first and second terminals, the third terminal having a first surface in contact with the resistive layer and a second surface having a width less than the width of the first surface.

According to another aspect of the present invention, there is provided a resistance element mounting board comprising: a printed circuit board having a plurality of electrode pads on an upper surface thereof; And a resistive element disposed on the printed circuit board, wherein the resistive element comprises a base substrate, a resistive layer disposed on one side of the base, first and second resistive elements arranged to be separated from each other on the resistive layer, And a third terminal disposed between the first and second terminals and having a first surface in contact with the resistive layer and a second surface having a width less than the width of the first surface.

The resistive element according to an embodiment of the present invention has an excellent space efficiency when mounting a substrate, and has a stable connection with a printed circuit board.

1 is a perspective view showing a resistance element according to an embodiment of the present invention.
2 is a cross-sectional view taken along the line I-I 'in Fig.
3 is a cross-sectional view showing a resistance element according to another embodiment of the present invention.
4 is a perspective view showing a mounting substrate of a resistance element according to an embodiment of the present invention.
5 is a sectional view of II-II 'of FIG.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the following embodiments. Further, the embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive.

FIG. 1 is a perspective view showing a resistance element according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line I-I 'of FIG.

1 and 2, the resistance device 100 according to an embodiment of the present invention includes a base substrate 110, a resistance layer 120, and first to third terminals 131, 132, and 133 do.

The base substrate 110 is for supporting the resistance layer 120 and securing the strength of the resistance element 100, and is not particularly limited. For example, an aluminum substrate or an insulating substrate may be used.

Although not limited thereto, the base substrate 110 may have a predetermined thickness and may have a thin plate shape having a rectangular shape on one side, and the surface may be formed of an insulated alumina material by anodizing .

In addition, since the base substrate 110 is formed of a material having a good thermal conductivity, it can serve as a heat diffusion path for dissipating the heat generated in the resistance layer 120 to the outside when the resistance element is used.

The resistive layer 120 is disposed on one side of the base substrate. The resistor layer 120 may be connected to the first to third terminals 131, 132 and 133 to form a predetermined resistance between the first to third terminals 131, 132 and 133.

The resistor layer 120 is connected to the first and third terminals 131 and 133 and is connected to the first resistor layer and the second and third terminals 132 and 133, And a second resistor layer forming a resistor.

For example, the resistive layer 120 can be resisted by trimming. Trimming refers to a process such as cutting for fine adjustment of a resistance value, and may be a process of determining a resistance value set in each resistance portion when designing a circuit.

The resistance layer 120 may include Ag, Pd, Cu, Ni, Cu-Ni alloy, Ni-Cr alloy, Ru oxide, Si oxide, Mn and Mn alloy And may include various materials depending on the required resistance value.

The first to third terminals 131, 132, and 133 are disposed to be separated from each other on the first surface of the base substrate 110. The width W3 'of the first surface is greater than the width W3' of the second surface. The width W3 'of the first surface is greater than the width W3' of the second surface. (For example, a cross-sectional shape in the form of a trapezoid).

The widths W4 and W5 of the resistive layer exposed between the first to third terminals 131, 132 and 133 are equal to or greater than the width W3 'of the first surface, (W3 ") of the second surface with respect to the first surface (W3 ') may be 0.4 or more and less than 1.

The widths W4 and W5 of the resistive layer exposed between the first to third terminals 131 and 132 and 133 are smaller than the width W3 'of the first surface and the width W3 ) Of the second surface to the width W3 "of the second surface may be 0.4 or more and 0.9 or less.

Here, the base substrate 110 has a rectangular parallelepiped shape, and the width W3 'of the first surface and the width W3''of the second surface may be the width of the length direction L of the rectangular parallelepiped.

Table 1 below shows the relationship between the width W3 'of the first surface and the width W3' of the second surface with respect to the width W3 ' Data of Experimental Example 1 tested.

Unit (Lot) W3 ' W3 " W3 "/ W3'ratio result One 0.08 mm 0.008 mm 0.1 fail 2 0.08 mm 0.016 mm 0.2 fail 3 0.08 mm 0.028 mm 0.35 fail 4 0.08 mm 0.032 mm 0.4 pass 5 0.08 mm 0.036 mm 0.45 pass 6 0.08 mm 0.040 mm 0.5 pass 7 0.08 mm 0.048 mm 0.6 pass 8 0.08 mm 0.056 mm 0.7 pass 9 0.08 mm 0.064 mm 0.8 pass 10 0.08 mm 0.072㎜ 0.9 pass 11 0.08 mm 0.076 mm 0.95 pass 12 0.08 mm 0.080 mm One pass

In Experimental Example 1, the widths W4 and W5 of the resistive layer exposed between the first to third terminals 131, 132 and 133 are equal to or greater than the width W3 'of the first surface, Was tested under the condition that the width W3 'of the first surface of the third terminal 133 was fixed to 0.08 mm and the width W3 "of the second surface of the third terminal 133 was changed As a result, 1000 resistance elements were manufactured and tested for each lot in Table 1. In the case where one or more defects occurred in each unit, the result was shown as failure. Referring to Table 1, If W3 "/ W3 'ratio is less than 0.4, it can be confirmed that a defect has occurred.

That is, if the W3 '' / W3 'ratio is excessively small, the height of the third terminal 133 may not be formed to a predetermined height after the plating process. So that a so-called cold solder joint phenomenon may appear, which appears to be apparently bonded but not actually bonded.

Table 2 below shows the relationship between the width W3 'of the second surface and the width W3' / W3 'ratio of the second surface with respect to the width W3' of the first surface under conditions different from those of Experimental Example 1, This is the data of Experimental Example 2 in which it is tested whether the mounted state of the device is appropriate.

Unit (Lot) W3 ' W3 " W3 "/ W3'ratio result One 0.08 mm 0.008 mm 0.1 fail 2 0.08 mm 0.016 mm 0.2 fail 3 0.08 mm 0.028 mm 0.35 fail 4 0.08 mm 0.032 mm 0.4 pass 5 0.08 mm 0.036 mm 0.45 pass 6 0.08 mm 0.040 mm 0.5 pass 7 0.08 mm 0.048 mm 0.6 pass 8 0.08 mm 0.056 mm 0.7 pass 9 0.08 mm 0.064 mm 0.8 pass 10 0.08 mm 0.072㎜ 0.9 pass 11 0.08 mm 0.076 mm 0.95 fail 12 0.08 mm 0.080 mm One fail

In Experimental Example 2, the widths W4 and W5 of the resistive layer exposed between the first to third terminals 131, 132 and 133 are smaller than the width W3 'of the first surface, The width W3 'of the first surface of the third terminal 133 is fixed to 0.08 mm and the width W3' 'of the second surface of the third terminal 133 is changed, , And 1000 resistance elements per lot are manufactured and tested as shown in Table 1. In the case where one or more defects occurred in each unit, the result is shown as failure. W3 "/ W3 'ratio is out of the range of 0.4 to 0.9, it can be confirmed that a defect has occurred.

That is, if the W3 '' / W3 'ratio is excessively small as in the case of Experimental Example 1, the soldering may be excessive in the soldering process. A so-called solder in excess phenomenon may occur, which is a problem that solder is formed at an unnecessary portion around the electrode pad. The solder formed by such overcharge causes a short circuit between the electrode pads, which causes malfunction and overcurrent.

Although not shown in the drawing, the third terminal 133 may have a first surface contacting the resistance layer 120 and a second surface having a length smaller than the length of the first surface.

For example, the longitudinal direction of the third terminal 133 (that is, the width direction W of the resistance element) may have a trapezoidal shape.

The first to third terminals 131, 132, and 133 may include first to third electrode layers 131a, 132a, and 133a that are separated from each other on one surface of the base substrate 110, 132b, and 133b covering the first to third electrode layers 131a, 132a, and 133a, respectively.

2, the first terminal 131 includes a first electrode layer 131a and a first plating layer 131b, and the second terminal 132 includes a second electrode layer 132a and a second electrode layer 132b. 2 plating layer 132b and the third terminal 133 may include a third electrode layer 133a and a third plating layer 133b.

As shown in FIG. 2, the third electrode layer 133a may have a width larger than the width of the upper side in contact with the resistance layer 120, which is larger than a width of the lower side facing the upper side. Accordingly, the third terminal 133 including the third electrode layer 133a and the third plating layer 133b covering the surface of the third electrode layer 133a may have a trapezoidal cross section.

Although not limited thereto, the first to third electrode layers 131a, 132a, and 133a may be formed by applying a conductive paste for forming a conductive electrode on the resistive layer 120 and the base substrate 110 And a method such as screen printing may be used as a coating method.

The first, second, and third electrode layers 131a, 132a, and 133a may be formed of a material different from that of the resistance layer 120. For example, copper, nickel, and platinum may be used. Components such as the resistive layer 120 may be used.

The first and second backside electrodes 131d and 132d may be disposed on the other side of the base substrate 110 opposite to the first and second electrode layers 131a and 132a. When the first and second backside electrodes 131d and 132d are disposed on the other surface of the base substrate 110 as described above, the first and second electrode layers 131a and 132a and the first and second backside electrodes 131d and 131d And 132d can cancel the force applied to the base substrate 110 by the resistive layer 120 in the firing process, thereby preventing the base substrate from being bent by the resistive layer 120. [

Although not limited thereto, the first and second backside electrodes 131d and 132d may be formed by printing a conductive paste.

The first and second electrode layers 131a and 132a are formed on both end faces of the laminate having the base substrate 110, the resistance layer 120, and the first to third electrode layers 131a, 132a, and 133a. The first and second side electrodes 131c and 132c may be selectively arranged.

That is, the first side electrode is connected to the first electrode layer 131a and the first back electrode 132d, the second side electrode 132c is connected to the second electrode layer 132a and the second back electrode 132d, As shown in FIG.

The first and second side electrodes 131c and 132c may be formed by sputtering a conductive material that forms the side electrodes 131c and 132c on the end surface of the laminate. However, the present invention is not limited thereto.

A protection layer 140 for protecting the resistance layer 120 from external impact may be disposed on the surface of the resistance layer 120 where the first to third electrode layers 131a, 132a, and 133a are not disposed.

Although not limited thereto, the protective layer 140 may be formed of silicon (SiO ₂ ) or glass, and may be formed on the resistance layer 120 by overcoating.

The first through third terminals 131, 132, and 133 may protrude from the protective layer 140 even if the protective layer 140 is disposed on the resistance layer 120, Contact between the third terminals 131, 132, and 133 and the electrode pads disposed on the substrate can be facilitated.

After the protective layer 140 is formed, first to third plating layers 131b, 132b, and 133b are formed on the first to third electrode layers 131a, 132a, and 133a, respectively, .

When the resistance element 100 includes the first and second backside electrodes 131d and 132d and the first and second side electrodes 131c and 132c, (131b, 132b) may be formed.

For example, the first plating layer 131b may be formed to cover the first electrode layer 131a, the first back electrode 131d, and the side electrode 131c connecting the first electrode layer and the first back electrode. And the second plating layer 132b may cover the second electrode layer 132a, the second backside electrode 132d and the side electrode 132c connecting the second electrode layer and the second backside electrode. Although not limited thereto, the first to third plating layers 131b, 132b, and 133b may be formed by a barrel plating method.

Since the resistance element according to an embodiment of the present invention includes the first to third terminals 131, 132, and 133, the mounting strength is improved at the time of substrate mounting and stable connection with the printed circuit board is possible. Since the resistance of the third terminal 133 is smaller than the width of the first surface of the resistor 133, it is possible to prevent solder in excess or cold solder joint during substrate mounting. Effect.

3 is a cross-sectional view showing a resistance element according to another embodiment of the present invention. Referring to FIG. 3, the resistance element 100 'according to the embodiment in which the first to third terminals 131, 132, and 133 are deformed can be identified as compared with the resistance element 100 shown in FIG. 2 .

The thickness t2 of the third electrode layer 133a may be greater than the thickness t1 of the first and second electrode layers 131a and 132a and the thickness t2 of the third plating layer 133b may be greater than the thickness t1 of the first and second electrode layers 131a and 132a, The target t4 may be formed to be thinner than the thickness t3 of the first and second plating layers 131b and 132b.

For example, since the plating layers 131b, 132b, and 133b can be formed by the barrel plating method, the third electrode layer 133a is less likely to be energized due to contact with the first and second electrode layers 131a and 132a Plating of the third electrode layer 133a is mainly performed by energization through the resistive layer. Generally, since the resistance layer has a lower conductivity than the electrode layer, the thickness of the third electrode layer 133a may be thinner than that of the first and second electrode layers 131a and 132a.

As shown in FIG. 3, by forming the third electrode layer 133a to be thick, the entire thicknesses of the first to third terminals 131, 132, and 133 including the electrode layer and the plating layer can be uniformly formed.

The third electrode layer 133a is formed of at least two layers including an upper electrode layer 133a 'disposed on the lower electrode layer 133a "and the lower electrode layer 133a" and in contact with the resistance layer 120 .

The width W7 of the upper electrode layer 133a 'may be greater than the width W8 of the lower electrode layer 133a. That is, the third electrode layer 133a may have a plurality of Layer.

When the third electrode layer 133a including the upper electrode layer 133a 'and the lower electrode layer 133a is subjected to a plating process to cover the third plating layer 133b, the third terminal 133 may have a trapezoidal cross section have.

Other configurations and functions can be understood from the resistance element 100 described with reference to Fig. 1 and Fig. 2, and thus redundant description will be omitted.

FIG. 4 is a perspective view showing a mounting substrate of a resistance device according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view of II-II 'of FIG.

4 and 5, a mounting substrate 10 of a resistive element according to an embodiment of the present invention includes a printed circuit board 11 having a plurality of electrode pads and resistive elements 100 ' .

The resistance element includes a base substrate 110, a resistance layer 120 disposed on one side of the base substrate, and a first and a second terminal 120, which are disposed to be separated from each other on the resistance layer 120, (131, 132).

A third terminal 131 is disposed between the first and second terminals 131 and 132 and has a first surface contacting the resistance layer 120 and a second surface having a width smaller than the width of the first surface. (133).

Since the resistance element 100 'can be understood from the resistance element described with reference to FIGS. 1 to 3, a duplicate description will be omitted.

The printed circuit board 11 is a portion in which an electronic circuit is formed. An integrated circuit (IC) or the like for specific operation or control of the electronic apparatus is formed, and a current supplied from a separate power source can flow.

In this case, the printed circuit board 11 may include various wiring lines or may further include other kinds of semiconductor elements such as transistors and the like. In addition, the printed circuit board 11 may include a conductive layer, a dielectric layer, or the like.

The first to third electrode pads 12, 13 and 14 are disposed on the printed circuit board 11 so as to be spaced apart from each other and are connected to the first to third terminals 131, 132, and 133, respectively.

4 and 5, the first electrode pad 12 is connected to the first terminal 131 and the second electrode pad 13 is connected to the second terminal 132. However, according to the design, The pad 12 may be connected to the second terminal 132 and the second electrode pad 13 may be connected to the first terminal 131.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, and that various changes and modifications may be made therein without departing from the scope of the invention. It will be obvious to those of ordinary skill in the art.

100, 100 ': Resistance element
110: base substrate
120: resistance layer
131, 132, 133: first to third terminals
140: Protective layer
10: Resistor element mounting substrate
11: printed circuit board
12, 13 and 14: first to third electrode pads
15: Solder

Claims (15)

A base substrate;
A resistive layer disposed on one surface of the base substrate;
First and second terminals arranged to be separated from each other on the resistive layer and connected to the resistive layer; And
A third terminal disposed between the first and second terminals, the third terminal having a first surface in contact with the resistive layer and a second surface having a width smaller than the width of the first surface,
≪ / RTI >
The method according to claim 1,
Wherein a width of the resistive layer exposed between the first to third terminals is equal to or greater than a width of the first surface and a ratio of a width of the second surface to a width of the first surface is 0.4 or more and less than 1 device.
The method according to claim 1,
Wherein the width of the resistive layer exposed between the first to third terminals is smaller than the width of the first surface and the ratio of the width of the second surface to the width of the first surface is 0.4 or more and 0.9 or less.
The method according to claim 1,
Each of the first to third terminals
First to third electrode layers disposed on the resistance layer; And
The first to third plating layers covering the first to third electrode layers
≪ / RTI >
5. The method of claim 4,
Wherein the third electrode layer is thicker than the first and second electrode layers, and the third plating layer is thinner than the first and second plating layers.
5. The method of claim 4,
Wherein the third electrode layer is formed of at least two layers including a lower electrode layer and an upper electrode layer disposed on the lower electrode layer and in contact with the resistance layer.
The method of claim 6, wherein
Wherein a width of the upper electrode layer is larger than a width of the lower electrode layer.
The method according to claim 1,
And a protective layer disposed on the resistive layer between the first to third terminals.
The method according to claim 1,
Wherein the base substrate has a rectangular parallelepiped shape,
Wherein the width of the first surface and the width of the second surface are the width in the longitudinal direction of the rectangular parallelepiped.
A printed circuit board having a plurality of electrode pads; And
And a resistance element disposed on the printed circuit board,
The resistance element includes a base substrate, a resistive layer disposed on one side of the base substrate, first and second terminals arranged to be separated from each other on the resistive layer, the first and second terminals being connected to the resistive layer, And a third terminal having a first surface in contact with the resistance layer and a second surface having a width smaller than the width of the first surface,
And the resistor element mounting substrate.
11. The method of claim 10,
Wherein a width of the resistive layer exposed between the first to third terminals is equal to or greater than a width of the first surface and a ratio of a width of the second surface to a width of the first surface is 0.4 or more and less than 1 Element mounting substrate.
11. The method of claim 10,
Wherein a width of the resistive layer exposed between the first to third terminals is smaller than a width of the first surface and a ratio of a width of the second surface to a width of the first surface is 0.4 or more and 0.9 or less, Board.
11. The method of claim 10,
And the third terminal includes a lower electrode layer and at least two layers disposed on the lower electrode layer and including an upper electrode layer in contact with the resistance layer.
11. The method of claim 10,
And a protective layer disposed on the resistive layer between the first to third terminals.
11. The method of claim 10,
Wherein the base substrate has a rectangular parallelepiped shape,
Wherein the width of the first surface and the width of the second surface are the width in the longitudinal direction of the rectangular parallelepiped.

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