KR20170050521A

KR20170050521A - Display device and driving method thereof

Info

Publication number: KR20170050521A
Application number: KR1020150152153A
Authority: KR
Inventors: 김동수; 유상희
Original assignee: 엘지디스플레이 주식회사
Priority date: 2015-10-30
Filing date: 2015-10-30
Publication date: 2017-05-11

Abstract

More particularly, the present invention relates to a display panel having a display area and a non-display area, a display panel formed in the non-display area, and a gate signal is applied to the display panel using a plurality of switch circuits A power supply generating unit for supplying a threshold voltage shift control voltage that is involved in a threshold voltage shift of the plurality of circuit switches, and a plurality of shift registers which are located on the plurality of circuit switches and minimize an erroneous operation of the shift register And Shield Patterns.

Description

DISPLAY DEVICE AND DRIVING METHOD THEREOF [0002]

The present invention relates to a display device and a driving method thereof, and more particularly to a display device using a GIP (gate drive IC in panel) method in which a gate drive integrated circuit is directly formed on a display panel and a driving method thereof.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Accordingly, a variety of flat panel displays (FPDs) have been developed and marketed to reduce weight and volume, which are disadvantages of cathode ray tubes. For example, various flat panel display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED) .

The display device displays an image using a gate drive circuit for supplying a scan signal to the gate lines of the display panel and a data drive circuit for supplying a data voltage to the data lines. The gate driving circuit may be a TAB (Tape Automated Bonding) method in which a printed circuit board on which a plurality of gate drive integrated circuits are mounted is attached to a display panel, or a gate drive integrated circuit is formed directly on a display panel (Gate Drive IC in Panel) method. Since the GIP method can reduce the external beauty of the display device as compared with the TAB method, it is possible to reduce the cost, and it is possible to reduce the number of the scan signals for compensating the threshold voltage of the driving TFT (Thin Film Transistor) The display panel maker can directly design them. Therefore, recently, the gate drive circuit is formed by the GIP method rather than the TAB method.

In a panel of a general flat panel display (hereinafter, simply referred to as a "display device"), a gate drive circuit is formed on the panel in a GIP system. Therefore, for example, when the source drive IC is in the non-display area of the upper part, gate transmission lines for transmitting driving signals to the gate driving circuit and the gate driving circuit are formed in the non-display area of the panel.

Such a gate driving circuit includes a gate shift register for sequentially supplying scan pulses to a plurality of gate lines.

The shift register of the scan driver circuit has stages including a plurality of thin film transistors. The stages are connected in a cascade to generate the output signal sequentially.

Fig. 1 is a diagram showing a circuit configuration of each stage of a conventional shift register, specifically showing a circuit configuration of a stage driven in three phases. 1 shows a circuit configuration of a conventional stage composed of N-type TFTs, the circuit of the stage composed of P-type TFTs may be constructed in the same structure as in FIG. 1 and driven by the same method. That is, the stage shown in FIG. 1 is driven by three phases (2Phase) and includes a plurality of input signals and a plurality of switch circuits for receiving a CLK signal and outputting a gate pulse.

More specifically, assuming that the stage shown in FIG. 1 is Stage 1, the operation of Stage 1 will be described step by step with reference to FIG.

In the stage 1, a switch T2 for receiving a carry signal input from a previous stage, a switch T4 for initializing, a switch terminal T1 for starting the stage 1, A switch T6 involved in discharging the output voltage of the stage 1 (Stage 1), a switch T6 participating in the output voltage Vout of the stage 1 (Stage 1), an output voltage Vout of the stage 1 (Bootstrapping Capacitance and Q_node) involved in raising the voltage across the Q-node (not shown), the queue-node (Q_node) connected to the gate terminal controlling the off- And a switch T3 that is involved in discharging and the like. Stage 1 is initialized in response to a signal input to the initialization switch T4. To the start signal VST input to the switch T1 involved in the Node Q_node by bootstrapping in response to a clock signal input to a switch T6 that participates in the output voltage Vout of Stage 1 (Stage 1) is connected to the switch T6 and the gate voltage of the Q-node is increased by the voltage of the Q-node (Q_node) And outputs a scan pulse having the same pulse as the input clock through the output terminal G_OUT.

That is, the driving circuit including the shift register as described above applies the start signal VST and the clocks CLK to the stage 1 and outputs the output signal Output corresponding thereto, Is a circuit that seeks for a shift effect of an output signal by applying it again to the driving circuit of the stage 2 (Stage 2).

On the other hand, a leakage current remains in the shift register, and the shift register may malfunction even in the initialization state of the drive circuit. That is, a voltage is applied to the switch of the shift register at the threshold voltage (VTH) or more, and the switch is turned on and operated. Therefore, the shift register operates in the initialized state, and an error may occur that the output signal is transmitted to the gate line of the panel due to the operation. It is necessary to improve the reliability of the display device due to such an error and to minimize the power consumption due to erroneous operation of the shift register.

The inventors of the present invention invented a new structure and a manufacturing method of a display device for preventing erroneous operation of a shift register.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a gate driving circuit in which a shift register does not malfunction by controlling movement of a threshold voltage VTH of switch circuits constituting a shift register of a GIP A display device is provided.

Other features and advantages of the invention will be set forth in the description which follows, or may be obvious to those skilled in the art from the description and the claims.

A display device according to an embodiment of the present invention includes: a display panel having a display region and a non-display region; A shift register formed in the non-display region and sequentially outputting a gate signal to the display panel using a plurality of switch circuits; A power generator for supplying a threshold voltage shift control voltage that is involved in a threshold voltage shift of the plurality of circuit switches; And a plurality of shield patterns positioned on the plurality of circuit switches to minimize an erroneous operation of the shift register.

A display device according to an embodiment of the present invention is a GIP (Gate In Panel) driving circuit including a plurality of driving switches, wherein the plurality of driving switches are turned on during a first period before the GIP driving circuit operates, The threshold voltage is shifted in one direction and the threshold voltage of the plurality of driving switches is shifted in a direction opposite to the one direction during the second period after the GIP driving circuit operates for a predetermined period.

There is provided an advantage of providing a gate driving circuit in which a shift register does not malfunction by controlling shift of a threshold voltage (VTH) of a switch constituting a shift register of a GIP (gate in panel) according to an embodiment of the present invention and a display device using the same have.

1 is an exemplary view showing a circuit configuration of a first stage (Stage 1) of a conventional shift register.
2 is a block diagram schematically showing a display device according to an embodiment of the present invention;
3 is a waveform diagram schematically illustrating an output voltage of a power generation unit according to an embodiment of the present invention.
4 is an exemplary view showing a change in threshold voltage in a shift register according to an embodiment of the present invention.
5 is a block diagram of a shift register according to the present invention;
6 is an exemplary diagram showing a circuit configuration of the N-th stage (Stage n) shown in FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

A display device according to an embodiment of the present invention may include any display device that sequentially supplies gate pulses (or scan pulses) to gate lines (or scan lines) to write digital video data to pixels by line sequential scanning have. For example, a display device according to an embodiment of the present invention may include a liquid crystal display (LCD), an organic light emitting diode (OLED), a field emission display (FED) , And an electrophoresis display (EPD). While the present invention has been described with reference to the case where a display device is implemented by a liquid crystal display device in the following embodiments, it should be noted that the display device of the present invention is not limited to a liquid crystal display device. The liquid crystal display device can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device.

2 is a block diagram schematically showing a display device according to an embodiment of the present invention. Referring to FIG. 2, the display device of the present invention includes a display panel 110, a data driving circuit 120, a level shifter 150, a shift register 130, a timing controller 160, a shield pattern 131 and a power generating unit 140.

In the display panel 110, a liquid crystal layer is formed between two substrates. The lower substrate of the display panel 110 is connected to data lines, gate lines intersecting the data lines, TFTs formed at intersections of the data lines and the gate lines, TFTs connected to the TFTs by an electric field between the pixel electrodes and the common electrodes A liquid crystal cell to be driven, and a TFT array including a storage capacitor are formed. On the upper substrate of the display panel 110, a color filter array including a black matrix and a color filter is formed. The liquid crystal display according to the exemplary embodiment of the present invention may be implemented in a liquid crystal mode such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode or FFS (Fringe Field Switching) mode. The common electrode may be formed on the upper substrate in a vertical electric field driving mode such as a TN mode and a VA mode, and may be formed on a lower substrate together with the pixel electrode in a horizontal electric field driving mode such as an IPS mode and an FFS mode. On the upper substrate and the lower substrate of the display panel 110, a polarizing plate whose optical axis is orthogonal is attached, and an alignment film for setting a pre-tilt angle of liquid crystal is formed at an interface with the liquid crystal layer.

The data driver circuit includes a plurality of fractional drive ICs 120. The source drive ICs 120 receive digital video data RGB from the timing controller 160. The minority drive ICs 120 convert the digital video data RGB to a gamma compensation voltage in response to a source timing control signal DCS from the timing controller 160 to generate a data voltage, To the data lines of the display panel 100 in synchronization with the gate pulse. The minority drive ICs 120 may be connected to the data lines of the display panel 110 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The GIP type gate driving circuit includes a level shifter 150 mounted on a PCB (not shown) and a shift register 130 formed on a lower substrate of the display panel 110.

A timing controller 160, a level shifter 150, and a voltage generator 140 are mounted on a PCB (not shown).

The level shifter 150 outputs a TTL (Transistor-Transistor-Logic) logic level voltage of i (i is a natural number of 2 or more) upper gate shift clocks (CLK1 to CLKi) input from the timing controller 160 to a gate high voltage VGH) and the gate-low voltage (VGL). The level-shifted clocks (CLK1 to CLKi) are input to the shift register (130).

The level shifter 150 receives the first clock GCLK and the second clock MCLK from the timing controller 160. The level shifter 150 receives the drive voltage such as the gate high voltage VGH and the gate low voltage VGL from the voltage generator 140. The first clock GCLK and the second clock MCLK swing between 0V and 3.3V. The gate high voltage VGH is a voltage equal to or higher than the threshold voltage VTH of the TFT formed in the TFT array of the display panel 100 and is about 14 V and the gate low voltage VGL is applied to the TFT array of the display panel 110 Which is lower than the threshold voltage VTH of the formed TFT, is a voltage of approximately -12V.

The level shifter 150 is connected between the gate high voltage VGH and the gate low voltage VGL in response to the first clock GCLK and the second clock MCLK input from the timing controller 160, And outputs the clock signals CLK1 to CLK4 that swing. The clock signals CLK output from the level shifter 150 are sequentially shifted in phase and transferred to the shift register 130 formed on the display panel 10. [

The shift register 130 is connected to the gate lines of the display panel 110 and sequentially outputs gate pulses to the gate lines. The shift register 130 is formed directly on the lower substrate of the display panel 110 in a GIP (Gate Drive-IC In Panel) manner. In the GIP scheme, the level shifter 150 is mounted on a printed circuit board (not shown).

The shift register 130 includes a plurality of stages ST1 to STn which are connected in a dependent manner. In the shift register 130, the clock signals CLK input from the level shifter 150 are shifted to sequentially supply gate pulses Gout to the gate lines.

An oxide thin film transistor Oxide-TFT having an active layer composed of an oxide semiconductor material has a good advantage over an amorphous silicon thin film transistor (a-Si TFT) in terms of current mobility and off current. In addition, the oxide thin film transistor (Oxide-TFT) is excellent in the change of the current density of the active layer when an external electric field is applied, and the phenomenon that the threshold voltage (VTH) of the oxide thin film transistor have.

Each stage of the shift register 130 uses an oxide thin film transistor (Oxide-TFT) having such characteristics as a switch. As a result, the erroneous operation occurring before the initialization of the shift register 130 can be prevented by appropriately shifting the threshold voltage VTH of the oxide thin film transistor (Oxide-TFT).

Specifically, the shift register 130 forms a shield pattern 131 on an oxide thin film transistor (Oxide-TFT) constituting each stage. Then, a voltage is applied to the shield pattern 131 to change the current density in the active layer of the oxide-TFT (oxide-TFT). Then, the threshold voltage VTH of the oxide thin film transistor (Oxide-TFT) can be moved in a desired direction. Each of the shield patterns 131 is electrically connected to each other. The shield pattern 131 is formed on the shift register 130 at the same time when the common electrode of the display panel 110 is formed. The shift register 130 of the present invention will be described later in detail with reference to FIG.

The power supply unit 140 starts to operate when the input voltage supplied from the host system is equal to or higher than the UVLO level, and generates an output after a predetermined time delay. The output of the power supply 140 includes VGH, VGL, VSS, VDD, HVDD, VST, VCO, and the like. VCC may be a voltage of 3.3 V as a logic power supply voltage for driving the timing controller 160, the source drive ICs 120, and the like. VDD and HVDD are the high potential supply voltage and the 1/2 high potential supply voltage to be supplied to the voltage dividing circuit of the gamma reference voltage generating circuit that generates the positive / negative gamma reference voltages. The positive / negative gamma reference voltages are supplied to the source drive ICs 120. RST is a reset signal for resetting the timing controller 160, and may be 3.3V.

The power supply unit 140 supplies a common voltage VCOM to the common electrode formed on the substrate of the display panel 110 in displaying an image on the display panel 110. [

The power supply unit 140 supplies power necessary for operating the data driving circuit and the gate driving circuit, that is, the high potential power supply (VDD), the low potential power supply (VSS), and the like. The power supply unit 140 supplies the gate high voltage VGH and the gate low voltage VGL to the level shifter 150 in response to the first clock GCLK and the second clock MCLK input from the timing controller 160 Supply.

In order to control the shift of the threshold voltage VTH of the oxide-TFT of the shift register 130, the power supply 140 supplies a threshold voltage shift control voltage VSC before the shift register is operated, To the shield pattern 131 of the shift register 130.

The threshold voltage shift control voltage VSC may be a voltage controlling the movement of the threshold voltage VTH of the oxide thin film transistor (Oxide-TFT) of the shift register 130 as a voltage of 14V or -12V.

The timing controller 160 receives digital video data (RGB) from an external host system through an interface such as a Low Voltage Differential Signaling (LVDS) interface and a Transition Minimized Differential Signaling (TMDS) interface. The timing controller 160 transmits the digital video data (RGB) input from the host system to the source drive ICs 120. The timing controller 160 receives the vertical synchronizing signal Vsync, the horizontal synchronizing signal Hsync, the data enable signal DE and the main clock MCLK from the host system through the LVDS or TMDS interface receiving circuit As shown in FIG. The timing controller 160 generates timing control signals for controlling the operation timing of the data driving circuit and the gate driving circuit based on the timing signal from the host system. The timing control signals include a gate timing control signal (GCS) for controlling the operation timing of the gate drive circuit, a data timing control signal (DCS) for controlling the operation timing of the source drive ICs 120 and the polarity of the data voltage .

The gate timing control signal includes a start pulse ST, a first clock GCLK, and a second clock MCLK.

The start pulse ST is input to the shift register 130 with the start voltage VST. The first clock GCLK increases the clock signals CLK1 through CLK4 to be supplied to the shift register 30 at the time of rising and the first clock GCLK amplifies the clock signals CLK1 through CLK4 each time the first clock GCLK is input. (CLK1 to CLK4). Each of the clock signals CLK1 to CLK4 swings between the gate high voltage VGH and the gate low voltage VGL.

The data timing control signal DCS includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal, and a source output enable signal (Source Output Enable) . The source start pulse SSP controls the shift start timing of the source drive ICs 120. [ The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source drive ICs 120 based on the rising or falling edge. The polarity control signal controls the polarity of the data voltage output from the source drive ICs 120. [ If the data transfer interface between the timing controller 160 and the source drive ICs 120 is a mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted.

3 is a waveform diagram schematically illustrating an output voltage of the power generating unit according to the embodiment of the present invention.

Referring to FIG. 3, the power supply unit 140 sequentially outputs voltages required for driving the liquid crystal display according to a preset power-on sequence. The power supply 140 starts to operate when the input voltage reaches the UVLO level when the input voltage rises, and generates the enable signal EN after the first delay time DLY0. The power supply unit 140 outputs RST after the enable signal EN is delayed by the second delay time DLY1 after generating the VCC. The power supply unit 140 generates VGL after RST and outputs VDD and HVDD after VGL and after the third delay time DLY2. Power supply 140 outputs VGH after VDD and HVDD and after fourth delay time DLY3. Finally, the power supply unit 140 outputs the threshold voltage shift control voltage VSC after the fifth delay time DLY4, following the VGH.

FIG. 4 is a diagram illustrating a change in the threshold voltage VTH in the shift register according to the embodiment of the present invention.

The shift register 130 of the GIP gate drive circuit composed of an oxide thin film transistor (Oxide-TFT) can remain in the drive circuit before the shift register 130, so that the oxide thin film transistor is turned on before the operation of the drive circuit The normal operation is performed, which results in poor display performance of the display device, deterioration of display quality, increase in power consumption, and shortened life span.

The embodiment of the present invention can reduce the threshold voltage shift control voltage VSC in the power supply part 140 from the shield pattern 131 to improve the characteristic deterioration caused by the shift of the threshold voltage VTH of the oxide- ) To shift the threshold voltage (VTH) of the oxide thin film transistor (Oxide-TFT) by -0.18V / 1V. After a certain period of time, the threshold voltage VTH of the oxide-TFT is shifted in the positive or negative direction according to the input threshold voltage shift control voltage VSC.

4, the threshold voltage VTH has a minus value in an oxide-TFT having an initial value, and an oxide-TFT is formed by a leakage current. The threshold voltage VTH is lower than the gate source voltage Vgs of the oxide thin film transistor (Oxide-TFT) when the low potential power source VSS is applied to the input terminal of the oxide thin film transistor (VSS) The oxide thin film transistor (Oxide-TFT) does not operate. This shows that the threshold voltage VTH of the oxide thin film transistor (oxide TFT) having a minus (-) value shifts in the positive direction and becomes higher than the gate source voltage Vgs. The threshold voltage VTH of the oxide thin film transistor is shifted in the positive direction and the leakage current blocking function is performed at Vgs = 0 V of the oxide thin film transistor (oxide-TFT).

In addition, after the display device of the present invention operates for a certain period of time, the oxide thin film transistor (Oxide-TFT) of the shift register 130 has a threshold voltage VTH higher than the voltage input to the shift register . Therefore, the threshold voltage VTH becomes higher than the gate source voltage Vgs of the oxide thin film transistor (Oxide-TFT) having a high threshold voltage (VTH), so that it may fail to operate as a switch circuit.

The threshold voltage VTH is lower than the gate-source voltage Vgs of the oxide-TFT (oxide-TFT) when the high-potential power supply VDD of +14 V is applied to the input terminal of the oxide- (Oxide-TFT) is operated. This shifts the threshold voltage VTH of the oxide thin film transistor (Oxide-TFT) having a negative (+) value in the negative direction and becomes lower than the gate source voltage (Vgs). That is, the threshold voltage VTH of the oxide thin film transistor (Oxide-TFT) is shifted in the negative direction, so that it can be continuously used as a switch circuit. As a result, the lifetime of the oxide thin film transistor (oxide-TFT) can be increased.

5 is a block diagram of a shift register according to the present invention. 6 is an exemplary diagram showing a circuit configuration of the N-th stage (Stage n) shown in FIG.

For reference, the TFT described in the embodiment may be configured as a P type or an N type, but in the following, the TFT is assumed to be of N type. Therefore, in the embodiment, the gate-on voltage is the gate high voltage VGH and the gate-off voltage is the gate low voltage VGL.

The shift register 200 is used as a driving circuit for driving a panel in a liquid crystal display or an organic light emitting display (hereinafter simply referred to as a flat panel display). The scan driving circuit of a flat panel display (display) And the scan pulse is sequentially supplied to the scan lines by using the register 200.

The shift register 200 of this scan driving circuit has a plurality of stages (Stage 1 to Stage n) 210 including a plurality of oxide thin film transistors (Oxide-TFT).

5, the shift register of the present invention includes a plurality of stages (Stage 1 to Stage n) 210, a plurality of shield patterns 220, a control voltage transmission line 230, and a plurality of stages 210, Signal transmission lines 240 for transmitting signals.

6, each of the plurality of stages Stage 1 to Stage n 210 includes a start signal Vst for starting the plurality of stages 210, a high potential power supply VDD, and a low potential power supply VSS ). The plurality of stages 210 are connected in a cascade to sequentially generate the output signals Gout 1 to Gout n.

Each of the plurality of stages (Stage 1 to Stage n) 210 includes a Q node for controlling a pull-up transistor (not shown) and a pull-down transistor (not shown) Lt; / RTI > node. In addition, each of the plurality of stages (Stage 1 to Stage n) 210 loads the Q node and the QB node voltage in response to the carry signal input from the previous stage, the carry signal input from the next stage, and the clock signal CLK. And discharge circuits T1 to T7 for discharging.

6, a plurality of stages 210 of the shift register 200 according to the present invention includes a switch T4 for initialization, a switch T1 for starting, an output voltage Vout A pull-up transistor T5 that is involved in discharging the output voltage of each stage, and a gate terminal that controls the turn-on and turn-off of the output voltage Vout switch of each stay A bootstrapping capacitance (CB) involved in raising the voltage across the connected queue-node (Q_node), a switch (T3) involved in discharging the queue-node (Q_node) .

In addition, the shift register 200 according to the present invention includes a plurality of shield patterns 220. The plurality of shield patterns 220 can control the movement of the threshold voltage VTH of the oxide-TFT of the shift register 200. The plurality of shield patterns 220 are formed on the switch circuits T1 to T7. In addition, the plurality of shield patterns 220 are electrically connected to each other. The plurality of shield patterns 220 are formed of the same material as the common electrode VCOM formed on the lower substrate of the display panel. The plurality of shield patterns 220 are supplied with the threshold voltage shift control voltage VSC using the control voltage transmission wiring 230. As a result, the threshold voltage VTH of the switch circuits T1 to T7 is shifted in a positive direction or a negative direction.

The shift register 200 according to the present invention includes a control voltage transmission line 230 for transmitting a threshold voltage shift control voltage VSC to a plurality of shield patterns 220. The control voltage transmission wiring 230 is electrically connected to each of the plurality of shield patterns 220. The control voltage transmission line 230 transmits the threshold voltage shift control voltage VSC transmitted from the power supply unit 140 to the plurality of shield patterns 220 before the shift register 200 operates.

Referring to FIG. 5, only one wiring for transmitting the threshold voltage transfer control voltage VSC to the plurality of stages 210 is illustrated. The control voltage transmission line 230 is electrically connected to the power supply unit 140 in the non-display area of the panel to transmit the threshold voltage shift control voltage VSC to the plurality of stages 210 of the shift register 200. The control voltage transmission line 230 is directly connected to the plurality of shield patterns 220 formed on the switch circuits T1 to T7 of the plurality of stages 210 through the contact holes. The control voltage transfer wiring 230 is formed in the same layer at the same time in the non-display region of the display panel when the gate line is formed in the display region of the display panel.

The plurality of shield patterns 220 according to the present invention are formed such that when a common electrode line positioned in a display region of a display panel is formed on an organic insulating film, a shield pattern 220 is formed simultaneously in the non- And is formed in the same layer as the common electrode line. The plurality of shield patterns 220 are electrically connected to the control voltage transmission line 230 in the non-display area using the contact holes. The control voltage transmission line 230 is electrically connected to the plurality of shield patterns 220 and transmits the threshold voltage shift control voltage VSC to the switch circuits T1 to T7 of the plurality of stages 210 . As a result, the threshold voltage (VTH) of the switch circuits (T1 to T7) can be appropriately shifted to prevent the shift register (200) of the GIP gate drive circuit from operating abnormally.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. It is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. .

100: display device 110: display panel
120: Source drive IC 130,200: Shift register
150: level shifter 160: timing controller
140: power generating unit 131, 220: multiple shield pattern
210: Multiple stages 230: Control voltage transmission wiring
240: clock signal transmission wiring

Claims

A display panel having a display area and a non-display area;
A shift register formed in the non-display region and sequentially outputting a gate signal to the display panel using a plurality of switch circuits;
A power generator for supplying a threshold voltage shift control voltage that is involved in a threshold voltage shift of the plurality of circuit switches; And
And a plurality of shield patterns disposed on the plurality of circuit switches to minimize an erroneous operation of the shift register.

The method according to claim 1,
And a connection wiring formed in the non-display area and connecting the power supply unit and the plurality of shield patterns.

3. The method of claim 2,
And the power supply unit transmits the threshold voltage shift control voltage to the connection wiring.

The method according to claim 1,
Wherein the power supply unit supplies the threshold voltage shift control voltage to the plurality of shield patterns before the shift register operates.

The method according to claim 1,
Wherein the switch circuits are oxide thin film transistors (Oxide-TFT).

6. The method of claim 5,
Wherein the oxide thin film transistor Oxide-TFTs have excellent threshold voltage transfer characteristics.

6. The method of claim 5,
Wherein the threshold voltage shift control voltage shifts a threshold voltage of the oxide thin film transistors Oxide-TFTs.

6. The method of claim 5,
Wherein the threshold voltage shift control voltage is a negative voltage to move the threshold voltage of the oxide thin film transistors Oxide-TFTs in a positive direction.

9. The method of claim 8,
And the threshold voltage of the oxide thin film transistor (Oxide-TFT) includes a leakage current remaining in a positive direction.

The method according to claim 1,
Wherein the threshold voltage shift control voltage is equal to a low potential voltage (VSS) supplied from the power supply unit.

The method according to claim 1,
The display region includes data lines, gate lines crossing the data lines, a TFT formed at each intersection of the data lines and the gate lines, and liquid crystal cells connected to the TFT and driven by an electric field between the pixel electrode and the common electrode And a TFT array including a storage capacitor.

12. The method of claim 11,
And the switch circuits of the shift register have the same structure as the TFTs of the display region.

12. The method of claim 11,
And the connection wiring located in the non-display area is formed in the same layer as the gate line in the display area.

12. The method of claim 11,
And the plurality of shield patterns located in the non-display region are formed in the same layer as the common electrode of the display region.

The method according to claim 1,
Wherein the power supply unit supplies the threshold voltage shift control voltage to the plurality of shield patterns after the shift register operates.

6. The method of claim 5,
Wherein the threshold voltage shift control voltage is a positive voltage and moves a threshold voltage of the oxide-TFTs in a negative direction.

17. The method of claim 16,
Wherein the shift of the threshold voltage of the oxide thin film transistors Oxide-TFTs in the negative direction increases the lifetime of the shifter resistors.

The method according to claim 1,
Wherein the threshold voltage shift control voltage is a voltage equal to a high potential voltage (VDD) supplied from the power supply unit.

In a GIP (Gate In Panel) driving circuit including a plurality of driving switches,
Wherein the plurality of drive switches shifts a threshold voltage of the plurality of drive switches in one direction during a first period before the GIP drive circuit operates, Wherein a threshold voltage of the plurality of driving switches shifts in a direction opposite to the one direction.

20. The method of claim 19,
Further comprising a power supply for supplying a control voltage to shift the threshold voltage of the plurality of driving switches.

20. The method of claim 19,
Wherein the driving switch is an oxide thin film transistor (Oxide-TFT) having a constant size.

22. The method of claim 21,
The oxide thin film transistor Oxide-TFT) having the same size as the oxide thin film transistor Oxide-TFT is located on the oxide thin film transistor Oxide-TFT.

23. The method of claim 22,
Wherein the power supply unit supplies a control voltage for controlling a threshold voltage shift to the metal pattern.