KR20170036865A - Organic Light Emitting Display Device - Google Patents

Abstract

The present invention improves driving reliability and durability of a display panel by using a connection structure which can prevent a side effect that a threshold voltage of a specific transistor included in a sub-pixel moves when a light blocking layer is used. To this end, a first light blocking layer is a conducted electrode of a switching transistor. A second light blocking layer is connected to a conducted electrode of a driving transistor.

Description

[0001] The present invention relates to an organic light emitting display device,

The present invention relates to an organic light emitting display.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, the use of display devices such as an organic light emitting display (OLED), a liquid crystal display (LCD), and a plasma display panel (PDP) is increasing.

Among the display devices described above, the organic light emitting display includes a display panel including a plurality of sub-pixels and a driver for driving the display panel. The driving unit includes a scan driver for supplying a scan signal (or a gate signal) to the display panel, and a data driver for supplying a data signal to the display panel.

The organic electroluminescent display device has a problem in that the characteristics (threshold voltage, current mobility, etc.) of the elements included in the sub-pixels change during long-term use. To compensate for this, a method of adding a circuit for sensing a characteristic of a device in a sub-pixel has been proposed. In addition, an organic light emitting display device has been proposed to add a light blocking layer that blocks external light to protect and stabilize an element (e.g., a thin film transistor) included in a sub-pixel from external light.

However, since the complexity of the elements constituting the subpixel is increased, when the light blocking layer is electrically connected to another electrode or wiring, the threshold voltage of a specific transistor included in the subpixel is shifted, Which is required to be improved.

SUMMARY OF THE INVENTION The present invention for solving the above problems of the background art is to prevent a side effect in which a threshold voltage of a specific transistor included in a sub-pixel is shifted when using a light blocking layer, thereby improving driving reliability, lifetime and display quality of the display panel.

According to an aspect of the present invention, there is provided an organic light emitting display including first through third light blocking layers, a buffer layer, an oxide semiconductor layer, and an insulating layer. The first through third light blocking layers are located on the substrate and correspond to the channel regions of the switching transistor, the driving transistor, and the sensing transistor, respectively. The buffer layer is located on the first to third light blocking layers. The oxide semiconductor layer is positioned corresponding to each of the buffer layers and has a conductive electrode corresponding to the source and drain regions of the switching transistor, the driving transistor, and the sensing transistor. The insulating layer is located on the oxide semiconductor layer. The first light blocking layer is connected to the conducting electrode of the switching transistor and the second light blocking layer is connected to the conducting electrode of the driving transistor.

The first light blocking layer and the conductive electrode of the switching transistor are exposed through the first contact hole of the insulating layer and can be electrically connected by the source drain metal layer located on the insulating layer.

The first contact hole may be located at the outline boundary of the conductive electrode of the switching transistor.

The first contact hole may be located between the driving transistor and the switching transistor or between the switching transistor and the data line.

The third light blocking layer may be integrated with the first light blocking layer.

The third light blocking layer may be disposed separately from the first light blocking layer.

The third light blocking layer and the electrically conductive electrode of the sensing transistor are exposed through the second contact hole of the insulating layer and can be electrically connected by the source drain metal layer located on the insulating layer.

The second contact hole may be located at an outer boundary line of the conductive electrode of the sensing transistor.

The second contact hole may be located between the driving transistor and the sensing transistor or may be located between the sensing transistor and the first power line.

The first light blocking layer may be coupled to the second electrode of the switching transistor and the third light blocking layer may be coupled to the second electrode of the driving transistor.

The present invention has the effect of improving driving reliability and lifetime of a display panel by using a connection structure that can prevent a side effect in which a threshold voltage of a specific transistor included in a subpixel is shifted when using a light blocking layer. Further, the present invention has the effect of improving the display quality by eliminating side effects due to use of the light blocking layer.

FIG. 1 is a schematic block diagram of an organic light emitting display according to a first embodiment of the present invention. FIG.
2 is a schematic circuit configuration diagram of a subpixel.
3 is a diagram illustrating an example of a circuit configuration of a subpixel according to the first embodiment of the present invention.
4 is a cross-sectional exemplary view of a display panel according to a first embodiment of the present invention;
5 to 9 are plan views schematically illustrating a process sequence of a subpixel according to the first embodiment of the present invention.
10 is a sectional view of the region A-A 'in FIG. 9;
11 is a diagram illustrating an example of a circuit configuration of a subpixel according to a second embodiment of the present invention.
12 to 16 are plan views schematically illustrating a process sequence of a subpixel according to a second embodiment of the present invention.
17 is a sectional view of the region A-A 'in Fig.
18 is a sectional view of the region B-B 'in Fig. 16;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

≪ Embodiment 1 >

FIG. 1 is a schematic block diagram of an organic light emitting display according to a first embodiment of the present invention. FIG. 2 is a schematic circuit diagram of a subpixel. FIG. 3 is a circuit diagram of a subpixel according to a first embodiment of the present invention. And Fig.

1, an organic light emitting display according to a first exemplary embodiment of the present invention includes an image processing unit 110, a timing control unit 120, a data driving unit 130, a scan driving unit 140, 150).

The image processing unit 110 outputs a data enable signal DE together with a data signal DATA supplied from the outside. The image processing unit 110 may output at least one of a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of explanation.

The timing controller 120 receives a data signal DATA from a video processor 110 in addition to a data enable signal DE or a driving signal including a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal. The timing controller 120 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 130, .

The data driver 130 samples and latches the data signal DATA supplied from the timing controller 120 in response to the data timing control signal DDC supplied from the timing controller 120 and converts the sampled data signal into a gamma reference voltage . The data driver 130 outputs the data signal DATA through the data lines DL1 to DLn. The data driver 130 may be formed in the form of an IC (Integrated Circuit).

The scan driver 140 outputs a scan signal (or a gate signal) while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 120. The scan driver 140 outputs a scan signal through the scan lines GL1 to GLm. The scan driver 140 is formed in the form of an integrated circuit (IC) or a gate-in-panel (GATE) panel in the display panel 150.

The display panel 150 displays an image corresponding to the data signal DATA and the scan signal supplied from the data driver 130 and the scan driver 140. The display panel 150 includes sub-pixels SP that operate to display an image.

The subpixels are formed in a top emission mode, a bottom emission mode, or a dual emission mode depending on the structure. The subpixels SP include a red subpixel, a green subpixel, and a blue subpixel or a white subpixel, a red subpixel, a green subpixel, and a blue subpixel. The subpixels SP may have one or more different emission areas depending on the emission characteristics.

As shown in FIG. 2, one sub-pixel includes a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light emitting diode OLED.

The switching transistor SW is operated so that a data signal supplied through the first data line DL1 is stored as a data voltage in the capacitor Cst in response to a scan signal supplied through the first scan line GL1. The driving transistor DR operates so that a driving current flows between the first power supply line EVDD and the second power supply line EVSS in accordance with the data voltage stored in the capacitor Cst. The organic light emitting diode OLED operates to emit light in accordance with the driving current generated by the driving transistor DR.

The compensation circuit CC is a circuit added in the sub-pixel to compensate the threshold voltage of the driving transistor DR and the like. The compensation circuit CC is composed of one or more transistors. The configuration of the compensation circuit (CC) varies greatly according to the compensation method. An example of the compensation circuit (CC) is as follows.

As shown in Fig. 3, the compensation circuit CC includes a sensing transistor ST and a sensing line VREF. The sensing transistor ST is connected between a source line of the driving transistor DR and an anode electrode of the organic light emitting diode OLED (hereinafter referred to as a sensing node). The sensing transistor ST operates to supply the initialization voltage (or sensing voltage) transmitted through the sensing line VREF to the sensing node or to sense the voltage or current of the sensing node.

The configuration and connection relationship of the elements included in the sub-pixel together with the compensation circuit CC will be described below.

In the switching transistor SW, the first electrode is connected to the first data line DL1, and the second electrode is connected to the gate electrode of the driving transistor DR. The first electrode of the driving transistor DR is connected to the first power supply line EVDD and the second electrode of the driving transistor DR is connected to the anode electrode of the organic light emitting diode OLED. In the capacitor Cst, the first electrode is connected to the gate electrode of the driving transistor DR, and the second electrode is connected to the anode electrode of the organic light emitting diode OLED. In the organic light emitting diode OLED, an anode electrode is connected to the second electrode of the driving transistor DR, and a cathode electrode is connected to the second power supply line EVSS. The sensing transistor ST has a first electrode connected to the sensing line VREF and a second electrode connected to the anode electrode of the organic light emitting diode OLED. The first electrode or the second electrode means a source electrode of the transistor (which may be a drain electrode depending on the transistor type) or a drain electrode (which may be a source electrode depending on the type of the transistor).

The operation time of the sensing transistor ST may be similar to or different from the switching transistor SW according to the compensation algorithm (or the configuration of the compensation circuit). For example, the gate electrode of the switching transistor SW may be connected to the first scan line GL1a, and the gate electrode of the sensing transistor ST may be coupled to the first scan line GL1b. As another example, the first scan line GL1a connected to the gate electrode of the switching transistor SW and the first scan line GL1b connected to the gate electrode of the sensing transistor ST may be commonly connected.

The sensing line VREF may be connected to the data driver. In this case, the data driver can sense the sensing node of the subpixel during the non-display period of the real time image, or the N frame (N is an integer of 1 or more) and generate the sensing result. The switching transistor SW and the sensing transistor ST can be turned on at the same time. In this case, the sensing operation through the sensing line (VREF) and the data output operation for outputting the data signal are separated (separated) based on the time division system of the data driver.

In addition, the object to be compensated according to the sensing result may be a digital data signal, an analog data signal, gamma, or the like. The compensation circuit for generating the compensation signal (or the compensation voltage) based on the sensing result may be implemented in the interior of the data driver, in the timing controller, or in a separate circuit.

Light blocking layers LSs, LSd, and LSt are formed on the lower or upper layers corresponding to the channel regions of the switching transistor SW, the driving transistor DR, and the sensing transistor ST. The light blocking layers LSs, LSd, and LSt exist to protect and stabilize the switching transistor SW, the driving transistor DR, and the sensing transistor ST from external light. The light blocking layers LSs, LSd, and LSt serve to block external light.

The channel region is protected by the first light blocking layer LSs of the switching transistor SW. The first light blocking layer LSs is connected to the second electrode of the switching transistor SW. The channel region is protected by the second light blocking layer LSd in the driving transistor DR. The second light blocking layer LSd is connected to the second electrode of the driving transistor DR. The channel region is protected by the third light blocking layer LSt in the sensing transistor ST. The third light blocking layer LSt is connected to the second electrode of the switching transistor SW.

3, a sub-pixel of a 3T (Capacitor) structure including a switching transistor SW, a driving transistor DR, a capacitor Cst, an organic light emitting diode OLED, and a sensing transistor ST However, if the compensation circuit CC is added, it may be composed of 3T2C, 4T2C, 5T1C, 6T2C, and the like.

Hereinafter, the display panel according to the first embodiment of the present invention will be described in detail with reference to sectional views / plan views of subpixels constituting the display panel.

FIGS. 5 to 9 are plan views schematically illustrating a process sequence of a subpixel according to the first embodiment of the present invention. FIG. 4 is a cross- 10 is a cross-sectional view of the region A-A 'in Fig.

As shown in FIG. 4, the display panel 150 includes a pixel P positioned between the substrate 150a and the protective substrate (or film) 150b. The area where the pixel P is arranged is defined as the display area AA and the outline of the display area AA where the pixel P is not arranged is defined as the non-display area NA.

The pixel P is composed of four subpixels of red (R), white (W), blue (B) and green (G) And may consist of more than three subpixels. The red (R), white (W), blue (B) and green (G) subpixels are arranged horizontally or vertically. The arrangement order of the subpixels can be variously changed according to the light emitting material, the light emitting area, the structure (or structure) of the compensation circuit, and the like.

One subpixel shown in FIG. 4 is formed as follows based on the circuit shown in FIG. However, since the first embodiment of the present invention deals with the connection relation and the stacking relationship of the light-blocking layer and the light-blocking layer formed in the device region of the sub-pixel, the illustration and description of the opening region of the sub-pixel are omitted.

As shown in FIGS. 5 to 9, an element region SPA and an opening region SPE of a subpixel are defined on a substrate 150a. The driving transistor DR, the capacitor Cst, the switching transistor SW, and the sensing transistor ST are formed in the element region SPA of the subpixel. An organic light emitting diode (OLED) is formed in an opening region (SPE) of a subpixel located above an element region (SPA) of a subpixel.

A light blocking layer 151 is formed on the substrate 150a. The light blocking layer 151 includes first and third light blocking layers LSs and LSt corresponding to the semiconductor layer 153 of the switching transistor SW and the sensing transistor ST and the semiconductor layer 153 of the driving transistor DR. The second light blocking layer LSd corresponding to the second light blocking layer LSd is formed separately. The light blocking layer 151 is formed of a portion LSs or LSt formed integrally (or commonly) for covering both the switching transistor SW and the semiconductor layer 153 of the sensing transistor ST, And a portion LSd formed so as to cover only one layer 153.

A buffer layer 152 is formed on the light blocking layer 151. The buffer layer 152 is formed corresponding to the light blocking layer 151. A semiconductor layer 153 is formed on the buffer layer 152. The semiconductor layer 153 is formed separately in regions occupied by the switching transistor SW, the sensing transistor ST, and the driving transistor DR.

The semiconductor layer 153 of the switching transistor SW, the sensing transistor ST and the driving transistor DR is made of an oxide semiconductor (for example, IGZO). The semiconductor layer 153 of the switching transistor SW, the sensing transistor ST and the driving transistor DR includes a portion that becomes a channel region and a portion that is made conductive by a conducting process.

Since the semiconductor layer 153 of the switching transistor SW, the sensing transistor ST and the driving transistor DR is made of an oxide semiconductor (for example, IGZO), if the conducting process is performed, . The conductor portion of the semiconductor layer 153 becomes the source electrode (or source region) and the drain electrode (or drain region) of the transistor. That is, the semiconductor layer 153 has a conductorized electrode corresponding to the source and drain regions of the switching transistor SW, the sensing transistor ST, and the driving transistor DR.

A first insulating layer 154 is formed on the semiconductor layer 153. A gate metal layer 155 is formed on the first insulating layer 154. The first insulating layer 154 may be defined as a gate insulating layer, which may be patterned in the island shape like the gate electrode formed on the top.

The gate metal layers 155a to 155d include first to fourth gate metal layers 155a to 155d. The first gate metal layer 155a serves as a connection electrode for connecting the first power supply line EVDD to the adjacent sub-pixels. The first gate metal layer 155a may be patterned with a needle-shaped electrode. And the second gate metal layer 155b becomes the gate electrode of the driving transistor DR. The second gate metal layer 155b may be patterned with an electrode in the form of a bar having a longer vertical direction. The third gate metal layer 155c becomes the scan line GL as the gate electrode of the switching transistor SW and the sensing transistor ST. The third gate metal layer 155c may be disposed along the horizontal direction, and may include a portion branched into two lines. The fourth gate metal layer 155d becomes a sensing line VREF connected to the first electrode of the sensing transistor ST. The fourth gate metal layer 155d may be disposed along the horizontal direction, and may include a portion branched into two lines.

A second insulating layer 156 is formed on the gate metal layers 155a to 155d. The second insulating layer 156 may be defined as an interlayer insulating layer that provides electrical insulation between a lower structure and a structure formed thereon.

The second insulating layer 156 is formed with a plurality of contact holes exposing a part of the lower structure. A plurality of contact holes are formed by a hole mask. A plurality of contact holes including the first contact hole CH1 and the second contact hole CH2 are formed in the second insulating layer 156 by the hole mask. The second contact hole CH2 connects the first and third light blocking layers LSs and LSt located below the switching transistor SW and the sensing transistor ST to the sensing transistor SW or the switching transistor SW 1 or the second electrode. The related description will be described again with reference to FIG.

On the second insulating layer 156, source drain metal layers 157a to 157e are formed. The first source drain metal layer 157a becomes the first power source line EVDD. The first source drain metal layer 157a is disposed along the vertical direction, and only a part of the first source drain metal layer 157a connected to the sub pixels protrudes in the horizontal direction. The second source drain metal layer 157b connects the second electrode of the switching transistor SW and the gate electrode 155b of the driving transistor DR and becomes one electrode of the capacitor Cst. The area of the second source drain metal layer 157b overlapping the region where the gate electrode of the driving transistor DR is made conductive can be broadened. The third source drain metal layer 157c serves as a connection electrode connecting the second electrode of the driving transistor DR and the second electrode of the sensing transistor ST. The third source drain metal layer 157c may be patterned in an L shape. And the fourth source drain metal layer 157d becomes the data line DLn1. The fourth source drain metal layer 157d is disposed along the vertical direction, and only a portion connected to the sub pixel is partially protruded in the horizontal direction. The fifth source drain metal layer 157e serves as a connection electrode for connecting the first electrode of the sensing transistor ST to the sensing line VREF. The fifth source drain metal layer 157e may be patterned in a one-letter shape or an I-letter shape.

A third insulating layer 158 is formed on the source drain metal layers 157a to 157e. The third insulating layer 158 may be defined as a protective layer for protecting structures such as transistors formed on the substrate 150a.

On the third insulating layer 158, a color filter (not shown) is formed corresponding to the opening area SPE of the subpixel. When the organic light emitting diode formed by the following process emits white light, a color filter is formed on the third insulating layer 158. However, when the organic light emitting diode itself emits red, green, .

A fourth insulating layer 160 is formed on the third insulating layer 159. The fourth insulating layer 160 may be defined as a coating layer for planarizing the surface. The third insulating layer 158 and the fourth insulating layer 160 have contact holes exposing a part of the source electrode of the driving transistor DR.

A pixel electrode 161 is formed on the fourth insulating layer 160. The pixel electrode 161 may be defined as an anode electrode of the organic light emitting diode OLED. The pixel electrode 161 is electrically connected to the source electrode exposed through the fourth insulating layer 160. The pixel electrode 161 may be selected as a transparent electrode to emit light emitted from the organic light emitting layer toward the substrate 150a.

A bank layer (not shown) is formed on the fourth insulating layer 160. The bank layer has an opening region that exposes a part of the pixel electrode 161, and defines a substantial light emitting region. An organic light emitting layer and an upper electrode (not shown) are formed on the bank layer. The upper electrode may be defined as a cathode electrode of the organic light emitting diode (OLED). The upper electrode is electrically connected to a second power line (not shown). The upper electrode may be selected as an opaque electrode so that light emitted from the organic light emitting layer is emitted only toward the substrate 150a. However, the upper electrode may also be selected as a transparent electrode in order to emit light emitted from the organic light emitting layer toward the substrate 150a in opposite or opposite directions depending on purposes, functions, etc. of the display panel.

3, the first embodiment of the present invention includes the first and third light blocking layers LSs and LSt located below the switching transistor SW and the sensing transistor ST, DR of the second light blocking layer LSd is separated as follows.

In the experimental example, the light blocking layers LSs, LSd, and LSt are commonly connected to the second electrode (sensing node) of the driving transistor DR in order to electrically stabilize the light blocking layer. As a result of the experiment based on this structure, as the voltage Vs flowing through the second electrode of the driving transistor DR is applied to the light blocking layers LSs, LSd, and LSt, the threshold voltage of the switching transistor SW is shifted Which is a problem.

Due to such a problem, when the threshold voltage Vth of the switching transistor SW is continuously shifted in the negative direction (-Vth Shift), a scan signal of a logic low (a signal or voltage for turning off the transistor, e.g., VGL) The switching transistor SW is turned on (VGL> Vth relation but Vth becomes lower than VGL). That is, the switching transistor SW is turned on during a period in which the switching transistor SW should not be turned on.

The first and third light blocking layers LSs and LSt of the switching transistor SW and the sensing transistor ST and the driving transistor DR of the sensing transistor ST, The second light blocking layer LSd was electrically isolated and simulated.

As a result of the simulation based on the first embodiment of the present invention, the first and third light blocking layers LSs and LSt of the switching transistor SW and the sensing transistor ST and the second light blocking layer The side effect that the threshold voltage of the switching transistor SW is shifted due to the electrical isolation of the switching transistor LSd is improved and can be solved.

As shown in Figs. 9 and 10, the first contact hole CH1 exposes a part of the second source drain metal layer 157b. The second source drain metal layer 157b exposed through the first contact hole CH1 is electrically connected to the pixel electrode 161. [

The second contact hole CH2 (second side contact hole) exposes a part of the second electrode 153a of the sensing transistor ST and the third light blocking layer 151 (LSt) located below the second electrode 153a. The second electrode 153a of the sensing transistor ST is formed by the semiconductor layer 153 which is made conductive. The region adjacent to the second electrode 153a is a channel region 153b.

The second contact hole CH2 is electrically connected to the second electrode 153a of the sensing transistor ST and the second electrode 153a of the sensing transistor ST to expose a part of the third light blocking layer 151, Is formed on the outer boundary line of the outer casing 153a. If the second contact hole CH2 is formed in the outer boundary line of the second electrode 153a of the sensing transistor ST, the second electrode 153a of the sensing transistor ST and the second electrode 153b 3 light blocking layer 151 (LSt) can be formed. The second contact hole CH2 may be located between the driving transistor DR and the sensing transistor ST or may be located between the sensing transistor ST and the first power source line EVDD.

The third light blocking layer 151 (LSt) located under the sensing transistor ST is connected to the gate electrode of the driving transistor by the second source drain metal layer 157b.

As described above, the third light blocking layer 151, LSt is formed in common to cover both the switching transistor SW and the semiconductor layer 153 of the sensing transistor ST. Therefore, only the third light blocking layer 151 (LSt) located under the sensing transistor ST may be connected to the gate electrode of the driving transistor DR.

The first and third light blocking layers 151 and LSs and LSt of the switching transistor SW and the sensing transistor ST are commonly connected to the second electrode 153a of the sensing transistor ST in the first embodiment of the present invention As an example. However, the first and third light blocking layers 151, LSs, and LSt of the switching transistor SW and the sensing transistor ST may be commonly connected to the first electrode of the sensing transistor ST. This is because when the first and third light blocking layers 151 and LSs and LSt of the switching transistor SW and the sensing transistor ST are electrically separated from the second light blocking layer LSd of the driving transistor DR, The effect according to the first embodiment of the present invention can be obtained.

Hereinafter, a structure in which a light blocking layer is separated in a manner different from the first embodiment will be described.

≪ Embodiment 2 >

FIG. 11 is a circuit diagram of a subpixel according to a second embodiment of the present invention, FIGS. 12 to 16 are plan views schematically illustrating a subpixel process sequence according to a second embodiment of the present invention, FIG. 17 is a cross-sectional view taken along the line A-A 'of FIG. 16, and FIG. 18 is a cross-sectional view taken along the line B-B' of FIG.

11, a first electrode of the switching transistor SW is connected to the first data line DL1, and a second electrode of the switching transistor SW is coupled to a gate electrode of the driving transistor DR. The first electrode of the driving transistor DR is connected to the first power supply line EVDD and the second electrode of the driving transistor DR is connected to the anode electrode of the organic light emitting diode OLED. In the capacitor Cst, the first electrode is connected to the gate electrode of the driving transistor DR, and the second electrode is connected to the anode electrode of the organic light emitting diode OLED. In the organic light emitting diode OLED, an anode electrode is connected to the second electrode of the driving transistor DR, and a cathode electrode is connected to the second power supply line EVSS. The sensing transistor ST has a first electrode connected to the sensing line VREF and a second electrode connected to the anode electrode of the organic light emitting diode OLED.

Light blocking layers LSs, LSd, and LSt are formed on the lower or upper layers corresponding to the channel regions of the switching transistor SW, the driving transistor DR, and the sensing transistor ST. The light blocking layers LSs, LSd, and LSt exist to protect and stabilize the switching transistor SW, the driving transistor DR, and the sensing transistor ST from external light. The light blocking layers LSs, LSd, and LSt serve to block external light.

The channel region is protected by the first light blocking layer LSs of the switching transistor SW. The first light blocking layer LSs is connected to the second electrode of the switching transistor SW. The channel region is protected by the second light blocking layer LSd in the driving transistor DR. The second light blocking layer LSd is connected to the second electrode of the driving transistor DR. The channel region is protected by the third light blocking layer LSt in the sensing transistor ST. And the third light blocking layer LSt is connected to the second electrode of the driving transistor DR. The third light blocking layer LSt may be connected to the first electrode of the sensing transistor ST. In this case, the third light blocking layer LSt is physically / electrically separated from the second light blocking layer LSd. However, in the following description, the light blocking layer of the switching transistor SW and the light blocking layer of the sensing transistor ST and the driving transistor DR are physically / electrically separated from each other.

One subpixel is formed based on the circuit described in Fig. 11 as follows. However, since the first embodiment of the present invention deals with the connection relation and the stacking relationship of the light-blocking layer and the light-blocking layer formed in the device region of the sub-pixel, the illustration and description of the opening region of the sub-pixel are omitted.

As shown in FIGS. 12 to 16, an element region SPA and an opening region SPE of a subpixel are defined on a substrate 150a. The driving transistor DR, the capacitor Cst, the switching transistor SW, and the sensing transistor ST are formed in the element region SPA of the subpixel. An organic light emitting diode (OLED) is formed in an opening region (SPE) of a subpixel located above an element region (SPA) of a subpixel.

A light blocking layer 151 is formed on the substrate 150a. The light blocking layer 151 includes first, second and third light blocking layers LSs, LSt, and LSd corresponding to the semiconductor layers 153 of the switching transistor SW, the sensing transistor ST, and the driving transistor DR, Are all formed separately. The light blocking layer 151 is separated into independent layers to cover the switching transistor SW, the sensing transistor ST, and the semiconductor layer 153 of the driving transistor DR, respectively.

A buffer layer 152 is formed on the light blocking layer 151. The buffer layer 152 is formed corresponding to the light blocking layer 151. A semiconductor layer 153 is formed on the buffer layer 152. The semiconductor layer 153 is formed separately in regions occupied by the switching transistor SW, the sensing transistor ST, and the driving transistor DR.

The semiconductor layer 153 of the switching transistor SW, the sensing transistor ST and the driving transistor DR is made of an oxide semiconductor (for example, IGZO). The semiconductor layer 153 of the switching transistor SW, the sensing transistor ST and the driving transistor DR includes a portion that becomes a channel region and a portion that is made conductive by a conducting process.

Since the semiconductor layer 153 of the switching transistor SW, the sensing transistor ST and the driving transistor DR is made of an oxide semiconductor (for example, IGZO), if the conducting process is performed, . The conductor portion of the semiconductor layer 153 becomes the source electrode (or source region) and the drain electrode (or drain region) of the transistor. That is, the semiconductor layer 153 has a conductorized electrode corresponding to the source and drain regions of the switching transistor SW, the sensing transistor ST, and the driving transistor DR.

A first insulating layer 154 is formed on the semiconductor layer 153. A gate metal layer 155 is formed on the first insulating layer 154. The first insulating layer 154 may be defined as a gate insulating layer, which may be patterned in the island shape like the gate electrode formed on the top.

The gate metal layers 155a to 155d include first to fourth gate metal layers 155a to 155d. The first gate metal layer 155a serves as a connection electrode for connecting the first power supply line EVDD to the adjacent sub-pixels. The first gate metal layer 155a may be patterned with a needle-shaped electrode. And the second gate metal layer 155b becomes the gate electrode of the driving transistor DR. The second gate metal layer 155b may be patterned with an electrode in the form of a bar having a longer vertical direction. The third gate metal layer 155c becomes the scan line GL as the gate electrode of the switching transistor SW and the sensing transistor ST. The third gate metal layer 155c may be disposed along the horizontal direction, and may include a portion branched into two lines. The fourth gate metal layer 155d becomes a sensing line VREF connected to the first electrode of the sensing transistor ST. The fourth gate metal layer 155d may be disposed along the horizontal direction, and may include a portion branched into two lines.

A second insulating layer 156 is formed on the gate metal layers 155a to 155d. The second insulating layer 156 may be defined as an interlayer insulating layer that provides electrical insulation between a lower structure and a structure formed thereon.

The second insulating layer 156 is formed with a plurality of contact holes exposing a part of the lower structure. A plurality of contact holes are formed by a hole mask. The second insulating layer 156 is formed with a plurality of contact holes including the first contact hole CH1 through the second contact hole CH3 by the hole mask. The second contact hole CH2 is used to connect the third light blocking layer LSt located under the sensing transistor ST to the first or second electrode of the sensing transistor ST. The third contact hole CH3 is used to connect the first light blocking layer LSs of the switching transistor SW to the first or second electrode of the switching transistor SW. The description related to this will be described again with reference to FIG. 17 and FIG.

On the second insulating layer 156, source drain metal layers 157a to 157e are formed. The first source drain metal layer 157a becomes the first power source line EVDD. The first source drain metal layer 157a is disposed along the vertical direction, and only a part of the first source drain metal layer 157a connected to the sub pixels protrudes in the horizontal direction. The second source drain metal layer 157b connects the second electrode of the switching transistor SW and the gate electrode 155b of the driving transistor DR and becomes one electrode of the capacitor Cst. The area of the second source drain metal layer 157b overlapping the region where the gate electrode of the driving transistor DR is made conductive can be broadened. The third source drain metal layer 157c serves as a connection electrode connecting the second electrode of the driving transistor DR and the second electrode of the sensing transistor ST. The third source drain metal layer 157c may be patterned in an L shape. And the fourth source drain metal layer 157d becomes the data lines DLn1. The fourth source drain metal layer 157d is disposed along the vertical direction, and only a portion connected to the sub pixel is partially protruded in the horizontal direction. The fifth source drain metal layer 157e serves as a connection electrode for connecting the first electrode of the sensing transistor ST to the sensing line VREF. The fifth source drain metal layer 157e may be patterned in a one-letter shape or an I-letter shape.

A third insulating layer 158 is formed on the source drain metal layers 157a to 157e. The third insulating layer 158 may be defined as a protective layer for protecting structures such as transistors formed on the substrate 150a.

On the third insulating layer 158, a color filter (not shown) is formed corresponding to the opening area SPE of the subpixel. When the organic light emitting diode formed by the following process emits white light, a color filter is formed on the third insulating layer 158. However, when the organic light emitting diode itself emits red, green, .

A fourth insulating layer 160 is formed on the third insulating layer 159. The fourth insulating layer 160 may be defined as a coating layer for planarizing the surface. The third insulating layer 158 and the fourth insulating layer 160 have contact holes exposing a part of the source electrode of the driving transistor DR.

A pixel electrode 161 is formed on the fourth insulating layer 160. The pixel electrode 161 may be defined as an anode electrode of the organic light emitting diode OLED. The pixel electrode 161 is electrically connected to the source electrode exposed through the fourth insulating layer 160. The pixel electrode 161 may be selected as a transparent electrode to emit light emitted from the organic light emitting layer toward the substrate 150a.

A bank layer (not shown) is formed on the fourth insulating layer 160. The bank layer has an opening region that exposes a part of the pixel electrode 161, and defines a substantial light emitting region. An organic light emitting layer and an upper electrode (not shown) are formed on the bank layer. The upper electrode may be defined as a cathode electrode of the organic light emitting diode (OLED). The upper electrode is electrically connected to a second power line (not shown). The upper electrode may be selected as an opaque electrode so that light emitted from the organic light emitting layer is emitted only toward the substrate 150a. However, the upper electrode may also be selected as a transparent electrode in order to emit light emitted from the organic light emitting layer toward the substrate 150a in opposite or opposite directions depending on purposes, functions, etc. of the display panel.

11, the second embodiment of the present invention includes a first light blocking layer LSs located under the switching transistor SW, a lower portion of the driving transistor DR and the sensing transistor ST, The second and third light blocking layers LSd and LSt are separated from each other. The reason for this is as follows.

Conventionally, the light blocking layers LSs, LSd, and LSt are commonly connected to the second electrode (sensing node) of the driving transistor DR in order to electrically stabilize the light blocking layers LSs, LSd, and LSt. As a result of the experiment based on this structure, as the voltage Vs flowing through the second electrode of the driving transistor DR is applied to the light blocking layers LSs, LSd, and LSt, the threshold voltage of the switching transistor SW is shifted Which is a problem.

Due to such a problem, when the threshold voltage Vth of the switching transistor SW is continuously shifted in the negative direction (-Vth Shift), a scan signal of a logic low (a signal or voltage for turning off the transistor, e.g., VGL) The switching transistor SW is turned on (VGL> Vth relation but Vth becomes lower than VGL). That is, the switching transistor SW is turned on during a period in which the switching transistor SW should not be turned on.

In order to solve the conventional problem, the second embodiment of the present invention is characterized in that the light blocking layer LSs of the switching transistor SW, the light blocking layers LSt, LSd of the sensing transistor ST and the driving transistor DR ) Were electrically isolated and simulated. As a result of simulation based on the second embodiment of the present invention, the light blocking layers LSs of the switching transistor SW and the light blocking layers LSt and LSd of the sensing transistor ST and the driving transistor DR are electrically separated Side effects in which the threshold voltage of the switching transistor SW is shifted can be improved and eliminated.

As shown in Figs. 16 and 17, the first contact hole CH1 exposes a part of the second source drain metal layer 157b. The second source drain metal layer 157b exposed through the first contact hole CH1 is electrically connected to the pixel electrode 161. [

The second contact hole CH2 (second side contact hole) exposes a part of the second electrode 153a of the sensing transistor ST and the third light blocking layer 151 (LSt) located below the second electrode 153a. The second electrode 153a of the sensing transistor ST is formed by the semiconductor layer 153 which is made conductive. The region adjacent to the second electrode 153a is a channel region 153b.

The second contact hole CH2 is electrically connected to the second electrode 153a of the sensing transistor ST and the second electrode 153a of the sensing transistor ST to expose a part of the third light blocking layer 151, Is formed on the outer boundary line of the outer casing 153a. If the second contact hole CH2 is formed in the outer boundary line of the second electrode 153a of the sensing transistor ST, the second electrode 153a of the sensing transistor ST and the second electrode 153b 3 light blocking layer 151 (LSt) can be formed. The second contact hole CH2 may be located between the driving transistor DR and the sensing transistor ST or may be located between the sensing transistor ST and the first power source line EVDD.

The third light blocking layer 151 (LSt) located under the sensing transistor ST is connected to the gate electrode of the driving transistor by the second source drain metal layer 157b.

16 and 18, the third contact hole CH3 (first side contact hole) is electrically connected to the second electrode 153a of the switching transistor SW and the first light blocking layer 151 , LSs). The second electrode 153a of the switching transistor SW is formed by a semiconductor layer 153 which is made conductive. The region adjacent to the second electrode 153a is a channel region 153b.

The third contact hole CH3 is electrically connected to the second electrode 153a of the switching transistor SW and the second electrode 153a of the switching transistor SW to expose a part of the first light blocking layer 151, Is formed on the outer boundary line of the outer casing 153a. If the third contact hole CH3 is formed on the outer boundary line of the second electrode 153a of the switching transistor SW, the second electrode 153a of the switching transistor SW and the lower electrode 1 light blocking layer 151 (LSs) can be formed. The third contact hole CH3 may be located between the driving transistor DR and the switching transistor SW or may be located between the switching transistor SW and the first data line DLn1.

The first light blocking layer 151 (LSs) located under the switching transistor SW is connected to the second electrode of the driving transistor DR by the third source drain metal layer 157c.

In the second embodiment of the present invention, the third light blocking layer 151 (LSt) of the sensing transistor ST is connected to the second electrode 153a of the sensing transistor ST, and the first light blocking layer (151, LSs) to the second electrode of the driving transistor DR. The first light blocking layer 151 of the switching transistor SW is connected to the first electrode of the switching transistor SW and the third light blocking layer 151 of the sensing transistor ST is connected to the sensing transistor ST, To the first electrode of the second transistor. This is because when the first and third light blocking layers 151 and LSs and LSt of the switching transistor SW and the sensing transistor ST are electrically separated from the second light blocking layer LSd of the driving transistor DR, The effect according to the second embodiment of the present invention can be obtained.

The present invention has the effect of improving the driving reliability and lifetime of the display panel by using a connection structure that can prevent a side effect in which a threshold voltage of a specific transistor included in a sub-pixel is shifted when using a light blocking layer. Further, the present invention has the effect of improving the display quality by eliminating side effects due to use of the light blocking layer.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

110: image processor 120: timing controller
130: Data driver 140:
150: display panel ST: sensing transistor
DR: driving transistor SW: switching transistor
VREF: sensing line DLn1: data line
151: light blocking layer 152: buffer layer
155a to 155d: gate metal layers 157a to 157e: source and drain metal layers

Claims (10)

First to third light blocking layers located on the substrate and corresponding to the channel regions of the switching transistor, the driving transistor and the sensing transistor, respectively;
A buffer layer located on the first through third light blocking layers;
An oxide semiconductor layer located corresponding to each of the buffer layers and having a conductive electrode corresponding to source and drain regions of the switching transistor, the driving transistor, and the sensing transistor; And
And an insulating layer disposed on the oxide semiconductor layer,
Wherein the first light blocking layer is connected to the conductive electrode of the switching transistor and the second light blocking layer is connected to the conductive electrode of the driving transistor. The method according to claim 1,
Wherein the first light blocking layer and the conductive electrode of the switching transistor are exposed through the first side contact hole of the insulating layer,
Wherein the source electrode and the drain electrode are electrically connected to each other by a source drain metal layer located on the insulating layer. 3. The method of claim 2,
The first side contact hole
Wherein the conductive layer of the switching transistor is located at an outer boundary line of the conductive electrode. The method of claim 3,
The first side contact hole
Wherein the organic light emitting display is located between the driving transistor and the switching transistor or between the switching transistor and the data line. The method according to claim 1,
The third light blocking layer
And the first light blocking layer is integrated with the first light blocking layer. 5. The method of claim 4,
The third light blocking layer
And the first light blocking layer is disposed separately from the first light blocking layer. The method according to claim 6,
Wherein the third light blocking layer and the conductive electrode of the sensing transistor are exposed through the second side contact hole of the insulating layer,
Wherein the source electrode and the drain electrode are electrically connected to each other by a source drain metal layer located on the insulating layer. 8. The method of claim 7,
The second side contact hole
Wherein the sensing transistor is located at an outer boundary line of a conductive electrode of the sensing transistor. 9. The method of claim 8,
The second side contact hole
Wherein the organic light emitting display is disposed between the driving transistor and the sensing transistor or between the sensing transistor and the first power line. The method according to claim 1,
Wherein the first light blocking layer is connected to the second electrode of the switching transistor and the third light blocking layer is connected to the second electrode of the driving transistor.

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