KR102563777B1 - Organic Light Emitting Display Device - Google Patents

Abstract

The present invention provides an organic light emitting display device capable of solving the problem of a capacitor disappearing without being formed due to a short circuit between electrodes caused by foreign matter or particles occurring in a process. The conductor region of the semiconductor layer is made of the semiconductor layer positioned on the first substrate and is conductive. The first insulating layer is located on the conductor region of the semiconductor layer. A gate metal layer is located on the first insulating layer. The second insulating layer has a contact hole exposing a portion of the gate metal layer. The source-drain metal layer is positioned on the second insulating layer and electrically connected to the gate metal layer through a contact hole. The conductor region of the semiconductor layer does not overlap with the gate metal layer.

Description

Organic light emitting display device {Organic Light Emitting Display Device}

The present invention relates to an organic light emitting display device.

As information technology develops, the market for display devices, which are communication media between users and information, is growing. Accordingly, the use of display devices such as organic light emitting displays (OLEDs), liquid crystal displays (LCDs), and plasma display panels (PDPs) is increasing.

Among the display devices described above, an organic light emitting display device includes a display panel including a plurality of subpixels and a driver that drives the display panel. The driver includes a scan driver for supplying scan signals (or gate signals) to the display panel and a data driver for supplying data signals to the display panel.

In the organic light emitting display device, when a scan signal and a data signal are supplied to subpixels arranged in a matrix form, the selected subpixel emits light, thereby displaying an image.

The sub-pixel includes a switching transistor for transmitting a data signal, a capacitor for storing the data signal as a data voltage, a driving transistor for generating a driving current based on the data voltage, and an organic light emitting diode for emitting light in response to the driving current. A capacitor for storing the data voltage is composed of an insulating layer and a portion of an electrode positioned in a sub-pixel, such as a portion of a gate metal layer, a portion of a semiconductor layer, and a portion of a source-drain metal layer.

When a display panel is implemented with a high resolution (UHD or higher), the size of a sub-pixel becomes smaller than before. For this reason, the limit design value condition on the layout in which the circuit must be configured within the limited space of the sub-pixel rises. In this case, problems such as capacitors disappearing without being formed due to a short circuit between electrodes due to foreign matter or particles generated in the process (structural weakness) may occur, and improvement is required.

The present invention to solve the problems of the background art described above is the rise of the limit design value condition on the layout in which the circuit must be configured within the limited space of the sub-pixel when the display panel is implemented with a high resolution (UHD or higher) and foreign matter or particles generated in the process It is to solve the problem that a capacitor disappears without being formed due to the occurrence of a short circuit between electrodes.

As a means for solving the above problems, the present invention provides an organic light emitting display device capable of solving the problem of a capacitor disappearing without being formed due to a short circuit between electrodes caused by foreign matter or particles occurring in a process. The conductor region of the semiconductor layer is made of the semiconductor layer positioned on the first substrate and is conductive. The first insulating layer is located on the conductor region of the semiconductor layer. A gate metal layer is located on the first insulating layer. The second insulating layer has a contact hole exposing a portion of the gate metal layer. The source-drain metal layer is positioned on the second insulating layer and electrically connected to the gate metal layer through a contact hole. The conductor region of the semiconductor layer does not overlap with the gate metal layer.

The conductor region of the semiconductor layer and the source-drain metal layer may form a capacitor together with an insulating layer positioned therebetween.

The first insulating layer and the gate metal layer may have an island shape.

A separation space may be located between the conductor region of the semiconductor layer and the gate metal layer.

The conductor region of the semiconductor layer may have a shape surrounding the contact hole of the gate metal layer.

The first insulating layer may have a thickness smaller than that of the second insulating layer.

In the present invention, when a display panel is implemented with a high resolution (UHD or higher), capacitors are damaged due to an increase in the limit design value condition on the layout in which a circuit must be configured within a limited space of a sub-pixel and a short circuit between electrodes due to foreign matter or particles generated in the process. It has the effect of solving the problem of disappearing without being formed. In addition, the present invention has an effect of improving reliability or production yield of a display panel by removing or avoiding a fragile structure so that a capacitor in a sub-pixel is robust against foreign substances or particles.

1 is a schematic block diagram of an organic light emitting display device according to an embodiment of the present invention.
2 is a schematic circuit configuration diagram of a subpixel;
3 is an exemplary diagram of a first circuit configuration of a sub-pixel according to an embodiment of the present invention;
4 is an exemplary diagram of a second circuit configuration of a sub-pixel according to an embodiment of the present invention;
5 is a cross-sectional view of a display panel according to an embodiment of the present invention;
6 is a plan view illustrating a part of a sub-pixel according to an embodiment of the present invention;
FIG. 7 is a cross-sectional view of the area A1-A2 shown in FIG. 6;
8 is a plan view illustrating a part of a sub-pixel according to an experimental example;
9 is a cross-sectional view of the area B1-B2 shown in FIG. 8;
10 is a plan view showing a part of a sub-pixel according to an embodiment of the present invention;
FIG. 11 is a cross-sectional view of an area B1-B2 shown in FIG. 10;
12 is a view for comparing and explaining features between experimental examples and examples on a plane;
13 is a view for comparing and explaining characteristics between experimental examples and examples on a cross-section;

Hereinafter, specific details for the implementation of the present invention will be described with reference to the accompanying drawings.

1 is a schematic block diagram of an organic light emitting display device according to an embodiment of the present invention, FIG. 2 is a schematic circuit diagram of a subpixel, and FIG. 3 is a first block diagram of a subpixel according to an embodiment of the present invention. FIG. 4 is an exemplary diagram of a second circuit configuration of a sub-pixel according to an exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view of a display panel according to an exemplary embodiment of the present invention.

As shown in FIG. 1 , an organic light emitting display device according to an embodiment of the present invention includes an image processor 110, a timing controller 120, a data driver 130, a scan driver 140, and a display panel 150. This is included.

The image processor 110 outputs a data enable signal DE along with the data signal DATA supplied from the outside. The image processor 110 may output one or more of a vertical sync signal, a horizontal sync signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of description.

The timing controller 120 receives a data signal DATA along with a data enable signal DE or driving signals including a vertical synchronization signal, a horizontal synchronization signal, and a clock signal from the image processing unit 110 . The timing controller 120 generates a gate timing control signal (GDC) for controlling the operation timing of the scan driver 140 and a data timing control signal (DDC) for controlling the operation timing of the data driver 130 based on the driving signal. outputs

The data driver 130 samples and latches the data signal DATA supplied from the timing controller 120 in response to the data timing control signal DDC supplied from the timing controller 120, converts it into a gamma reference voltage, and outputs the result. . The data driver 130 outputs the data signal DATA through the data lines DL1 to DLn. The data driver 130 may be formed in the form of an integrated circuit (IC).

The scan driver 140 shifts the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 120 and outputs a scan signal. The scan driver 140 outputs scan signals through scan lines GL1 to GLm. The scan driver 140 is formed in the form of an integrated circuit (IC) or formed in the display panel 150 in a gate-in-panel method.

The display panel 150 displays an image in response to the data signal DATA and the scan signal supplied from the data driver 130 and the scan driver 140 . The display panel 150 includes sub-pixels SP that operate to display an image.

Sub-pixels are formed in a top-emission method, a bottom-emission method, or a dual-emission method, depending on the structure. The subpixels SP include a red subpixel, a green subpixel, and a blue subpixel, or include a white subpixel, a red subpixel, a green subpixel, and a blue subpixel. The subpixels SP may have one or more different light emitting areas according to light emitting characteristics.

As shown in FIG. 2, one sub-pixel includes a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light emitting diode OLED.

The switching transistor SW performs a switching operation to store the data signal supplied through the first data line DL1 as a data voltage in the capacitor Cst in response to the scan signal supplied through the first scan line GL1. The driving transistor DR operates to allow a driving current to flow between the first power line EVDD and the second power line EVSS according to the data voltage stored in the capacitor Cst. The organic light emitting diode OLED operates to emit light according to a driving current formed by the driving transistor DR.

The compensation circuit CC is a circuit added in the sub-pixel to compensate for the threshold voltage of the driving transistor DR. The compensation circuit (CC) is composed of one or more transistors. The configuration of the compensation circuit (CC) is very diverse according to the compensation method, and examples thereof are described as follows.

As shown in FIGS. 3 and 4 , the compensation circuit CC includes a sensing transistor ST and a sensing line VREF. The sensing transistor ST is connected between the source line of the driving transistor DR and the anode electrode of the organic light emitting diode OLED (hereinafter referred to as a sensing node). The sensing transistor ST supplies the initialization voltage (or sensing voltage) transmitted through the sensing line VREF to the sensing node or operates to sense the voltage or current of the sensing node.

In the switching transistor SW, a first electrode is connected to the first data line DL1 and a second electrode is connected to the gate electrode of the driving transistor DR. The driving transistor DR has a first electrode connected to the first power line EVDD and a second electrode connected to the anode electrode of the organic light emitting diode OLED. In the capacitor Cst, a first electrode is connected to the gate electrode of the driving transistor DR and a second electrode is connected to the anode electrode of the organic light emitting diode OLED. In the organic light emitting diode OLED, the anode electrode is connected to the second electrode of the driving transistor DR and the cathode electrode is connected to the second power supply line EVSS. In the sensing transistor ST, a first electrode is connected to the sensing line VREF and a second electrode is connected to the anode electrode of the organic light emitting diode (OLED) as a sensing node.

The operating time of the sensing transistor ST may be similar/identical to or different from that of the switching transistor SW according to a compensation algorithm (or configuration of a compensation circuit). For example, the gate electrode of the switching transistor SW may be connected to the first scan line GL1a, and the gate electrode of the sensing transistor ST may be connected to the first scan line GL1b. As another example, the 1a scan line GL1a connected to the gate electrode of the switching transistor SW and the 1b scan line GL1b connected to the gate electrode of the sensing transistor ST may be connected in common.

The sensing line VREF may be connected to the data driver. In this case, the data driver can sense the sensing node of the sub-pixel in real time, during a non-display period of an image or during a period of N frames (N is an integer greater than or equal to 1) and generate a sensing result. Meanwhile, the switching transistor SW and the sensing transistor ST may be turned on at the same time. In this case, based on the time division method of the data driver, a sensing operation through the sensing line VREF and a data output operation of outputting a data signal are separated (separated) from each other.

In addition, a compensation target according to the sensing result may be a digital type data signal, an analog type data signal, or gamma. Also, a compensation circuit that generates a compensation signal (or compensation voltage) based on a sensing result may be implemented as a data driver, a timing controller, or a separate circuit.

3 and 4, a 3T (Transistor) 1C (Capacitor) structure including a switching transistor (SW), a driving transistor (DR), a capacitor (Cst), an organic light emitting diode (OLED), and a sensing transistor (ST) Although the sub-pixel has been described as an example, when a compensation circuit (CC) is added, it may be composed of 3T2C, 4T2C, 5T1C, 6T2C, and the like.

Meanwhile, comparing the circuit of the subpixel of FIG. 3 with the circuit of the subpixel of FIG. 4, there is a difference in the configuration of the light blocking layer LS in the two circuits. The light blocking layer LS exists to block external light. When the light blocking layer LS is formed of a metallic material, a parasitic voltage is charged. Therefore, the light blocking layer LS is connected to the source electrode of the driving transistor DR.

Specifically, the light blocking layer LS is disposed only under the channel region of the driving transistor DR as shown in FIG. 3, or the light blocking layer LS is disposed not only under the channel region of the driving transistor DR as shown in FIG. It may also be disposed under the channel regions of the transistor SW and the sensing transistor ST.

The light blocking layer LS may be used simply to block external light (FIG. 3), or may be used as an electrode constituting a capacitor or the like to promote connection with other electrodes or lines.

As shown in FIG. 5 , subpixels are formed on the display area AA of the first substrate 150a based on the circuit described in FIG. 3 or FIG. 4 . Sub-pixels formed on the display area AA are sealed by a protective film (or protective substrate) 150b. Other unexplained NA means a non-display area.

The subpixels are horizontally or vertically arranged in the order of red (R), white (W), blue (B), and green (G) on the display area AA. In addition, red (R), white (W), blue (B), and green (G) of the sub-pixels become one pixel (P). However, the arrangement order of the subpixels may be variously changed according to the light emitting material, the light emitting area, the configuration (or structure) of the compensation circuit, and the like. In addition, red (R), blue (B), and green (G) of the sub-pixels may become one pixel (P).

FIG. 6 is a plan view illustrating a part of a subpixel according to an exemplary embodiment of the present invention, and FIG. 7 is a cross-sectional view of an area A1-A2 shown in FIG. 6 .

As shown in FIGS. 6 and 7 , the first to fourth subpixels SPn1 to SPn4 disposed in the horizontal direction form one pixel. For example, the first sub-pixel SPn1 is a red sub-pixel R, the second sub-pixel SPn2 is a white sub-pixel W, the third sub-pixel SPn3 is a blue sub-pixel B, The fourth sub-pixel SPn4 may be selected as a green sub-pixel G.

A first power line EVDD is disposed on the left side of the first sub-pixel SPn1 along the vertical direction. The first power line EVDD is commonly connected to the first sub-pixel SPn1 and the second sub-pixel SPn2. A first data line DLn1 and a second data line DLn2 are disposed in the vertical direction between the first subpixel SPn1 and the second subpixel SPn2 (WA). The first data line DLn1 is connected to the first sub-pixel SPn1, and the second data line DLn2 is connected to the second sub-pixel SPn2. "WA" is defined as a wiring area.

A sensing line VREF is disposed on the left side of the third sub-pixel SPn3 along the vertical direction. The sensing line VREF is commonly connected to the first sub-pixel SPn1 to the fourth sub-pixel SPn4. A third data line DLn3 and a fourth data line DLn4 are disposed in the vertical direction between the third and fourth sub-pixels SPn3 and SPn3 (WA). The third data line DLn3 is connected to the third sub-pixel SPn3, and the fourth data line DLn4 is connected to the fourth sub-pixel SPn4.

The scan line GL1 is disposed in the horizontal direction in the region of the sensing transistor ST included in the first sub-pixel SPn1 to the fourth sub-pixel SPn4 . The scan line GL1 is connected to gate electrodes of the sensing transistor ST and the switching transistor SW. The sensing line VREF includes a vertical sensing line VREFM disposed along a vertical direction and a horizontal sensing line VREFS disposed along a horizontal direction. The sensing transistors ST of the first sub-pixel SPn1 to the fourth sub-pixel SPn4 are connected to the vertical sensing line VREFM via the horizontal sensing line VREFS.

A cross-sectional structure of the display panel will be described by taking a part of the first sub-pixel SPn1 as an example.

A light blocking layer 151 is formed on the first substrate 150a. The light blocking layer 151 is formed to correspond to the channel region of the driving transistor DR or is separately formed to correspond to the channel regions of the driving transistor DR, the sensing transistor ST, and the switching transistor SW.

A buffer layer 152 and a semiconductor layer 153 are formed on the light blocking layer 151 . After the light blocking layer 151, the buffer layer 152, and the semiconductor layer 153 are sequentially stacked on the first substrate 150a, they may all be patterned in an island shape (batch pattern) using the same mask. The illustrated semiconductor layer 153 is a semiconductor layer of the driving transistor DR and is composed of an oxide semiconductor layer (eg, IGZO). In addition, portions corresponding to the source and drain regions of the semiconductor layer 153, except for the portion corresponding to the channel region, are made into conductors to become metal electrodes or wires. The conductorization process may use a plasma or an etching process, but is not limited thereto.

A first insulating layer 154 is formed on the semiconductor layer 153 , and a gate metal layer 155 is formed on the first insulating layer 154 . The first insulating layer 154 may be defined as a gate insulating layer, which may be patterned in the same island shape as the gate electrode (or gate metal layer) formed thereon. The first insulating layer 154 may be selected from among silicon (Si)-based SiO2, SiNx, and SiON.

The gate metal layer 155 is used as a gate electrode of the driving transistor DR of the first sub-pixel SPn1. In addition, the gate metal layer 155 is used as an electrode electrically connecting the first to fourth sub-pixels SPn1 to SPn4 and the first power line EVDD.

A second insulating layer 156 is formed on the gate metal layer 155 . The second insulating layer 156 may be defined as an interlayer insulating layer that electrically insulates between a lower structure and an upper structure. A plurality of contact holes exposing a part of the lower structure are formed in the second insulating layer 156 . A plurality of contact holes are formed by a hole mask.

A source-drain metal layer 157 is formed on the second insulating layer 156 . The source-drain metal layer 157 is a line constituting the first power line EVDD, data lines DLn1 to DLn4, and sensing line VREF, and electrodes constituting transistors and capacitors included in sub-pixels, respectively. Separated.

Referring to a portion of the driving transistor DR corresponding to a portion of the source-drain metal layer 157, a portion of the source-drain metal layer 157 is connected to the semiconductor layers 153s and 153d in the source and drain regions, which is the driving transistor ( DR) becomes the source electrode 157s and the drain electrode 157d. The semiconductor layer 153a of the channel region is protected by the light blocking layer 151 .

A third insulating layer 158 is formed on the source-drain metal layer 157 . The third insulating layer 158 may be defined as a protective layer for protecting structures such as transistors formed on the first substrate 150a.

A color filter 159 is formed on the third insulating layer 158 to correspond to the opening area. When an organic light emitting diode formed below emits white light, a color filter 159 is formed on the third insulating layer 158 . However, when the organic light emitting diode emits colored light such as red, green, and blue, the color filter 159 is not formed on the third insulating layer 158 .

A fourth insulating layer 160 is formed on the third insulating layer 158 . The fourth insulating layer 160 may be defined as a coating layer that flattens the surface. The third insulating layer 158 and the fourth insulating layer 160 are the source electrode 157s (or drain electrode; since there are P-type and N-type transistors, and the source and drain electrodes vary depending on their type), It has a contact hole partially exposed.

A pixel electrode 161 is formed on the fourth insulating layer 160 . The pixel electrode 161 may be defined as an anode electrode of an organic light emitting diode. The pixel electrode 161 is electrically connected to the source electrode 157s exposed through the fourth insulating layer 160 . The pixel electrode 161 may be selected as a transparent electrode to emit light emitted from the organic emission layer toward the first substrate 150a.

A bank layer 162 is formed on the fourth insulating layer 160 . The bank layer 162 has an opening area exposing a part of the pixel electrode 161 and defines an actual light emitting area.

An organic emission layer 163 is formed on the bank layer 162 . The organic light emitting layer 163 is a layer that emits light, and may emit colored light such as white, red, green, or blue. In addition to the emission layer, the organic light emitting layer 163 may further include functional layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer, or a compensation layer such as a hole blocking layer and an interface buffer layer.

An upper electrode 164 is formed on the organic light emitting layer 163 . The upper electrode 164 may be defined as a cathode electrode of an organic light emitting diode. The upper electrode 164 is electrically connected to a second power line (not shown). The upper electrode 164 may be selected as an opaque electrode so that light emitted from the organic emission layer is emitted only in the direction of the first substrate 150a. However, depending on the purpose and function of the display panel, the upper electrode 164 may also be a transparent electrode in order to emit light emitted from the organic light emitting layer in the opposite direction to the first substrate 150a.

A capacitor Cst is formed inside each of the first sub-pixel SPn1 to the fourth sub-pixel SPn4 . The capacitor Cst may be formed in a single-layer or multi-layer structure using a portion of a light blocking layer, a portion of a gate metal layer, a portion of a semiconductor layer, a portion of a source-drain metal layer, a portion of a pixel electrode, and an insulating layer positioned therebetween. .

When a display panel is implemented with a high resolution (UHD or higher), the size of a sub-pixel becomes smaller than before. The size of the sub-pixel becomes smaller compared to the previous one. For this reason, the limit design value condition on the layout in which the circuit must be configured within the limited space of the sub-pixel rises. In this case, the possibility of a short circuit between electrodes increases due to foreign matter or particles generated in the process, and structural problems (structural weakness) may occur, such as capacitors disappearing without being formed.

Hereinafter, an experimental example in which a problem related to the above occurs is considered, and a structure of an embodiment capable of improving it will be described.

8 is a plan view showing a portion of a subpixel according to an experimental example, FIG. 9 is a cross-sectional view of a region B1-B2 shown in FIG. 8, and FIG. 10 is a plan view showing a portion of a subpixel according to an embodiment of the present invention. , FIG. 11 is a cross-sectional view of the B1-B2 region shown in FIG. 10, FIG. 12 is a view for comparing and explaining features between experimental examples and examples on a plane, and FIG. 13 is a cross-sectional view of features between experimental examples and examples. It is a drawing for comparative explanation.

-Experimental example-

As shown in FIGS. 8, 9, 12(a) and 13(b), in the experimental example, a portion of the semiconductor layer 153M of the driving transistor DR is used as the lower electrode of the capacitor Cst. and a part of the source-drain metal layer 157 of the driving transistor DR is formed as an upper electrode of the capacitor Cst.

The gate electrode of the driving transistor DR and the upper electrode of the capacitor Cst are electrically connected by using a part of the gate metal layer 155 constituting the gate electrode of the driving transistor DR. That is, the portion 155 of the gate metal layer serves as a gate electrode of the driving transistor DR and a connection electrode electrically connecting the gate electrode of the driving transistor DR and the upper electrode of the capacitor Cst.

Hereinafter, the source region and the drain region, which are parts of the semiconductor layer 153M of the driving transistor DR, correspond to a portion changed to a conductor instead of a semiconductor layer by becoming a conductor. .

A structure positioned at a portion constituting the capacitor Cst will be described with reference to some cross-sections of the experimental example.

A conductor region 153M of a semiconductor layer is formed on the buffer layer 152 covering the first substrate 150a. A first insulating layer 154 positioned in an island shape is formed on the conductor region 153M of the semiconductor layer. A gate metal layer 155 is formed on the first insulating layer 154 . A second insulating layer 156 having a contact hole exposing a part of the gate metal layer 155 is formed on the gate metal layer 155 . A source-drain metal layer 157 electrically connected to the gate metal layer 155 through a contact hole is formed on the second insulating layer 156 .

In the experimental example, the conductor region 153M of the semiconductor layer has a shape covering the contact hole of the gate metal layer 155 serving as a connection electrode and its surroundings.

Meanwhile, the capacitance of the capacitor Cst is determined corresponding to an overlapping region existing between a portion of the conductor region 153M of the semiconductor layer and a portion of the source-drain metal layer 157 corresponding to the upper electrode.

The first insulating layer 154 is formed thinner than the second insulating layer 156 in order to satisfy high-resolution process requirements, such as improving driving performance of a top-gate driving transistor. In this case, in order to compensate/compensate for the thin thickness of the first insulating layer 154, the thickness of the second insulating layer 154 is formed to be at least twice as thick as the thickness of the first insulating layer 154. For example, the first insulating layer 154 may have a thickness of 300 Å to 2500 Å, and the second insulating layer 156 may have a thickness of 4000 Å to 6000 Å.

Under the above conditions, the driving capability of the top-gate driving transistor is improved, but the separation distance between a part of the gate metal layer 155 located in the region where the capacitor Cst is formed and the conductor region 153M of the semiconductor layer is reduced.

As a result, in the experimental example, when a foreign substance or particle PT generated in the process is present in the vicinity (especially the lower part) of the first insulating layer 154 located in the region where the capacitor Cst is formed, it serves as a connection electrode. A short circuit occurs between the gate metal layer 155 and the conductor region 153M of the semiconductor layer, so that the capacitor Cst disappears without being formed. That is, by the above conditions, the driving ability of the top-gate driving transistor is improved, but the reliability or production yield of the display panel may decrease due to a structural problem (structural weakness) of the electrode part forming the capacitor Cst. can cause

- Examples -

As shown in FIGS. 10, 11, 12(b) and 13(b), in the exemplary embodiment, a portion of the semiconductor layer 153M of the driving transistor DR is used as a lower electrode of the capacitor Cst. and a part of the source-drain metal layer 157 of the driving transistor DR is formed as an upper electrode of the capacitor Cst.

The gate electrode of the driving transistor DR and the upper electrode of the capacitor Cst are electrically connected by using a part of the gate metal layer 155 constituting the gate electrode of the driving transistor DR. That is, the portion 155 of the gate metal layer serves as a gate electrode of the driving transistor DR and a connection electrode electrically connecting the gate electrode of the driving transistor DR and the upper electrode of the capacitor Cst.

Hereinafter, the source region and the drain region, which are parts of the semiconductor layer 153M of the driving transistor DR, correspond to a portion changed to a conductor instead of a semiconductor layer by becoming a conductor. .

A structure positioned at a portion constituting the capacitor Cst will be described with reference to some cross-sections of the embodiment.

A conductor region 153M of a semiconductor layer is formed on the buffer layer 152 covering the first substrate 150a. A first insulating layer 154 positioned in an island shape is formed on the conductor region 153M of the semiconductor layer. A gate metal layer 155 is formed on the first insulating layer 154 . A second insulating layer 156 having a contact hole exposing a part of the gate metal layer 155 is formed on the gate metal layer 155 . A source-drain metal layer 157 electrically connected to the gate metal layer 155 through a contact hole is formed on the second insulating layer 156 .

In the experimental example, the conductor region 153M of the semiconductor layer has a shape surrounding the contact hole of the gate metal layer 155 serving as a connection electrode and its periphery.

Meanwhile, the capacitance of the capacitor Cst is determined corresponding to an overlapping region existing between a portion of the conductor region 153M of the semiconductor layer and a portion of the source-drain metal layer 157 corresponding to the upper electrode.

The first insulating layer 154 is formed thinner than the second insulating layer 156 in order to satisfy high-resolution process requirements, such as improving driving performance of a top-gate driving transistor. In this case, in order to compensate/compensate for the thin thickness of the first insulating layer 154, the thickness of the second insulating layer 154 is formed to be at least twice as thick as the thickness of the first insulating layer 154. For example, The first insulating layer 154 may have a thickness of 300 Å to 2500 Å, and the second insulating layer 156 may have a thickness of 4000 Å to 6000 Å. At this time, if the thickness of the first insulating layer 154 is thin, such as 300 Å to 2500 Å, the driving ability of the driving transistor (improvement of current mobility, uniformity of transistor on-voltage, etc.) can be improved.

Under the above conditions, the driving capability of the top-gate driving transistor is improved, but the separation distance between a portion of the gate metal layer 155 located in the region where the capacitor Cst is formed and the conductor region 153M of the semiconductor layer is reduced.

However, in the embodiment, a part of the conductor region 153M of the semiconductor layer located in the region overlapping the gate metal layer 155 serving as a connection electrode is patterned and removed to solve the problem shown in the experimental example. That is, by patterning a part of the conductor region 153M of the semiconductor layer so that the gate metal layer 155 serving as a connection electrode and the conductor region 153M of the semiconductor layer do not overlap in the vertical direction (cross-section), the overlapping region between the two electrodes is formed. Remove.

At this time, the conductor region 153M of the semiconductor layer and the gate metal layer 155 serving as a connection electrode have spaces (L1 and L2 in FIG. 12B) spaced apart from each other in the horizontal direction (on a plane). (153M) can be deeply patterned. In this case, even if there are foreign substances or particles (PT) generated in the process, a short circuit that may occur outside the conductor region 153M of the semiconductor layer and the gate metal layer 155 serving as a connection electrode can also be removed.

As a result, the embodiment serves as a connection electrode even if foreign substances or particles PT generated in the process are present in the vicinity (especially the lower part) of the first insulating layer 154 located in the region where the capacitor Cst is formed. Since a short circuit between the gate metal layer 155 and the conductor region 153M of the semiconductor layer does not occur, the problem of the capacitor Cst eventually disappearing is solved. That is, by the above conditions, the driving ability of the top-gate driving transistor is improved, and the structural problem (structural weakness) of the electrode part forming the capacitor Cst is also solved, so that the reliability or production yield of the display panel may decrease. The problem goes away.

As can be seen through the comparison between the experimental example and the embodiment, the reason for the same problem as in the experimental example is that the thickness of the first insulating layer 154 is greater than that of the second insulating layer 156 in order to improve the driving ability of the top-gate driving transistor. When forming thin (for example, 300 Å ~ 2500 Å), the frequency of occurrence increases. Therefore, in the embodiment of the present invention, problems that may occur between the upper and lower electrodes constituting the capacitor can be improved by reducing the thickness of the first insulating layer corresponding to the gate insulating film. It will also be applicable to capacitors of the form.

On the other hand, when there is an overlapping region between the gate metal layer 155 serving as a connection electrode and the conductor region 153M of the semiconductor layer, as in the experimental example, capacitance is formed between them to accurately calculate the actual capacitance of the capacitor Cst. There was a problem that was difficult to do (because the capacitance of the capacitor changes depending on the potential applied to the gate electrode).

However, when there is no overlapping region between the gate metal layer 155 serving as a connection electrode and the conductor region 153M of the semiconductor layer, as in the embodiment, capacitance is not formed between them, thereby reducing the actual capacitance of the capacitor Cst. can be calculated relatively accurately.

As can be seen through the comparison between (a) of FIG. 12 and (b) of FIG. 12, the embodiment removes the overlapping region between the gate metal layer 155 serving as a connection electrode and the conductor region 153M of the semiconductor layer, and these Separation spaces (L1, L2) between the two are formed to solve problems that may occur in the process.

At this time, the separation spaces (L1, L2) between the gate metal layer 155 serving as a connection electrode and the conductor region 153M of the semiconductor layer are L1 = L2, L1 ≠ L2, L1 > L2, L1 < L2 and may vary together. As separation spaces (L1, L2) are formed between the gate metal layer 155 serving as a connection electrode and the conductor region 153M of the semiconductor layer, the conductor region 153M of the semiconductor layer is connected to the gate metal layer 155 serving as a connection electrode. It has a shape surrounding the periphery of the contact hole of

As described above, when the display panel of the present invention is implemented with a high resolution (UHD or higher), the limit design value condition on the layout in which circuits must be configured within the limited space of the sub-pixel increases and the occurrence of a short circuit between electrodes due to foreign matter or particles occurring in the process causes the capacitor to It has the effect of solving the problem of disappearing without being formed. In addition, the present invention has an effect of improving reliability or production yield of a display panel by removing or avoiding a fragile structure so that a capacitor in a sub-pixel is robust against foreign substances or particles.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the above-described technical configuration of the present invention can be changed into other specific forms by those skilled in the art without changing the technical spirit or essential features of the present invention. It will be appreciated that this can be implemented. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

110: image processing unit 120: timing control unit
130: data driving unit 140: scan driving unit
150: display panel 153: semiconductor layer
154: first insulating layer 155: gate metal layer
156: second insulating layer 157: source drain metal layer
DR: driving transistor 153M: conductor region of the semiconductor layer

Claims (6)

a first substrate;
a conductor region of a semiconductor layer made of a semiconductor layer positioned on the first substrate but made conductive;
a first insulating layer located on the same layer as the conductor region of the semiconductor layer;
a gate metal layer positioned on the first insulating layer;
a second insulating layer having a contact hole exposing a portion of the gate metal layer; and
a source-drain metal layer disposed on the second insulating layer and electrically connected to the gate metal layer through the contact hole;
As a separation space is formed between the conductor region of the semiconductor layer and the gate metal layer, the conductor region of the semiconductor layer does not overlap with the gate metal layer,
The conductor region of the semiconductor layer and the source-drain metal layer are
forming a capacitor with an insulating layer located between them;
The first insulating layer and the gate metal layer have an island shape,
The first insulating layer has a thickness thinner than the second insulating layer,
The conductor region of the semiconductor layer has a shape surrounding at least three surfaces of the contact hole of the gate metal layer,
The gate metal layer is disposed in a vertical direction parallel to the data lines disposed on the first substrate, and the length of the gate metal layer disposed on the first subpixel in the vertical direction and the length of the gate metal layer disposed on the second subpixel in the vertical direction An organic light emitting display device having different lengths. delete delete delete delete delete

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