KR20240107752A - Display Device and Method for Manufacturing thereof - Google Patents

Abstract

This embodiment includes a substrate including a first transistor area and a capacitor area; a light blocking layer located on the substrate and including a lower electrode of a lower capacitor; a buffer layer located on the substrate and covering the light blocking layer; a lower semiconductor layer located on the buffer layer, overlapping the lower electrode of the lower capacitor, and including an active region and a partially conductive region to become an upper electrode of the lower capacitor and a lower electrode of the upper capacitor; a first insulating layer located on the buffer layer and covering the lower semiconductor layer; an upper semiconductor layer located on the first insulating layer, overlapping a conductive region of the lower semiconductor layer, and including an active region and a partially conductive region to serve as an upper electrode of the upper capacitor; and a second insulating layer located on the first insulating layer and covering the upper semiconductor layer.

Description

Display device and method for manufacturing thereof}

This specification relates to a display device and a method of manufacturing the same.

As information technology develops, the market for display devices, which are a connecting medium between users and information, is growing. Accordingly, the use of display devices such as Light Emitting Display Device (LED), Quantum Dot Display Device (QDD), and Liquid Crystal Display Device (LCD) is increasing.

The display devices described above include a display panel including subpixels, a driver that outputs a driving signal to drive the display panel, and a power supply that generates power to be supplied to the display panel or the driver.

The above display devices can display images by transmitting light or directly emitting light through the selected subpixels when driving signals, such as scan signals and data signals, are supplied to the subpixels formed on the display panel.

This embodiment can implement a multi-layer capacitor with a simplified process and configuration, and improves compensation performance and image quality characteristics by eliminating or reducing parasitic capacitance that may appear around the driving transistor and data line, as well as pattern density. The goal is to improve yield by lowering .

This embodiment includes a substrate including a first transistor area and a capacitor area; a light blocking layer located on the substrate and including a lower electrode of a lower capacitor; a buffer layer located on the substrate and covering the light blocking layer; a lower semiconductor layer located on the buffer layer, overlapping the lower electrode of the lower capacitor, and including an active region and a partially conductive region to become an upper electrode of the lower capacitor and a lower electrode of the upper capacitor; a first insulating layer located on the buffer layer and covering the lower semiconductor layer; an upper semiconductor layer located on the first insulating layer, overlapping a conductive region of the lower semiconductor layer, and including an active region and a partially conductive region to serve as an upper electrode of the upper capacitor; and a second insulating layer located on the first insulating layer and covering the upper semiconductor layer.

A gate electrode layer located on the second insulating layer and overlapping the active area of the upper semiconductor layer, a third insulating layer located on the second insulating layer and covering the gate electrode layer, and located on the third insulating layer. It may include a lower source drain electrode layer.

The lower source and drain electrode layer includes a first lower source and drain electrode layer in contact with the conductive region of the lower semiconductor layer, a second lower source and drain electrode layer in contact with the gate electrode layer, and a second lower source and drain electrode layer in contact with the conducted region of the upper semiconductor layer. It may include a third lower source drain electrode layer.

a first planarization layer located on the third insulating layer and covering the first lower, second lower and third lower source and drain electrode layers; and a first planarization layer located on the first planarization layer and connected to the third lower source and drain electrode layer. It may include an upper source drain electrode layer.

In another aspect, the present invention includes a first transistor having a gate electrode connected to a first scan signal line and a first electrode connected to a first data line; a driving transistor whose gate electrode is connected to the second electrode of the first transistor and which generates a driving current to drive a light emitting diode; a first capacitor having a first electrode connected to a second electrode of the first transistor and a gate electrode of the driving transistor and a second electrode connected to the second electrode of the driving transistor; A second capacitor having a first electrode connected to a second electrode of the first capacitor and a second electrode of the driving transistor and a second electrode connected to a first voltage line, wherein the first transistor, the driving transistor, and the first electrode are connected to the first voltage line. The first capacitor and the second capacitor include a light blocking layer located on the substrate and including the second electrode of the second capacitor, a buffer layer located on the substrate and covering the light blocking layer, and a first capacitor located on the buffer layer and including the second electrode of the second capacitor. A lower semiconductor layer including a region that overlaps two electrodes and is partially conductive to become the first electrode of the second capacitor and the second electrode of the first capacitor, and the active region of the driving transistor, on the buffer layer. A first insulating layer located on the first insulating layer and covering the lower semiconductor layer, a region located on the first insulating layer and overlapping the conductive region of the lower semiconductor layer, a portion of which is conductive to become the first electrode of the first capacitor, and A display device can be provided including an upper semiconductor layer including an active area of a first transistor, and a second insulating layer located on the first insulating layer and covering the upper semiconductor layer.

A gate electrode layer located on the second insulating layer and overlapping the active area of the upper semiconductor layer, a third insulating layer located on the second insulating layer and covering the gate electrode layer, and located on the third insulating layer. It may include a lower source drain electrode layer.

A first planarization layer located on the third insulating layer and covering the first lower, second lower and third lower source and drain electrode layers, and a first planarization layer located on the first planarization layer and connected to the third lower source and drain electrode layer. and may include an upper source and drain electrode layer that serves as the first data line.

In another aspect, the present invention includes forming a light blocking layer including a lower electrode of a lower capacitor on a substrate; forming a buffer layer covering the light blocking layer on the substrate; Forming a lower semiconductor layer on the buffer layer that overlaps the lower electrode of the lower capacitor and includes an active region of the driving transistor and a region partially conductive to become the upper electrode of the lower capacitor and the lower electrode of the upper capacitor. step; forming a first insulating layer covering the lower semiconductor layer on the buffer layer; Forming an upper semiconductor layer on the first insulating layer that overlaps the conductive region of the lower semiconductor layer and includes a partially conductive region to become an upper electrode of the upper capacitor and an active region of the first transistor. ; and forming a second insulating layer on the first insulating layer to cover the upper semiconductor layer.

The conductive regions of the lower semiconductor layer and the upper semiconductor layer may be collectively conductive through a doping process.

The lower capacitor and the upper capacitor are connected in series, the lower electrode of the lower capacitor is in contact with the first voltage line, and the upper electrode of the upper capacitor is connected to the gate electrode of the driving transistor and the second electrode of the first transistor. can be contacted.

This embodiment can implement a multi-layer capacitor with a simplified process and configuration, and has the effect of improving compensation performance and improving image quality characteristics by removing or reducing parasitic capacitance that may appear around the driving transistor and data line. there is. In addition, this embodiment has the effect of improving vertical crosstalk and ghost mura by removing or reducing parasitic capacitance, as well as improving the phenomenon of vertical gradient staining. In addition, this embodiment has the effect of improving yield by lowering the pattern density of the source-drain electrode layer and semiconductor layer based on a simplified process and configuration, as well as reducing investment costs for equipment required for processing and manufacturing. there is.

FIG. 1 is a block diagram schematically showing a light emitting display device, and FIG. 2 is a block diagram schematically showing a subpixel according to a first embodiment.
Figures 3 and 4 are diagrams for explaining the configuration of a gate-in-panel type gate driver, and Figure 5 is a diagram showing an example of the arrangement of a gate-in-panel type gate driver.
FIG. 6 is a cross-sectional view showing an area where the driving transistor is located in the subpixel of FIG. 2 according to the first embodiment, and FIG. 7 is an area where the first transistor and capacitors are located in the subpixel of FIG. 2 according to the first embodiment. This is a cross-sectional view showing.
FIG. 8 is a circuit diagram showing the configuration of a subpixel according to a second embodiment, FIG. 9 is a plan view showing the arrangement of components included in the subpixel of FIG. 8, and FIG. 10 is a cross-sectional view showing area A1-A2 in FIG. 9. , and FIG. 11 is a cross-sectional view showing area B1-B2 in FIG. 9.
FIG. 12 is a plan view showing the arrangement of components included in the subpixel of FIG. 8 according to the third embodiment, and FIGS. 13 and 24 are diagrams showing the manufacturing of a light emitting display device including the subpixel of FIG. 12 according to the third embodiment. These are process flow charts to explain the method.

The display device according to this embodiment can be implemented as a television, video player, personal computer (PC), home theater, automobile electric device, smartphone, etc., but is not limited thereto. The display device according to this embodiment may be implemented as a light emitting display device (LED), a quantum dot display device (QDD), a liquid crystal display device (LCD), etc. However, hereinafter, for convenience of explanation, a light emitting display device that directly emits light based on an inorganic light emitting diode or an organic light emitting diode is taken as an example.

In addition, the subpixel described below includes an n-type thin film transistor as an example, but it may also be implemented as a p-type thin film transistor or a combination of n-type and p-type. A thin film transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within a thin film transistor, carriers begin to flow from a source. The drain is the electrode through which carriers go out in a thin film transistor. That is, in a thin film transistor, carriers flow from the source to the drain.

In the case of a p-type thin film transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type thin film transistor, current flows from the source to the drain because holes flow from the source to the drain. On the other hand, in the case of an n-type thin film transistor, since the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-type thin film transistor, since electrons flow from the source to the drain, the direction of current flows from the drain to the source. However, the source and drain of a thin film transistor can change depending on the applied voltage. Reflecting this, in the following description, one of the source and drain will be described as the first electrode, and the other one of the source and drain will be described as the second electrode.

FIG. 1 is a block diagram schematically showing a light emitting display device, and FIG. 2 is a block diagram schematically showing a subpixel according to a first embodiment.

As shown in Figures 1 and 2, the light emitting display device includes an image supply unit 110, a timing control unit 120, a gate driver 130, a data driver 140, a display panel 150, and a power supply unit 180. It may include etc.

The image supply unit (set or host system) 110 can output various driving signals in addition to image data signals supplied from outside or image data signals (image data signals) stored in internal memory. The image supply unit 110 may supply data signals and various driving signals to the timing control unit 120.

The timing control unit 120 includes a gate timing control signal (GDC) for controlling the operation timing of the gate driver 130, a data timing control signal (DDC) for controlling the operation timing of the data driver 140, and various synchronization signals ( The vertical synchronization signal (VSYNC) and the horizontal synchronization signal (HSYNC) can be output. The timing control unit 120 may supply the data signal DATA supplied from the image supply unit 110 together with the data timing control signal DDC to the data driver 140. The timing control unit 120 may be formed in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited to this.

The gate driver 130 may output a gate signal (or gate voltage) in response to a gate timing control signal (GDC) supplied from the timing control unit 120. The gate driver 130 may supply a gate signal to subpixels included in the display panel 150 through the gate lines GL1 to GLm. The gate driver 130 may be formed in the form of an IC or directly on the display panel 150 using a gate in panel method, but is not limited thereto.

The data driver 140 samples and latches the data signal (DATA) in response to the data timing control signal (DDC) supplied from the timing control unit 120 and converts the digital data signal into analog data based on the gamma reference voltage. It can be converted to voltage and output. The data driver 140 may supply a data voltage to subpixels included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 may be formed in the form of an IC and mounted on the display panel 150 or on a printed circuit board, but is not limited thereto.

The power supply unit 180 may generate a high potential voltage and a low potential voltage based on an external input voltage supplied from the outside, and output them through the first voltage line (EVDD) and the second voltage line (EVSS). The power supply unit 180 may generate and output not only a high potential voltage and a low potential voltage, but also a voltage necessary to drive the gate driver 130 or a voltage necessary to drive the data driver 140.

The display panel 150 can display an image in response to a driving signal including a gate signal and a data voltage, and a driving voltage including a high potential voltage and a low potential voltage. Subpixels of the display panel 150 directly emit light. Subpixels that emit light may be composed of pixels containing red, green, and blue colors or pixels containing red, green, blue, and white.

For example, the subpixel SP may be connected to the first data line DL1, the first gate line GL1, the first voltage line EVDD, and the second voltage line EVSS. One subpixel (SP) includes an organic light emitting diode that emits light, as well as a first transistor (T1), a driving transistor (DT), a first capacitor (C1), and a second capacitor (C2) for driving the organic light emitting diode. can do.

Sub-pixels (SP) used in light-emitting displays directly emit light, so the circuit configuration is complex. In addition, there are various compensation circuits that compensate for the deterioration of not only the organic light-emitting diode that emits light, but also the driving transistor (DT) that supplies driving current to the organic light-emitting diode. Therefore, please refer to the fact that the subpixel SP is simply shown in the form of a block.

In addition, in the above description, the timing control unit 120, gate driver 130, data driver 140, etc. were described as if they were individual components. However, depending on the implementation method of the light emitting display device, one or more of the timing control unit 120, gate driver 130, and data driver 140 may be integrated into one IC.

Figures 3 and 4 are diagrams for explaining the configuration of a gate-in-panel type gate driver, and Figure 5 is a diagram showing an example of the arrangement of a gate-in-panel type gate driver.

As shown in FIG. 3, the gate-in-panel type gate driver 130 may include a shift register 131 and a level shifter 135. The level shifter 135 may generate clock signals Clks and a start signal Vst based on signals and voltages output from the timing control unit 120 and the power supply unit 180. The shift register 131 operates based on the clock signals (Clks) and the start signal (Vst) output from the level shifter 135 and can output gate signals (Gout[1] to Gout[m]). there is.

As shown in Figures 3 and 4, unlike the shift register 131, the level shifter 135 may be formed independently in the form of an IC or may be included inside the power supply unit 180. However, this is only an example and is not limited to this.

As shown in FIG. 5, the first and second shift registers 131a and 131b that output gate signals from the gate-in-panel type gate driver may be disposed in the non-display area (NA) of the display panel 150. . The first and second shift registers 131a and 131b may be formed in a thin film form on the display panel 150 using a gate-in-panel method. The first and second shift registers 131a and 131b are shown as an example of being disposed in the left and right non-display areas (NA) of the display panel 150, but the present invention is not limited thereto.

FIG. 6 is a cross-sectional view showing an area where the driving transistor is located in the subpixel of FIG. 2 according to the first embodiment, and FIG. 7 is an area where the first transistor and capacitors are located in the subpixel of FIG. 2 according to the first embodiment. This is a cross-sectional view showing.

As shown in FIG. 6, a driving transistor DT may be formed in the area where the driving transistor is located (driving transistor area) as follows.

A first light blocking layer 151a may be located on the first substrate 150a. The first light blocking layer 151a may serve to block external light from entering through the first substrate 150a. A buffer layer 152 covering the first light blocking layer 151a may be positioned on the first substrate 150a.

A first lower semiconductor layer 153a may be located on the buffer layer 152. The first lower semiconductor layer 153a may be selected as oxide. The first lower semiconductor layer 153a may be an active layer (or active area) of the driving transistor DT. A first insulating layer 154 covering the first lower semiconductor layer 153a may be positioned on the buffer layer 152. The first insulating layer 154 may be a gate insulating layer of the driving transistor DT.

A first upper semiconductor layer 155a may be located on the first insulating layer 154. The first upper semiconductor layer 155a may be selected as oxide. The first upper semiconductor layer 155a may be selected as the gate node of the driving transistor DT. A second insulating layer 156 covering the first upper semiconductor layer 155a may be positioned on the first insulating layer 154.

A first gate electrode layer 157a may be located on the second insulating layer 156. The first gate electrode layer 157a may be the gate electrode of the driving transistor DT. A third insulating layer 158 covering the first gate electrode layer 157a may be located on the second insulating layer 156. The third insulating layer 158 may be an interlayer insulating layer.

A first lower source and drain electrode layer 159a may be located on the third insulating layer 158. The first lower source and drain electrode layer 159a may be a source electrode or a drain electrode of the driving transistor DT. The first planarization layer 160 may be located on the third insulating layer 158. The second planarization layer 163 may be located on the first planarization layer 160.

As shown in FIG. 7, in the area where the first transistor and capacitors are located (first transistor and capacitor area), capacitors C1, C2, etc. connected in series with the first transistor T1 will be formed as follows. You can.

A second light blocking layer 151b may be located on the first substrate 150a. The second light blocking layer 151b may be the lower electrode of the second capacitor C2. A buffer layer 152 covering the second light blocking layer 151b may be positioned on the first substrate 150a.

A second lower semiconductor layer 153b that overlaps the second light blocking layer 151b may be located on the buffer layer 152. The second lower semiconductor layer 153b may be selected as oxide. A portion of the second lower semiconductor layer 153b (the area overlapping the second light blocking layer) may become an electrode through a conductive process. The second lower semiconductor layer 153b may become the upper electrode of the second capacitor C2 and the lower electrode of the first capacitor C1. A first insulating layer 154 covering the second lower semiconductor layer 153b may be located on the buffer layer 152.

A second upper semiconductor layer 155b that overlaps the second lower semiconductor layer 153b may be located on the first insulating layer 154. The second upper semiconductor layer 155b may be selected as oxide. A portion of the second upper semiconductor layer 155b (a region overlapping with the second lower semiconductor layer) may become an electrode through a conductive process. A portion of the second upper semiconductor layer 155b that becomes an electrode may become the upper electrode of the first capacitor C1, and the other portion (non-conducting active area) may become an active layer of the first transistor T1. You can. A second insulating layer 156 covering the second upper semiconductor layer 155b may be positioned on the first insulating layer 154. The second insulating layer 156 may be a gate insulating layer of the first transistor T1.

A second gate electrode layer 157b may be located on the second insulating layer 156. The second gate electrode layer 157b may be the gate electrode of the first transistor T1. A third insulating layer 158 covering the second gate electrode layer 157b may be located on the second insulating layer 156. The third insulating layer 158 may be an interlayer insulating layer.

A second lower source and drain electrode layer (159b), a third lower source and drain electrode layer (159c), and a fourth lower source and drain electrode layer (159d) may be located on the third insulating layer 158. The second lower source-drain electrode layer 159b may serve as a first connection electrode connecting the first capacitor C1 and the first transistor T1. The third lower source-drain electrode layer 159c may be a second connection electrode that connects the gate electrode of the first transistor T1 to another electrode or line. The fourth lower source and drain electrode layer 159d may be the source or drain electrode of the first transistor (T1). The first planarization layer 160 may be located on the third insulating layer 158.

A first upper source and drain electrode layer 161 may be located on the first planarization layer 160. The first upper source and drain electrode layer 161 may be a third connection electrode that connects the source or drain electrode of the first transistor (T1) to another electrode or line. A second planarization layer 163 covering the first upper source and drain electrode layer 161 may be positioned on the first planarization layer 160.

Meanwhile, since the second capacitor C2 is located in a lower layer than the first capacitor C1, the second capacitor C2 may be defined as the lower capacitor and the first capacitor C1 may be defined as the upper capacitor.

FIG. 8 is a circuit diagram showing the configuration of a subpixel according to a second embodiment, FIG. 9 is a plan view showing the arrangement of the components included in the subpixel of FIG. 8, and FIG. 10 is a cross-sectional view showing area A1-A2 in FIG. 9. , and FIG. 11 is a cross-sectional view showing area B1-B2 in FIG. 9.

As shown in FIG. 8, the subpixel includes a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), and a driving transistor (DT). ), a first capacitor (C1), a second capacitor (C2), a parasitic capacitor (Cel), and an organic light emitting diode (OLED).

The first transistor (T1) has a gate electrode connected to the first scan signal line (SC1), a first electrode connected to the first data line (DL1), a gate electrode of the driving transistor (DT), and a first capacitor (C1). The second electrode may be connected to the gate node including the first electrode of and the second electrode of the second transistor T2. The first transistor T1 may transmit the data voltage applied through the first data line DL1 to the gate node in response to the first scan signal applied through the first scan signal line SC1.

The second transistor T2 has a gate electrode connected to the second scan signal line SC2, a first electrode connected to the reference line VREF, and a second electrode connected to the gate node including the gate electrode of the driving transistor DT. Electrodes can be connected. The second transistor T2 may transmit the reference voltage applied through the reference line VREF to the gate node in response to the second scan signal applied through the second scan signal line SC2.

The third transistor (T3) has a gate electrode connected to the third scan signal line (SC3), a first electrode connected to the initialization voltage line (VINI), a second electrode of the fifth transistor (T5), and a compensation capacitor (Cel). The second electrode may be connected to the initialization node including the first electrode of and the anode electrode of the organic light emitting diode (OLED). The third transistor (T3) transmits the initialization voltage applied through the initialization voltage line (VINI) to the anode electrode of the organic light emitting diode (OLED) in response to the third scan signal applied through the third scan signal line (SC3). You can.

The fourth transistor (T4) has a gate electrode connected to the first light emitting signal line (EM1), a first electrode connected to the first voltage line (EVDD), and a second electrode connected to the first electrode of the driving transistor (DT). You can. The fourth transistor (T4) transmits a high potential voltage applied through the first voltage line (EVDD) in response to the first light emission signal applied through the first light emission signal line (EM1) to the first electrode of the driving transistor (DT). It can be delivered to .

The fifth transistor (T5) has a gate electrode connected to the second light emitting signal line (EM2), the second electrode of the first capacitor (C1), the first electrode of the second capacitor (C2), and the second electrode of the driving transistor (DT). A first electrode may be connected to a source node including two electrodes, and a second electrode may be connected to an initialization node including an anode electrode of an organic light-emitting diode (OLED). The fifth transistor (T5) can transmit the driving current generated from the driving transistor (DT) to the anode electrode of the organic light-emitting diode (OLED) in response to the second light-emitting signal applied through the second light-emitting signal line (EM2). .

The driving transistor DT has a gate electrode connected to the gate node including the first electrode of the first capacitor C1, a first electrode connected to the second electrode of the fourth transistor T4, and a first capacitor C1. ) The second electrode may be connected to the source node including the second electrode. The driving transistor DT may generate a driving current based on the data voltage stored in the first capacitor C1.

The first capacitor C1 may have a first electrode connected to a gate node including the gate electrode of the driving transistor DT and a second electrode connected to a source node including the second electrode of the driving transistor DT. The first capacitor C1 can transmit the stored data voltage to the gate electrode of the driving transistor DT.

The second capacitor C2 may have a first electrode connected to the second electrode of the first capacitor C1 and a second electrode connected to the first voltage line EVDD. When storing the data voltage in the first capacitor C1, the second capacitor C2 can reflect the change in the potential of the gate node to the source node through voltage distribution.

The parasitic capacitor Cel may have a first electrode connected to an initialization node including an anode electrode of an organic light emitting diode (OLED) and a second electrode connected to a second voltage line EVSS. Since the parasitic capacitor (Cel) is intended to show that it can exist at both ends of an organic light emitting diode (OLED), it will be omitted below.

The organic light emitting diode (OLED) may have an anode connected to an initialization node including the second electrode of the fifth transistor T5, and a cathode connected to the second voltage line EVSS. An organic light emitting diode (OLED) can emit light based on the driving current provided by the turn-on operation of the fourth transistor (T4), driving transistor (DT), and fifth transistor (T5).

Meanwhile, an organic light emitting diode (OLED) can emit light based on a driving current, but the emission time is determined by the fourth transistor T4 controlled by the first light emitting signal and the fifth transistor controlled by the second light emitting signal. It can be varied in response to the on/off time of (T5). In addition, the first scan signal line (SC1), the second scan signal line (SC2), the third scan signal line (SC3), the first light emission signal line (EM1), and the second light emission signal line (EM2) are subpixels. It may be included in the first gate line for controlling the operation of (SP). In addition, the subpixel (SP) described above can compensate for the threshold voltage of the driving transistor (DT) based on configurations such as the reference line (VREF), initialization voltage line (VINI), and capacitors (C1 and C2). .

As shown in FIG. 9 , the first data line DL1 may be disposed in the first direction (vertical direction) of the subpixel SP. In the second direction (horizontal direction) of the subpixel SP, from the upper side (upper side of the drawing) to the lower side, there are a first voltage line (EVDD), a first light emission signal line (EM1), a reference line (VREF), and a second scan signal. The lines may be arranged in the following order: line SC2, first scan signal line SC1, second light emission signal line EM2, third scan signal line SC3, and initialization voltage line VINI.

The fourth transistor T4 may be arranged to correspond to the first light emitting signal line EM1 passing between the first voltage line EVDD and the reference line VREF. The second transistor T2 may be arranged to correspond to the second scan signal line SC2 passing between the reference line VREF and the driving transistor DT.

The driving transistor DT may be disposed between the second scan signal line SC2 and the capacitors C1 and C2. The capacitors C1 and C2 may be adjacent to each other and disposed between the driving transistor DT and the first scan signal line SC1.

The first transistor T1 may be arranged to correspond to the first scan signal line SC1 passing between the capacitors C1 and C2 and the second light emitting signal line EM2. The fifth transistor T5 may be arranged to correspond to the second light emitting signal line EM2 passing between the first scan signal line SC1 and the third scan signal line SC3.

The third transistor T1 may be arranged to correspond to the third scan signal line SC3 passing between the second light emitting signal line EM2 and the initialization voltage line VINI. The initialization voltage line VINI may be placed at the bottom of the subpixel SP.

In Figure 9, LS is a light blocking layer, ACT1 is a lower semiconductor layer, ACT2 is an upper semiconductor layer, GATE is a gate electrode layer, SD1 is a lower source-drain electrode layer, SD2 is an upper source-drain electrode layer, S-CNT is a source contact hole, G- CNT stands for gate contact hole, and for related parts, refer to the process flow chart below.

The subpixel SP according to the second embodiment has a structure in which the overlap ratio between the first data line DL1 and other electrodes is minimized, and the parasitic capacitance that can be formed between the data line and the driving transistor DT can be removed, thereby improving vertical crosstalk and ghost mura. In addition, as the first voltage line (EVDD) is formed on a lower layer than the first data line (DL1), the parasitic capacitance can be reduced and the phenomenon of vertical gradient staining can be improved.

Hereinafter, with reference to FIGS. 10 and 11 , the cross-sectional structure of the area where the driving transistor DT is located and the cross-sectional structure of the area where the capacitors C1 and C2 and the first transistor T1 are located will be described.

As shown in FIG. 10, a first light blocking layer 151a may be located on the first substrate 150a. The first light blocking layer 151a may serve to block external light from entering through the first substrate 150a. A buffer layer 152 covering the first light blocking layer 151a may be positioned on the first substrate 150a.

A first lower semiconductor layer 153a may be located on the buffer layer 152. The first lower semiconductor layer 153a may be selected as oxide. The first lower semiconductor layer 153a may be an active layer of the driving transistor DT. A first insulating layer 154 covering the first lower semiconductor layer 153a may be located on the buffer layer 152. The first insulating layer 154 may be a gate insulating layer of the driving transistor DT.

A first upper semiconductor layer 155a may be located on the first insulating layer 154. The first upper semiconductor layer 155a may be selected as oxide. The first upper semiconductor layer 155a may be selected as the gate node of the driving transistor DT. A second insulating layer 156 covering the first upper semiconductor layer 155a may be positioned on the first insulating layer 154.

A first gate electrode layer 157a may be located on the second insulating layer 156. The first gate electrode layer 157a may be the gate electrode of the driving transistor DT. A third insulating layer 158 covering the first gate electrode layer 157a may be located on the second insulating layer 156. The third insulating layer 158 may be an interlayer insulating layer.

A first lower source and drain electrode layer 159a may be located on the third insulating layer 158. The first lower source and drain electrode layer 159a may be a source electrode or a drain electrode of the driving transistor DT. The first lower source and drain electrode layer 159a may overlap the first lower semiconductor layer 153a so that it can also serve as a shielding electrode for the first lower semiconductor layer 153a. When the first lower semiconductor layer 153a and the first lower source drain electrode layer 159a overlap, the parasitic capacitance is reduced and the compensation performance of the driving transistor DT is improved, thereby improving image quality characteristics. The first planarization layer 160 may be located on the third insulating layer 158. The second planarization layer 163 may be located on the first planarization layer 160.

As shown in FIG. 11, a second light blocking layer 151b may be located on the first substrate 150a. The second light blocking layer 151b may serve as the lower electrode of the second capacitor C2 and may also serve as the first voltage line. A buffer layer 152 covering the second light blocking layer 151b may be positioned on the first substrate 150a.

A second lower semiconductor layer 153b that overlaps the second light blocking layer 151b may be located on the buffer layer 152. The second lower semiconductor layer 153b may be selected as oxide. A portion of the second lower semiconductor layer 153b (the area overlapping the second light blocking layer) may become an electrode through a conductive process. The second lower semiconductor layer 153b may become the upper electrode of the second capacitor C2 and the lower electrode of the first capacitor C1. A first insulating layer 154 covering the second lower semiconductor layer 153b may be located on the buffer layer 152.

A second upper semiconductor layer 155b that overlaps the second lower semiconductor layer 153b may be located on the first insulating layer 154. The second upper semiconductor layer 155b may be selected as oxide. A portion of the second upper semiconductor layer 155b (a region overlapping with the second lower semiconductor layer) may become an electrode through a conductive process. A part of the second upper semiconductor layer 155b that becomes an electrode can be the upper electrode of the first capacitor C1, and the other part (non-conducting active area) can be used as an upper electrode of the first transistor T1 (the second transistor T1). It can be the active layer (including the part that becomes the active layer). A second insulating layer 156 covering the second upper semiconductor layer 155b may be positioned on the first insulating layer 154. The second insulating layer 156 may be a gate insulating layer of the first transistor T1.

A second gate electrode layer 157b may be located on the second insulating layer 156. The second gate electrode layer 157b may be the gate electrode of the first transistor T1. A third insulating layer 158 covering the second gate electrode layer 157b may be located on the second insulating layer 156. The third insulating layer 158 may be an interlayer insulating layer.

A second lower source and drain electrode layer (159b), a third lower source and drain electrode layer (159c), and a fourth lower source and drain electrode layer (159d) may be located on the third insulating layer 158. The second lower source-drain electrode layer 159b may serve as a first connection electrode connecting the first capacitor C1 and the first transistor T1. The third lower source-drain electrode layer 159c may be a second connection electrode that connects the gate electrode of the first transistor T1 to another electrode or line. The fourth lower source and drain electrode layer 159d may be the source or drain electrode of the first transistor (T1). The first planarization layer 160 may be located on the third insulating layer 158.

A first upper source and drain electrode layer 161 may be located on the first planarization layer 160. The first upper source and drain electrode layer 161 may be a third connection electrode that connects the source or drain electrode of the first transistor (T1) to another electrode or line. For example, the first upper source and drain electrode layer 161 may be a data line connected to the source or drain electrode of the first transistor (T1). A second planarization layer 163 covering the first upper source and drain electrode layer 161 may be positioned on the first planarization layer 160.

FIG. 12 is a plan view showing the arrangement of components included in the subpixel of FIG. 8 according to the third embodiment, and FIGS. 13 and 24 are diagrams showing the manufacturing of a light emitting display device including the subpixel of FIG. 12 according to the third embodiment. These are process flow charts to explain the method.

As shown in FIG. 12, the subpixel includes a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), and a driving transistor (DT). ), a first capacitor (C1), a second capacitor (C2), a parasitic capacitor (Cel), and an organic light emitting diode (OLED).

In the third embodiment, in order to illustrate and explain the mask process, a cross-sectional view of the C1-C2 region, which is a cross-section cut from the A1 region to the A2 region in FIG. 9 and a cross-section from the A2 region to the B2 region, is taken as an example. Accordingly, since the arrangement relationship between lines (wires) and components (elements) is the same as in FIG. 9, the process flow will be described below based on FIGS. 13 to 24.

As shown in FIG. 13, a light blocking layer 151 may be located on the first substrate 150a. The light blocking layer 151 may be patterned into a portion that serves to block external light from entering through the first substrate 150a and a portion that serves as a lower electrode of the second capacitor. The first substrate 150a may be selected based on a rigid or flexible substrate such as glass, silicon, or polyimide. A first mask process (#1) may be required to form the light blocking layer 151 (LS).

As shown in FIG. 14, a buffer layer 152 covering the light blocking layer 151 may be formed on the first substrate 150a, and a lower semiconductor layer 153 may be formed on the buffer layer 152. The lower semiconductor layer 153 may be selected as oxide. The lower semiconductor layer 153 may include a portion that serves as an active layer of the driving transistor, an upper electrode of the second capacitor, and a portion that serves as a lower electrode of the first capacitor. The portion of the lower semiconductor layer 153 that becomes the upper electrode of the second capacitor and the lower electrode of the first capacitor can be converted into an electrode through a conductive process. A second mask process (#2) may be required to form the lower semiconductor layer 153 (ACT1).

As shown in FIG. 15, a first insulating layer 154 covering the lower semiconductor layer 153 is formed on the buffer layer 152, and an upper semiconductor layer 155 is formed on the first insulating layer 154. can do. The upper semiconductor layer 155 may be selected as oxide. The upper semiconductor layer 155 may include a portion that serves as an active layer of the first transistor and a portion that serves as an upper electrode of the first capacitor. The portion of the upper semiconductor layer 155 that becomes the upper electrode of the first capacitor may be converted into an electrode through a conductive process. According to an embodiment, the portions of the lower semiconductor layer 153 and the upper semiconductor layer 155 that serve as electrodes (excluding the active region) may be collectively made into conductors through a doping process. A third mask process (#3) may be required to form the upper semiconductor layer 155 (ACT2).

According to the embodiment, the number of light blocking layers 151 used when forming a multi-layer capacitor can be reduced from the conventional two layers to one layer, thereby simplifying the number of processes. Additionally, due to the simplification of the number of processes, exposure machine or deposition equipment ( Investment costs for CVD, etc. can be reduced.

According to the embodiment, since it is possible to configure the first transistor and the second transistor with the upper semiconductor layer 155, the pattern density of the semiconductor layer can be reduced compared to the conventional method of configuring the transistor only with the lower semiconductor layer 153. .

As shown in FIG. 16, a second insulating layer 156 covering the upper semiconductor layer 155 is formed on the first insulating layer 154, and a gate contact hole (G-) is formed in the second insulating layer 156. CNT) can be formed. A fourth mask process (#4) may be required to form the second insulating layer 156 and the gate contact hole (G-CNT).

As shown in FIG. 17, a gate electrode layer is formed on the second insulating layer 156, a first gate electrode layer 157a overlapping the light blocking layer 151, a lower semiconductor layer 153, and an upper semiconductor layer. It can be patterned to be divided into a second gate electrode layer 157b overlapping (155) and a third gate electrode layer 157c overlapping the upper semiconductor layer 155. At least one of the first gate electrode layer 157a, the second gate electrode layer 157b, and the third gate electrode layer 157c is used as a bridge electrode connecting electrodes (or lines), and the other is used as a bridge electrode for the first transistor. It can be used as a gate electrode. A fifth mask process (#5) may be required to pattern the gate electrode layer (Gate) into the first gate electrode layer (157a) to the third gate electrode layer (157c).

As shown in FIG. 18, a third insulating layer 158 is formed on the second insulating layer 156, covering the first gate electrode layer 157a to third gate electrode layer 157c, and the third insulating layer ( 158), a source contact hole (S-CNT) can be formed. A sixth mask process (#6) may be required to form the third insulating layer 158 and the source contact hole (S-CNT).

As shown in FIG. 19, a lower source-drain electrode layer (SD1) is formed on the third insulating layer 158, and a first lower source-drain electrode layer (159a) is in contact with and overlaps the lower semiconductor layer (153); It can be patterned to be divided into a second lower source and drain electrode layer 159b that contacts and overlaps the upper semiconductor layer 155. A seventh mask process (#7) may be required to pattern the lower source and drain electrode layer (SD1) into the first lower source and drain electrode layer (159a) and the second lower source and drain electrode layer (159b).

According to an embodiment, the gate contact hole (G-CNT) and the gate electrode layer (Gate) formed around it can serve as a gate electrode and as a bridge electrode connecting electrodes and electrodes and lines. As a result, the pattern density of the lower source and drain electrode layer (SD1) can be lowered by reducing the number of source contact holes (S-CNT). That is, the embodiment can be explained in a way to increase the usability of the gate electrode located lower than the lower source and drain electrode in order to lower the pattern density of the layer where the lower source and drain electrode is formed.

As shown in FIG. 20, a first planarization layer 160 covering the first lower source and drain electrode layer 159a and the second lower source and drain electrode layer 159b may be formed on the third insulating layer 158. . An eighth mask process (#8) may be required to form the first planarization layer 160 (PLN1).

As shown in FIG. 21, an upper source and drain electrode layer (SD2) is formed on the first planarization layer 160, a first upper source and drain electrode layer (161a) overlapping the first lower source and drain electrode layer (159a), and It can be patterned to be divided into a second upper source and drain electrode layer (161b) overlapping the second lower source and drain electrode layer (159b). A ninth mask process (#9) may be required to pattern the upper source and drain electrode layer (SD2) into the first upper source and drain electrode layer (161a) and the second upper source and drain electrode layer (161b).

As shown in FIG. 22, a second planarization layer 163 covering the first upper source and drain electrode layer 161a and the second upper source and drain electrode layer 161b may be formed on the first planarization layer 160. . A tenth mask process (#10) may be required to form the second planarization layer (163, PLN2).

As shown in FIG. 23, an anode electrode layer 164 in contact with the first upper source and drain electrode layer 161a may be formed on the second planarization layer 163. An 11th mask process (#11) may be required to form the anode electrode layer 164 (AND).

As shown in FIG. 24, the bank layer 165 may be formed on the second planarization layer 163 so that a portion of the anode electrode layer 164 is exposed. A 12th mask process (#12) may be required to form the bank layer 165 (BNS).

Hereinafter, the method of manufacturing a light emitting display device including subpixels can be completed through a process of forming an organic light emitting layer on the anode electrode layer 164 and forming a cathode electrode layer on the organic light emitting layer. However, since a touch sensor may be implemented on the organic light emitting layer and the cathode electrode layer, or an encapsulation layer therefor may be formed in various forms, description of the corresponding part will be omitted.

As mentioned above, this embodiment can implement a multi-layer capacitor with a simplified process and configuration, and can improve compensation performance and improve image quality characteristics by removing or reducing parasitic capacitance that may appear around the driving transistor and data line. It works. In addition, this embodiment has the effect of improving vertical crosstalk and ghost mura by removing or reducing parasitic capacitance, as well as improving the phenomenon of vertical gradient staining. In addition, this embodiment has the effect of improving yield by lowering the pattern density of the source-drain electrode layer and semiconductor layer based on a simplified process and configuration, as well as reducing investment costs for equipment required for processing and manufacturing. there is.

151a, 151b, 151: light blocking layer 152: buffer layer
153a, 153b, 153: lower semiconductor layer 154: first insulating layer
155a, 155b, 155: upper semiconductor layer 156: second insulating layer
157a, 157b, 157: gate electrode layer 158: third insulating layer

Claims (10)

A substrate including a first transistor area and a capacitor area;
a light blocking layer located on the substrate and including a lower electrode of a lower capacitor;
a buffer layer located on the substrate and covering the light blocking layer;
a lower semiconductor layer located on the buffer layer, overlapping the lower electrode of the lower capacitor, and including an active region and a partially conductive region to become an upper electrode of the lower capacitor and a lower electrode of the upper capacitor;
a first insulating layer located on the buffer layer and covering the lower semiconductor layer;
an upper semiconductor layer located on the first insulating layer, overlapping a conductive region of the lower semiconductor layer, and including an active region and a partially conductive region to serve as an upper electrode of the upper capacitor; and
A display device comprising a second insulating layer located on the first insulating layer and covering the upper semiconductor layer. According to paragraph 1,
a gate electrode layer located on the second insulating layer and overlapping the active area of the upper semiconductor layer;
a third insulating layer located on the second insulating layer and covering the gate electrode layer;
A display device including a lower source and drain electrode layer located on the third insulating layer. According to paragraph 2,
The lower source drain electrode layer is
A first lower source and drain electrode layer in contact with the conductive region of the lower semiconductor layer, a second lower source and drain electrode layer in contact with the gate electrode layer, and a third lower source and drain electrode layer in contact with the conducted region of the upper semiconductor layer. A display device including a. According to clause 3,
a first planarization layer located on the third insulating layer and covering the first lower, second lower and third lower source and drain electrode layers;
A display device comprising an upper source and drain electrode layer located on the first planarization layer and connected to the third lower source and drain electrode layer. a first transistor with a gate electrode connected to a first scan signal line and a first electrode connected to a first data line;
a driving transistor whose gate electrode is connected to the second electrode of the first transistor and which generates a driving current to drive a light emitting diode;
a first capacitor having a first electrode connected to a second electrode of the first transistor and a gate electrode of the driving transistor and a second electrode connected to the second electrode of the driving transistor;
A second capacitor having a first electrode connected to a second electrode of the first capacitor and a second electrode of the driving transistor and a second electrode connected to a first voltage line,
The first transistor, the driving transistor, the first capacitor, and the second capacitor are
A light blocking layer located on the substrate and including a second electrode of the second capacitor,
A buffer layer located on the substrate and covering the light blocking layer,
A region located on the buffer layer, overlapping the second electrode of the second capacitor, becoming the first electrode of the second capacitor, and partially conductive to become the second electrode of the first capacitor, and the active region of the driving transistor A lower semiconductor layer comprising,
A first insulating layer located on the buffer layer and covering the lower semiconductor layer,
An upper semiconductor layer located on the first insulating layer, overlapping the conductive region of the lower semiconductor layer, and including a region partially conductive to become the first electrode of the first capacitor and the active region of the first transistor. , and
A display device comprising a second insulating layer located on the first insulating layer and covering the upper semiconductor layer. According to clause 5,
a gate electrode layer located on the second insulating layer and overlapping the active area of the upper semiconductor layer;
a third insulating layer located on the second insulating layer and covering the gate electrode layer;
A display device including a lower source and drain electrode layer located on the third insulating layer. According to clause 6,
a first planarization layer located on the third insulating layer and covering the first lower, second lower and third lower source and drain electrode layers;
A display device comprising an upper source and drain electrode layer located on the first planarization layer, connected to the third lower source and drain electrode layer, and serving as the first data line. Forming a light blocking layer including the lower electrode of the lower capacitor on the substrate;
forming a buffer layer covering the light blocking layer on the substrate;
Forming a lower semiconductor layer on the buffer layer that overlaps the lower electrode of the lower capacitor and includes an active region of the driving transistor and a region partially conductive to become the upper electrode of the lower capacitor and the lower electrode of the upper capacitor. step;
forming a first insulating layer covering the lower semiconductor layer on the buffer layer;
Forming an upper semiconductor layer on the first insulating layer that overlaps the conductive region of the lower semiconductor layer and includes a partially conductive region to become an upper electrode of the upper capacitor and an active region of the first transistor. ; and
A method of manufacturing a display device including forming a second insulating layer on the first insulating layer to cover the upper semiconductor layer. According to clause 8,
The conductive regions of the lower semiconductor layer and the upper semiconductor layer are
A method of manufacturing a display device that is collectively converted into a conductor by a doping process. According to clause 8,
The lower capacitor and the upper capacitor are connected in series,
The lower electrode of the lower capacitor is in contact with the first voltage line,
A method of manufacturing a display device in which the upper electrode of the upper capacitor is in contact with the gate electrode of the driving transistor and the second electrode of the first transistor.