KR102593451B1 - Organic Light Emitting Display Device and Method of Manufacturing the same - Google Patents

Abstract

The present invention prevents the problem of light leakage from leaking to other subpixels (blocks light leakage), realizes accurate colors, and improves display quality. For this purpose, the present invention places a barrier layer in the boundary area between subpixels.

Description

Display device and method of manufacturing the same {Organic Light Emitting Display Device and Method of Manufacturing the same}

The present invention relates to a display device and a method of manufacturing the same.

As information technology develops, the market for display devices, which are a connecting medium between users and information, is growing. Accordingly, the use of display devices such as Organic Light Emitting Display (OLED), Liquid Crystal Display (LCD), and Plasma Display Panel (PDP) is increasing.

Some of the display devices described above, such as liquid crystal displays and organic light emitting display devices, include a display panel including a plurality of subpixels arranged in a matrix and a driver that drives the display panel. The driver includes a scan driver that supplies scan signals (or gate signals) to the display panel and a data driver that supplies data signals to the display panel.

In the above display device, when scan signals and data signals are supplied to subpixels, the selected subpixels emit light, allowing images to be displayed. The display panel displays images using light emitted through subpixels. The structure and shape of subpixels may vary depending on the implementation and manufacturing method of the display panel.

However, the conventionally proposed structure causes problems such as inability to implement accurate colors or deterioration of display quality when light reflection, interference, or color mixing occurs between adjacent subpixels, so improvement is required. .

The present invention to solve the problems of the above-mentioned background technology is to prevent the problem of light leakage from leaking to other sub-pixels (blocking light leakage) to implement accurate colors and improve display quality.

As a means of solving the above-described problem, the present invention provides a display device including subpixels, at least one signal line, and a barrier layer. Subpixels are located on a substrate. At least one signal line is located between boundary areas between subpixels. The barrier layer is disposed in the boundary area between subpixels and is located on at least one signal line.

The barrier layer may be arranged vertically along the boundary area between subpixels.

The partition layer may include an area having a straight section along a boundary area between subpixels and an area having a non-straight section including diagonal lines and straight lines.

The barrier layer is disposed along the boundary area between the light emitting areas of the subpixels, and the light emitting area may be an area where the organic light emitting diode emits light.

The barrier layer extends to the circuit area of the subpixels, and the circuit area may be an area where transistors that drive the organic light emitting diode are located.

The boundary area between subpixels includes at least one signal line located on the substrate, an insulating layer located on the at least one signal line, and a space located on the insulating layer and separated into one side and the other side on the signal line. It may include a planarization layer and a partition layer located in a space separated from the planarization layer.

The partition layer may be located in an upper portion of the planarization layer and on the side walls.

In another aspect, the present invention provides a method of manufacturing a display device. A method of manufacturing a display device includes forming at least one signal line on a substrate, forming an insulating layer on the at least one signal line, forming a planarization layer on the insulating layer, and forming a planarization layer on one side and the other on the signal line. It includes the step of patterning the planarization layer to be separated and have a space apart, and forming a partition layer in the space between the planarization layer.

The barrier layer may be disposed in a boundary area between subpixels located on the substrate.

The partition layer may be located in an upper portion of the planarization layer and on the side walls.

The present invention has the effect of implementing accurate colors and improving display quality by preventing problems such as light reflection, interference, and color mixing (view color blurring) between left and right adjacent subpixels. In addition, the present invention has the effect of improving luminance by preventing the problem of light leakage (blocking light leakage) in which light emitted through a subpixel leaks to other subpixels.

1 is a schematic block diagram of an organic light emitting display device according to a first embodiment of the present invention.
2 is a schematic circuit diagram of a subpixel.
3 is an example of a specific circuit configuration of a subpixel.
FIG. 4 is an exemplary cross-sectional view of a display panel, and FIG. 5 is an exemplary plan view of a subpixel.
Figure 6 is a plan example of subpixels to explain the problem of the conventional structure.
Figure 7 is a cross-sectional view of area A1-A2 in Figure 6.
Figure 8 is a cross-sectional view of area B1-B2 in Figure 6.
Figure 9 is a plan view of subpixels for explaining the structure of the first embodiment of the present invention.
FIG. 10 is a cross-sectional view of region C1-C2 of FIG. 9.
FIG. 11 is a cross-sectional view of area D1-D2 of FIG. 9.
Figure 12 is a cross-sectional view to help understand the light emitting area and circuit area of Figure 9.
13 is a plan view of subpixels for explaining the structure of the second embodiment of the present invention.

Hereinafter, specific details for implementing the present invention will be described with reference to the attached drawings.

The display device according to the present invention is implemented in televisions, set-top boxes, navigation systems, video players, Blu-ray players, personal computers (PCs), home theaters, mobile phones, etc. The display panel of the display device may be selected from a liquid crystal display panel, an organic light emitting display panel, a quantum dot display panel, an electrophoretic display panel, a plasma display panel, etc., but is not limited thereto. However, hereinafter, an organic electroluminescent display device based on an organic light emitting display panel will be described as an example.

<First embodiment>

FIG. 1 is a schematic block diagram of an organic light emitting display device according to a first embodiment of the present invention, FIG. 2 is a schematic circuit configuration diagram of a subpixel, and FIG. 3 is an example of a specific circuit configuration of a subpixel. FIG. 4 is an exemplary cross-sectional view of a display panel, and FIG. 5 is an exemplary plan view of a subpixel.

As shown in FIG. 1, the organic light emitting display device according to the first embodiment of the present invention includes an image processing unit 110, a timing control unit 120, a data driver 130, a scan driver 140, and a display panel ( 150) are included.

The image processing unit 110 outputs a data enable signal (DE) in addition to a data signal (DATA) supplied from the outside. In addition to the data enable signal DE, the image processor 110 may output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, but these signals are omitted for convenience of explanation.

The timing control unit 120 receives a data enable signal (DE) or a driving signal including a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, as well as a data signal (DATA) from the image processing unit 110. The timing control unit 120 provides a gate timing control signal (GDC) for controlling the operation timing of the scan driver 140 and a data timing control signal (DDC) for controlling the operation timing of the data driver 130 based on the driving signal. outputs.

The data driver 130 samples and latches the data signal (DATA) supplied from the timing control unit 120 in response to the data timing control signal (DDC) supplied from the timing control unit 120, converts it to a gamma reference voltage, and outputs it. . The data driver 130 outputs a data signal (DATA) through the data lines (DL1 to DLn). The data driver 130 may be formed in the form of an integrated circuit (IC).

The scan driver 140 outputs a scan signal (or gate signal) while shifting the level of the gate voltage in response to the gate timing control signal (GDC) supplied from the timing controller 120. The scan driver 140 outputs scan signals through scan lines GL1 to GLm. The scan driver 140 is formed in the form of an integrated circuit (IC) or is formed in the display panel 150 using a gate in panel method.

The display panel 150 displays images in response to data signals (DATA) and scan signals supplied from the data driver 130 and the scan driver 140. The display panel 150 includes subpixels (SP) that operate to display images. The display panel 150 is formed in a top-emission, bottom-emission, or dual-emission manner depending on the structure of the subpixels SP.

As shown in FIG. 2, one subpixel includes a switching transistor (SW), a driving transistor (DR), a capacitor (Cst), a compensation circuit (CC), and an organic light emitting diode (OLED).

The switching transistor SW operates in response to the scan signal supplied through the first scan line GL1 so that the data signal supplied through the first data line DL1 is stored as a data voltage in the capacitor Cst. The driving transistor DR operates so that a driving current flows between the first power line EVDD and the second power line EVSS according to the data voltage stored in the capacitor Cst. An organic light emitting diode (OLED) operates to emit light according to a driving current formed by a driving transistor (DR).

The compensation circuit (CC) is a circuit added to the subpixel to compensate for the threshold voltage of the driving transistor (DR). The compensation circuit (CC) consists of one or more transistors. The composition of the compensation circuit (CC) varies greatly depending on the compensation method, and an example is as follows.

As shown in FIG. 3, the compensation circuit (CC) includes a sensing transistor (ST) and a sensing line (VREF). The sensing transistor (ST) is connected between the source line of the driving transistor (DR) and the anode electrode of the organic light emitting diode (OLED) (hereinafter referred to as the sensing node). The sensing transistor (ST) operates to supply the initialization voltage (or sensing voltage) transmitted through the sensing line (VREF) to the sensing node or to sense the voltage or current of the sensing node.

The configuration and connection relationships of the elements included in the subpixel along with the compensation circuit (CC) are explained as follows.

The switching transistor (SW) has a first electrode connected to the first data line (DL1) and a second electrode connected to the gate electrode of the driving transistor (DR). The driving transistor (DR) has a first electrode connected to the first power line (EVDD) and a second electrode connected to the anode electrode of the organic light emitting diode (OLED). The capacitor Cst has a first electrode connected to the gate electrode of the driving transistor DR and a second electrode connected to the anode electrode of the organic light emitting diode (OLED).

The organic light emitting diode (OLED) has an anode connected to the second electrode of the driving transistor (DR) and a cathode connected to the second power line (EVSS). The sensing transistor (ST) has a first electrode connected to the sensing line (VREF) and a second electrode connected to the anode electrode of the organic light emitting diode (OLED). The first electrode or the second electrode refers to the source electrode of the transistor (which may be a drain electrode depending on the type of transistor) or the drain electrode (which may be a source electrode depending on the type of transistor).

The operation time of the sensing transistor (ST) may be similar/same or different from that of the switching transistor (SW) depending on the compensation algorithm (or configuration of the compensation circuit). For example, the switching transistor (SW) may have its gate electrode connected to the 1a scan line (GL1a), and the sensing transistor (ST) may have its gate electrode connected to the 1b scan line (GL1b). As another example, the 1a scan line (GL1a) connected to the gate electrode of the switching transistor (SW) and the 1b scan line (GL1b) connected to the gate electrode of the sensing transistor (ST) may be connected to share in common.

The sensing line (VREF) may be connected to the data driver. In this case, the data driver may sense the sensing node of the subpixel in real time, during a non-display period of the image, or during an N frame period (N is an integer greater than 1) and generate a sensing result. The switching transistor (SW) and sensing transistor (ST) may be turned on at the same time. In this case, the sensing operation through the sensing line (VREF) and the data output operation of outputting the data signal are separated (differentiated) from each other based on the time division method of the data driver.

In addition, the compensation target according to the sensing result may be a digital data signal, an analog data signal, or gamma. And the compensation circuit that generates a compensation signal (or compensation voltage) based on the sensing result may be implemented inside the data driver, inside the timing control unit, or as a separate circuit.

A light blocking layer (LSd) is formed on the lower or upper layer corresponding to the channel region of the driving transistor (DR). The light blocking layer (LSd) exists to protect and stabilize the driving transistor (DR) from external light. The light blocking layer (LSd) serves to block external light and may be located in the lower layer of the switching transistor (SW) or the sensing transistor (ST).

Meanwhile, in Figure 3, a subpixel with a 3T (Transistor) 1C (Capacitor) structure including a switching transistor (SW), a driving transistor (DR), a capacitor (Cst), an organic light emitting diode (OLED), and a sensing transistor (ST) is shown. Although explained as an example, if a compensation circuit (CC) is added, it can be configured as 3T2C, 4T2C, 5T1C, 6T2C, etc.

As shown in FIG. 4 , the display panel 150 includes a pixel P located between a substrate 150a and a protective substrate (or film) 150b. The area where the pixel (P) is placed is defined as the display area (AA), and the outside of the display area (AA) where the pixel (P) is not placed is defined as the non-display area (NA).

For example, a pixel (P) is made up of four subpixels: red (R), white (W), blue (B), and green (G). It may be composed of three or more subpixels. Red (R), white (W), blue (B), and green (G) subpixels are arranged horizontally or vertically. The arrangement order of subpixels may vary depending on the light emitting material, light emitting area, composition (or structure) of the compensation circuit, etc. Therefore, hereinafter, they will be referred to as first to third subpixels or first to fourth subpixels.

As shown in FIGS. 5(a) and 5(b), the first to third subpixels (SP1 to SP3) and the first to fourth subpixels (SP1 to SP4) have an emission area (EMA). ) and circuit area (DRA) are included.

The light emitting area (EMA) corresponds to an area that emits light, and an organic light emitting diode is located in this area. The circuit area (DRA) corresponds to an area that does not emit light, and a driving transistor that drives an organic light-emitting diode is located in this area.

The ratio of dividing the light emitting area (EMA) and the circuit area (DRA) and its shape can vary depending on the light emitting material, light emitting area, characteristics of the transistor, composition (or structure) of the compensation circuit, etc.

Meanwhile, the structure and shape of subpixels may vary depending on the implementation and manufacturing method of the display panel, but if light reflection, interference, or color mixing occurs between adjacent subpixels, problems such as not being able to implement accurate colors or display quality problems may occur. It causes problems such as deterioration.

Hereinafter, the problems of the conventional structure will be considered and a detailed description of embodiments of the present invention to solve them will be provided.

-Conventional structure-

FIG. 6 is a plan view of subpixels to explain problems with the conventional structure, FIG. 7 is a cross-sectional view of area A1-A2 in FIG. 6, and FIG. 8 is a cross-sectional view of area B1-B2 in FIG. 6.

As shown in FIG. 6, first to fourth subpixels SP1 to SP4 are disposed on the display panel. For example, the first to fourth subpixels SP1 to SP4 may be arranged in the order of red (R), white (W), blue (B), and green (G) subpixels. However, the arrangement order of subpixels may vary depending on the light emitting material, light emitting area, composition (or structure) of the compensation circuit, etc.

A 1a scan line GL1a and a 1b scan line GL1b are disposed in the horizontal direction of the first to fourth subpixels SP1 to SP4. A first power line (EVDD), a sensing line (VREF), and data lines (DL1 to DL4) are arranged in the vertical direction of the first to fourth subpixels (SP1 to SP4).

A first power line (EVDD) may be placed on the left side of the first subpixel (SP1), and a first data line (DL1) may be placed on the right side. The second data line DL2 may be placed on the left side of the second subpixel SP2, and the sensing line VREF may be placed on the right side. A sensing line (VREF) may be placed on the left side of the third subpixel (SP3), and a third data line (DL3) may be placed on the right side. A fourth data line DL4 may be placed on the left side of the fourth subpixel SP4, and a first power line (not shown) may be placed on the right side. Hereinafter, a description of the conventional structure will be detailed with reference to cross-sectional drawings.

As shown in FIGS. 6 and 7 , first and second data lines DL1 and DL2 are disposed between the first subpixel SP1 and the second subpixel SP2. That is, two signal lines are disposed between the first subpixel (SP1) and the second subpixel (SP2).

Referring to the cross-sectional view of this area, a red color filter (CFR) exists below the planarization layer (OC) of the first subpixel (SP1), but a color filter (CFR) exists below the planarization layer (OC) of the second subpixel (SP2). No filter exists.

A bank layer (BNK) exists on top of the planarization layer (OC) of the first subpixel (SP1) and the second subpixel (SP2). The bank layer (BNK) structurally combines the light emitting area (EMA) existing on the top of the first subpixel (SP1) and the light emitting area (EMA) existing on the top of the planarization layer (OC) of the second subpixel (SP2). It plays a separating role.

However, in the conventional structure, when the first subpixel (SP1) corresponding to red displays an image, only the first subpixel (SP1) must emit light, but light is emitted toward the adjacent second subpixel (SP2).

Therefore, in the conventional structure, even if the first subpixel (SP1) emits light and the second subpixel (SP2) emits light or does not emit light, the light emitted from the first subpixel (SP1) is transmitted to the second subpixel (SP1). It is emitted into the light emitting area (EMA) of the pixel (SP2) and mixed colors occur.

As shown in FIGS. 6 and 8 , a sensing line VREF is disposed between the second subpixel SP2 and the third subpixel SP3. That is, one signal line is disposed between the second subpixel (SP2) and the third subpixel (SP3).

Referring to the cross-sectional view of this area, there is no color filter under the planarization layer OC of the second subpixel SP2, but a blue color filter CFB exists under the third subpixel SP3.

A bank layer (BNK) exists on top of the planarization layer (OC) of the second subpixel (SP2) and the third subpixel (SP3). The bank layer (BNK) structurally combines the light emitting area (EMA) existing on top of the second subpixel (SP2) and the light emitting area (EMA) existing on top of the planarization layer (OC) of the third subpixel (SP3). It plays a separating role.

However, in the conventional structure, when the third subpixel (SP3) corresponding to blue displays an image, only the third subpixel (SP3) must emit light, but light is emitted toward the adjacent second subpixel (SP2).

Therefore, in the conventional structure, even if the third subpixel (SP3) emits light and the second subpixel (SP2) emits light or does not emit light, the light emitted from the third subpixel (SP3) is transmitted to the second subpixel (SP3). It is emitted into the light emitting area (EMA) of the pixel (SP2) and mixed colors occur.

As mentioned above, the conventionally proposed structure causes problems such as not being able to implement accurate colors or deteriorating display quality when light reflection, interference, or color mixing occurs between adjacent subpixels, so improvement is required. .

-Structure of the first embodiment-

FIG. 9 is a plan view of subpixels for explaining the structure of the first embodiment of the present invention, FIG. 10 is a cross-sectional view of the C1-C2 region of FIG. 9, and FIG. 11 is a cross-sectional view of the D1-D2 region of FIG. 9. , FIG. 12 is a cross-sectional view to help understand the light emitting area and circuit area of FIG. 9.

As shown in FIG. 9, first to fourth subpixels SP1 to SP4 are disposed on the display panel. For example, the first to fourth subpixels SP1 to SP4 may be arranged in the order of red (R), white (W), blue (B), and green (G) subpixels. However, the arrangement order of subpixels may vary depending on the light emitting material, light emitting area, composition (or structure) of the compensation circuit, etc.

A 1a scan line GL1a and a 1b scan line GL1b are disposed in the horizontal direction of the first to fourth subpixels SP1 to SP4. A first power line (EVDD), a sensing line (VREF), and data lines (DL1 to DL4) are arranged in the vertical direction of the first to fourth subpixels (SP1 to SP4).

A first power line (EVDD) may be placed on the left side of the first subpixel (SP1), and a first data line (DL1) may be placed on the right side. The second data line DL2 may be placed on the left side of the second subpixel SP2, and the sensing line VREF may be placed on the right side. A sensing line (VREF) may be placed on the left side of the third subpixel (SP3), and a third data line (DL3) may be placed on the right side. A fourth data line DL4 may be placed on the left side of the fourth subpixel SP4, and a first power line (not shown) may be placed on the right side.

A barrier layer BLW is disposed vertically in the boundary area of the first to fourth subpixels SP1 to SP4. The barrier layer BLW is arranged to correspond to the length of the light emitting area EMA of the first to fourth subpixels SP1 to SP4. That is, the barrier layer BLW does not exist in the circuit area DRA of the first to fourth subpixels SP1 to SP4.

The barrier layer BLW may be disposed along the boundary area between all subpixels, but may also be disposed only between specific subpixels. For example, it may be selectively placed only in the boundary area between a white subpixel and an adjacent subpixel.

Light-emitting layers included in subpixels have different optical properties, such as color expression, lifespan, and luminance, depending on the material. Therefore, a design is needed to implement similar or identical optical characteristics of subpixels or to compensate for the shortcomings of a specific subpixel. Therefore, in an embodiment of the present invention, subpixels are designed as follows in consideration of the optical characteristics of the light emitting layers, but this is only an example and the present invention is not limited thereto.

The boundary areas of subpixels include an area with a straight section (e.g., the left side of SP1), an area that protrudes to the left and has a non-linear section (e.g., the left side of SP2), and an area that protrudes to the right and has a non-linear section (e.g., right side of SP3), etc. may exist. Accordingly, the barrier layer BLW may have an area having a straight section and an area having a non-straight section (an area including diagonal lines and straight lines) along the boundary areas of the subpixels.

The barrier layer (BLW) can be made of colored pigments or metal materials that can block light. Hereinafter, as an example, the barrier layer (BLW) is selected as a metal material capable of blocking light.

Hereinafter, the structure of the first embodiment will be described in detail with reference to the cross-sectional drawings.

As shown in FIGS. 9 and 10 , first and second data lines DL1 and DL2 are disposed between the first subpixel SP1 and the second subpixel SP2. That is, two signal lines are disposed between the first subpixel (SP1) and the second subpixel (SP2).

Referring to the cross-sectional view of this area, a red color filter (CFR) exists below the planarization layer (OC) of the first subpixel (SP1), but a color filter (CFR) exists below the planarization layer (OC) of the second subpixel (SP2). No filter exists.

The planarization layer OC covering the first subpixel SP1 and the second subpixel SP2 is separated into one side and the other at the boundary area between the first subpixel SP1 and the second subpixel SP2. That is, the planarization layer OC is separated to have a space between the first data line and the second data line DL1 and DL2. The space separating the planarization layer OC may be formed by patterning using an etching method, but is not limited thereto.

In this area, the separation distance between the planarization layers (OC) can be selected within the line width of the first data line and the second data line (DL1, DL2). However, if the separation distance between the planarization layers (OC) exceeds the outermost range of the combined line width of the first and second data lines (DL1 and DL2), the emission area (EMA) becomes narrow. In other words, the spacing between the planarization layers (OC) is related to the aperture ratio that defines the luminescent area (EMA), and if this spacing is set too wide, care must be taken as this will result in a decrease in the aperture ratio.

A barrier layer (BLW) is disposed between the space between the planarization layers (OC). The barrier layer (BLW) is formed to cover the upper part of the separated planarization layer (OC) and the side walls. The barrier layer (BLW) serves as a blocking film (or barrier) that prevents color mixing and interference (light interference) between adjacent subpixels.

A bank layer (BNK) exists on top of the planarization layer (OC) of the first subpixel (SP1) and the second subpixel (SP2). The bank layer (BNK) structurally combines the light emitting area (EMA) existing on the top of the first subpixel (SP1) and the light emitting area (EMA) existing on the top of the planarization layer (OC) of the second subpixel (SP2). It plays a separating role.

As above, in the structure of the first embodiment, there is a barrier layer (BLW) that functions as a blocking film to block light in the space provided between the first subpixel (SP1) and the second subpixel (SP2). Therefore, even if the first subpixel (SP1) emits light and the second subpixel (SP2) emits light or does not emit light (or the opposite state), the light emitted from the first subpixel (SP1) Problems such as color mixing problems emitted from the light emitting area (EMA) of the second subpixel (SP2) do not occur.

As shown in FIGS. 9 and 11 , a sensing line VREF is disposed between the second subpixel SP2 and the third subpixel SP3. That is, one signal line is disposed between the second subpixel (SP2) and the third subpixel (SP3). Meanwhile, referring to FIGS. 10 and 11 together, the line width of the sensing line (VREF) is shown as corresponding to the combined line width of the first and second data lines (DL1 and DL2), but this is only an example. It is not limited to this.

Referring to the cross-sectional view of this area, there is no color filter under the planarization layer OC of the second subpixel SP2, but a blue color filter CFB exists under the third subpixel SP3.

The planarization layer OC covering the second subpixel SP2 and the third subpixel SP3 is separated from the boundary area between the second subpixel SP2 and the third subpixel SP3. That is, the planarization layer OC is separated to have a space spaced apart from each other on the third data line DL3.

In this area, the separation distance between the planarization layers (OC) can be selected within the line width of the sensing line (VREF). However, if the separation distance between the planarization layers (OC) exceeds the outermost range of the line width of the sensing line (VREF), the emission area (EMA) becomes narrow. In other words, the spacing between the planarization layers (OC) is related to the aperture ratio that defines the luminescent area (EMA), and if this spacing is set too wide, care must be taken as this will result in a decrease in the aperture ratio.

A barrier layer (BLW) is disposed between the space between the planarization layers (OC). The barrier layer BLW may be formed to cover a partial upper area and side walls of the separated planarization layer OC. The barrier layer (BLW) serves as a blocking film (or barrier) that prevents color mixing and interference (light interference) between adjacent subpixels.

A bank layer (BNK) exists on top of the planarization layer (OC) of the second subpixel (SP2) and the third subpixel (SP3). The bank layer (BNK) structurally combines the light emitting area (EMA) existing on top of the second subpixel (SP2) and the light emitting area (EMA) existing on top of the planarization layer (OC) of the third subpixel (SP3). It plays a separating role.

As above, in the structure of the first embodiment, there is a barrier layer (BLW) that functions as a blocking film to block light in the space provided between the second subpixel (SP2) and the third subpixel (SP3). Therefore, even if the third subpixel (SP3) emits light and the second subpixel (SP2) emits light or does not emit light (or the opposite state), the light emitted from the third subpixel (SP3) Problems such as color mixing problems emitted from the light emitting area (EMA) of the second subpixel (SP2) do not occur.

As described above, the structure of the first embodiment prevents problems such as light reflection, interference, and color mixing between left and right adjacent subpixels, so accurate colors can be implemented, and as a result, display quality can be further improved. Additionally, the structure of the first embodiment can improve luminance by preventing the problem of light leakage (blocking light leakage) in which light emitted through a subpixel leaks to other subpixels.

Meanwhile, the barrier layer BLW may be formed along with a process of forming a metal layer included in the circuit area DRA of the subpixels SP1 to SP4, which will be described in detail below.

As shown in FIGS. 10 to 12, the circuit area of the subpixels includes a driving transistor (DR) electrically connected to an organic light emitting diode (OLED). The first or second electrode of the driving transistor (DR) is electrically connected to the anode electrode of the organic light emitting diode (OLED). Hereinafter, the stacked structure of the driving transistor (DR) and organic light emitting diode (OLED) will be described as follows.

A gate metal layer 151 is formed on the substrate 150a. The gate metal layer 151 is one or an alloy thereof selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu). It may be composed of a single layer or multiple layers. The gate metal layer 151 serves as the gate electrode of the driving transistor DR and can be patterned and separated into scan lines, pad electrodes, etc.

A first insulating layer 152 is formed on the gate metal layer 151. The first insulating layer 152 serves to electrically insulate the gate metal layer 151. The first insulating layer 152 may be made of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx).

A semiconductor layer 153 is formed on the first insulating layer 152. The semiconductor layer 153 is connected to the source electrode and drain electrode of the transistor. The semiconductor layer 153 may be selected from a material such as oxide (IGZO, TiO2, ZnO, WO3, SnO2) or silicon (a-Si, p-Si).

An etch stopper layer (ESL) is formed on the semiconductor layer 153. The etch stopper layer (ESL) serves to expose a portion of the active layer that will be the source and drain regions of the semiconductor layer 153 and to prevent overetching during patterning. The etch stopper layer (ESL) may be made of an organic insulating film (photosensitive and non-photosensitive organic insulating film).

First source drain metal layers 154a and 154b (SD1) are formed on the etch stopper layer (ESL). The first source and drain metal layers 154a and 154b are patterned and separated into the source and drain electrodes 154a and 154b of the driving transistor DR. The source and drain electrodes 154a and 154b are in contact with the source and drain regions of the semiconductor layer 153. The source and drain electrodes 154a and 154b are selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu). It may be one or an alloy thereof, and may be made of a single layer or multiple layers.

A second insulating layer 155 is formed on the source and drain metal layers 154a and 154b. The second insulating layer 155 serves as a protective film to protect the source electrode and drain electrodes 154a and 154b. The second insulating layer 155 may be made of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx). The second insulating layer 155 has a contact hole exposing the source electrode 154a of the driving transistor DR.

Second source and drain metal layers 156a and 156b (SD2) are formed on the second insulating layer 155. The second source and drain metal layers 156a and 156b are formed by a portion of the connection electrode 156a that contacts the source electrode 154a of the driving transistor DR and the second gate electrode (or upper gate electrode) 156b of the driving transistor DR. ) It is patterned and separated into parts that play a role. The second source and drain metal layers 156a and 156b may be made of the same material as the first source and drain metal layers 154a and 154b, but are not limited thereto. The second gate electrode (or upper gate electrode) 156b of the driving transistor DR also serves to block light incident from the top or side.

A color filter (CF) is formed on the second gate electrode (or upper gate electrode) 156b. The color filter (CF) can be selected as red, green, or blue.

A planarization layer OC is formed on the second insulating layer 155 to cover the second source and drain metal layers 156a and 156b and the color filter CF. The planarization layer (OC) serves to planarize the lower surface corresponding to the transistor array. The planarization layer OC has a contact hole exposing the connection electrode 156a in contact with the source electrode 154a. The planarization layer (OC) may be an organic insulating film such as photoacrylic, but is not limited thereto.

An anode electrode layer 157 is formed on the planarization layer (OC). The anode electrode layer 157 is electrically connected to the connection electrode 156a. The anode electrode layer 157 may be made of a transparent oxide (eg, ITO), but is not limited thereto.

A bank layer (BNK) defining a light emitting area is formed on the planarization layer (OC). The bank layer (BNK) forms an opening corresponding to the light emitting area of the subpixel. The bank layer (BNK) may be selected as an organic insulating film or an inorganic insulating film.

An organic light-emitting layer 158 is formed on the anode electrode layer 157. The organic light-emitting layer 158 includes a light-emitting layer that emits red, green, blue, or white light, and a functional layer (hole injection layer, hole transport layer, electron transport layer, electron injection layer, etc.) that helps recombination of holes and electrons. The organic light emitting layer 158 may also be located on the bank layer (BNK), but is not limited thereto.

A cathode electrode layer 159 is formed on the organic light emitting layer 158. The cathode electrode layer 159 may be made of an opaque metal (eg, Al), but is not limited thereto. The cathode electrode layer 159 is commonly formed on the front surface of the display area of the display panel and is electrically connected to the second power line inside or outside the display area.

When a subpixel is formed with a stacked structure as described with reference to FIG. 12, the barrier layer BLW described in FIGS. 9 to 11 is formed along with the process of forming the second source and drain metal layers 156a and 156b. You can. That is, the barrier layer BLW may be formed using the same material and the same process as the second source and drain metal layers 156a and 156b. However, this is only an example, and if the second source and drain metal layers 156a and 156b do not exist, they are formed through a separate process.

<Second Embodiment>

Figure 13 is a plan view of subpixels for explaining the structure of the second embodiment of the present invention.

As shown in FIG. 13, first to fourth subpixels SP1 to SP4 are disposed on the display panel. For example, the first to fourth subpixels SP1 to SP4 may be arranged in the order of red (R), white (W), blue (B), and green (G) subpixels. However, the arrangement order of subpixels may vary depending on the light emitting material, light emitting area, composition (or structure) of the compensation circuit, etc.

A 1a scan line GL1a and a 1b scan line GL1b are disposed in the horizontal direction of the first to fourth subpixels SP1 to SP4. A first power line (EVDD), a sensing line (VREF), and data lines (DL1 to DL4) are arranged in the vertical direction of the first to fourth subpixels (SP1 to SP4).

A first power line (EVDD) may be placed on the left side of the first subpixel (SP1), and a first data line (DL1) may be placed on the right side. The second data line DL2 may be placed on the left side of the second subpixel SP2, and the sensing line VREF may be placed on the right side. A sensing line (VREF) may be placed on the left side of the third subpixel (SP3), and a third data line (DL3) may be placed on the right side. A fourth data line DL4 may be placed on the left side of the fourth subpixel SP4, and a first power line (not shown) may be placed on the right side.

A barrier layer BLW is disposed vertically in the boundary area of the first to fourth subpixels SP1 to SP4. The barrier layer BLW is arranged to correspond to the length of the emission area EMA of the first to fourth subpixels SP1 to SP4. Additionally, the barrier layer BLW is disposed to partially extend to the circuit area DRA of the first to fourth subpixels SP1 to SP4. That is, the barrier layer BLW exists in a partial section or the entire length of the light emitting area EMA and circuit area DRA of the first to fourth subpixels SP1 to SP4.

The barrier layer BLW may be disposed along the boundary area between all subpixels, but may also be disposed only between specific subpixels. For example, it may be placed only in the boundary area between a white subpixel and an adjacent subpixel.

Light-emitting layers included in subpixels have different optical properties, such as color expression, lifespan, and luminance, depending on the material. Therefore, a design is needed to implement similar or identical optical characteristics of subpixels or to compensate for the shortcomings of a specific subpixel. Therefore, in an embodiment of the present invention, subpixels are designed as follows in consideration of the optical characteristics of the light emitting layers, but this is only an example and the present invention is not limited thereto.

The boundary areas of subpixels include an area with a straight section (e.g., the left side of SP1), an area that protrudes to the left and has a non-linear section (e.g., the left side of SP2), and an area that protrudes to the right and has a non-linear section (e.g., right side of SP3), etc. may exist. Accordingly, the barrier layer BLW may have an area having a straight section and an area having a non-straight section (an area including diagonal lines and straight lines) along the boundary areas of the subpixels.

Hereinafter, since the cross-sectional view is similar to the structure of the first embodiment, it is omitted to avoid duplication of description, so the first embodiment will be referred to.

The present invention has the effect of implementing accurate colors and improving display quality by preventing problems such as light reflection, interference, and color mixing (view color blurring) between left and right adjacent subpixels. In addition, the present invention has the effect of improving luminance by preventing the problem of light leakage (blocking light leakage) in which light emitted through a subpixel leaks to other subpixels.

Although embodiments of the present invention have been described with reference to the accompanying drawings, the technical configuration of the present invention described above can be modified by those skilled in the art in the technical field to which the present invention belongs in other specific forms without changing the technical idea or essential features of the present invention. You will understand that it can be done. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the claims described later rather than the detailed description above. In addition, the meaning and scope of the patent claims and all changes or modified forms derived from the equivalent concept should be construed as being included in the scope of the present invention.

110: image processing unit 120: timing control unit
130: data driver 140: scan driver
150: Display panel SP1 to SP4: 1st subpixel to 4th subpixel
EMA: Emission area DRA: Circuit area
BLW: Bulkhead layer OC: Flattening layer

Claims (11)

Subpixels located on a substrate;
at least one signal line located between boundary areas between the subpixels; and
a barrier layer disposed in a boundary area between the subpixels and located on the at least one signal line;
The border area between the subpixels is
an insulating layer located on the at least one signal line,
a planarization layer located on the insulating layer and separated into one side and the other side on the signal line and having a space apart;
a bank layer of an inorganic insulating film covering the planarization layer and the partition layer;
an organic light-emitting layer located on the bank layer,
It includes a cathode electrode layer located on the organic light-emitting layer,
The partition layer includes a first part formed on one side wall of the planarization layer, a second part formed on an upper side of the insulating layer, and a third part formed on the other side wall of the planarization layer, and the planarization layer is spaced apart from each other. Having a sunken space along the space,
The bank layer, the organic light emitting layer formed thereon, and the cathode electrode layer have a recessed area corresponding to the recessed space of the barrier layer in a boundary area between the subpixels. According to paragraph 1,
The partition layer is
A display device arranged vertically along a boundary area between the subpixels. According to paragraph 1,
The partition layer is
an area having a straight section along a boundary area between the subpixels;
A display device that includes an area with non-straight sections including diagonal lines and straight lines. According to paragraph 1,
The partition layer is
Arranged along the boundary area between the light emitting areas of the subpixels,
The light emitting area is a display device where an organic light emitting diode emits light. According to paragraph 4,
The partition layer is
extends to the circuit area of the subpixels,
The circuit area is an area where transistors that drive the organic light emitting diode are located. delete According to paragraph 1,
The partition layer is
A display device located on an upper portion of the planarization layer and a sidewall. forming at least one signal line between boundary areas between subpixels defined on a substrate;
forming an insulating layer on the at least one signal line;
Forming a planarization layer on the insulating layer and patterning the planarization layer to have a space between one side and the other on the signal line;
forming a partition layer in a space separated from the planarization layer;
forming a bank layer of an inorganic insulating film to cover the planarization layer and the barrier layer;
forming an organic light-emitting layer on the bank layer; and
Comprising the step of forming a cathode electrode layer on the organic light-emitting layer,
The barrier layer includes a first part formed on one sidewall of the planarization layer between boundary areas between the subpixels, a second part formed on an upper side of the insulating layer, and a third part formed on the other sidewall of the planarization layer. It includes, and has a depressed space along the separation space of the planarization layer,
The method of manufacturing a display device wherein the bank layer, the organic light emitting layer formed thereon, and the cathode electrode layer have a recessed area corresponding to the recessed space of the barrier layer in a boundary area between the subpixels. delete According to clause 8,
The partition layer is
A method of manufacturing a display device located on an upper portion of the planarization layer and a side wall. delete

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