KR20170064126A - Organic Light Emitting Display Device and Method of Manufacturing the same - Google Patents

Abstract

The present invention prevents the light leakage problem (leakage of light leakage) leaked to other sub-pixels, thereby realizing accurate color and improving display quality. To this end, the present invention places a barrier layer in a boundary region between subpixels.

Description

DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

The present invention relates to a display device and a method of manufacturing the same.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, the use of display devices such as an organic light emitting display (OLED), a liquid crystal display (LCD), and a plasma display panel (PDP) is increasing.

Some of the above-described display devices, for example, a liquid crystal display device and an organic light emitting display device, include a display panel including a plurality of sub-pixels arranged in a matrix form and a driver for driving the display panel. The driving unit includes a scan driver for supplying a scan signal (or a gate signal) to the display panel, and a data driver for supplying a data signal to the display panel.

When a scan signal, a data signal, or the like is supplied to the subpixels, the selected subpixel emits light so that an image can be displayed. The display panel displays the image using light emitted through the sub-pixels. The structure and shape of the subpixels may be different depending on the implementation and manufacturing method of the display panel.

However, in the structure proposed in the prior art, when light reflection, interference, color mixture, or the like occurs between adjacent subpixels, a problem of not realizing accurate color or a problem of degrading display quality is required to be improved .

The present invention for solving the problems of the background art described above is to prevent the problem of light leakage defects leaked to other subpixels (block light leakage) to realize accurate colors and to improve display quality.

The present invention provides a display device including subpixels, at least one signal line, and a barrier rib layer. The subpixels are located on the substrate. At least one signal line is located between the boundary regions between the subpixels. The barrier rib layer is disposed in the boundary region between the subpixels and is located on at least one signal line.

The barrier ribs may be arranged in the longitudinal direction along the boundary region between the subpixels.

The barrier rib layer may include a region having a linear section along a boundary region between subpixels and a region having a nonlinear section including a slanting line and a straight line.

The barrier rib layer is disposed along the boundary region between the light emitting regions of the subpixels, and the light emitting region may be a region where the organic light emitting diode emits light.

The barrier layer extends to the circuit region of the subpixels, and the circuit region may be an area where transistors driving the organic light emitting diode are located.

At least one signal line located on the substrate, at least one signal line, and at least one signal line, the insulating layer being located on the insulating layer and separated from the signal line by one side and the other side, A planarization layer, and a barrier layer positioned in a spaced-apart space of the planarization layer.

The barrier layer may be located on a portion of the upper surface of the planarization layer and on the sidewall.

In another aspect, the present invention provides a method of manufacturing a display device. A method of manufacturing a display device includes forming at least one signal line on a substrate, forming an insulating layer on at least one signal line, forming a planarization layer on the insulating layer, Patterning the planarization layer to have a spaced apart spacing, and forming a barrier wall layer in the spaced apart space of the planarization layer.

The barrier rib layer may be disposed in a boundary region between subpixels located on the substrate.

The barrier layer may be located on a portion of the upper surface of the planarization layer and on the sidewall.

The present invention has the effect of preventing the problem of light reflection, interference, color mixing (visible color unevenness) between right and left adjacent subpixels, realizing accurate color and improving display quality. In addition, the present invention has an effect of preventing a problem of a light leakage failure (light blocking) by which light emitted through sub-pixels leaks to other sub-pixels, thereby improving brightness.

FIG. 1 is a schematic block diagram of an organic light emitting display according to a first embodiment of the present invention. FIG.
2 is a schematic circuit configuration diagram of a subpixel.
3 is a diagram illustrating a specific circuit configuration of a subpixel.
FIG. 4 is a cross-sectional view of a display panel, and FIG. 5 is a plan view of a subpixel. FIG.
Figure 6 is a plan view of a subpixel to illustrate the problem of the conventional structure;
7 is a sectional view of the region A1-A2 in Fig. 6;
8 is a cross-sectional view of the region B1-B2 in Fig. 6;
FIG. 9 is a planar view of subpixels for explaining the structure of the first embodiment of the present invention; FIG.
10 is a sectional view of the region C1-C2 in Fig. 9;
11 is a sectional view of the region D1-D2 in Fig. 9;
12 is a cross-sectional view for helping understanding of the light emitting region and the circuit region of FIG. 9;
13 is a plan view of a subpixel for explaining the structure of a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The display device according to the present invention is implemented as a television, a set-top box, a navigation device, a video player, a Blu-ray player, a personal computer (PC), a home theater and a mobile phone. The display panel of the display device may be selected from a liquid crystal display panel, an organic light emitting display panel, a quantum dot display panel, an electrophoretic display panel, a plasma display panel, and the like, but is not limited thereto. Hereinafter, an organic light emitting display device based on an organic light emitting display panel will be described as an example.

≪ Embodiment 1 >

FIG. 1 is a schematic block diagram of an organic light emitting display according to a first embodiment of the present invention, FIG. 2 is a schematic circuit diagram of subpixels, FIG. 3 is a specific circuit configuration diagram of a subpixel, 4 is a cross-sectional view of a display panel, and Fig. 5 is a plan view of a subpixel.

1, an organic light emitting display according to a first exemplary embodiment of the present invention includes an image processing unit 110, a timing control unit 120, a data driving unit 130, a scan driving unit 140, 150).

The image processing unit 110 outputs a data enable signal DE together with a data signal DATA supplied from the outside. The image processing unit 110 may output at least one of a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of explanation.

The timing controller 120 receives a data signal DATA from a video processor 110 in addition to a data enable signal DE or a driving signal including a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal. The timing controller 120 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 130, .

The data driver 130 samples and latches the data signal DATA supplied from the timing controller 120 in response to the data timing control signal DDC supplied from the timing controller 120 and converts the sampled data signal into a gamma reference voltage . The data driver 130 outputs the data signal DATA through the data lines DL1 to DLn. The data driver 130 may be formed in the form of an IC (Integrated Circuit).

The scan driver 140 outputs a scan signal (or a gate signal) while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 120. The scan driver 140 outputs a scan signal through the scan lines GL1 to GLm. The scan driver 140 is formed in the form of an integrated circuit (IC) or a gate-in-panel (GATE) panel in the display panel 150.

The display panel 150 displays an image corresponding to the data signal DATA and the scan signal supplied from the data driver 130 and the scan driver 140. The display panel 150 includes sub-pixels SP that operate to display an image. The display panel 150 is formed in a top emission mode, a bottom emission mode, or a dual emission mode according to the structure of the subpixels SP.

As shown in FIG. 2, one sub-pixel includes a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light emitting diode OLED.

The switching transistor SW is operated so that a data signal supplied through the first data line DL1 is stored as a data voltage in the capacitor Cst in response to a scan signal supplied through the first scan line GL1. The driving transistor DR operates so that a driving current flows between the first power supply line EVDD and the second power supply line EVSS in accordance with the data voltage stored in the capacitor Cst. The organic light emitting diode OLED operates to emit light in accordance with the driving current generated by the driving transistor DR.

The compensation circuit CC is a circuit added in the sub-pixel to compensate the threshold voltage of the driving transistor DR and the like. The compensation circuit CC is composed of one or more transistors. The configuration of the compensation circuit (CC) varies greatly according to the compensation method. An example of the compensation circuit (CC) is as follows.

As shown in Fig. 3, the compensation circuit CC includes a sensing transistor ST and a sensing line VREF. The sensing transistor ST is connected between a source line of the driving transistor DR and an anode electrode of the organic light emitting diode OLED (hereinafter referred to as a sensing node). The sensing transistor ST operates to supply the initialization voltage (or sensing voltage) transmitted through the sensing line VREF to the sensing node or to sense the voltage or current of the sensing node.

The configuration and connection relationship of the elements included in the sub-pixel together with the compensation circuit CC will be described below.

In the switching transistor SW, the first electrode is connected to the first data line DL1, and the second electrode is connected to the gate electrode of the driving transistor DR. The first electrode of the driving transistor DR is connected to the first power supply line EVDD and the second electrode of the driving transistor DR is connected to the anode electrode of the organic light emitting diode OLED. In the capacitor Cst, the first electrode is connected to the gate electrode of the driving transistor DR, and the second electrode is connected to the anode electrode of the organic light emitting diode OLED.

In the organic light emitting diode OLED, an anode electrode is connected to the second electrode of the driving transistor DR, and a cathode electrode is connected to the second power supply line EVSS. The sensing transistor ST has a first electrode connected to the sensing line VREF and a second electrode connected to the anode electrode of the organic light emitting diode OLED. The first electrode or the second electrode means a source electrode of the transistor (which may be a drain electrode depending on the transistor type) or a drain electrode (which may be a source electrode depending on the type of the transistor).

The operation time of the sensing transistor ST may be similar to or different from the switching transistor SW according to the compensation algorithm (or the configuration of the compensation circuit). For example, the gate electrode of the switching transistor SW may be connected to the first scan line GL1a, and the gate electrode of the sensing transistor ST may be coupled to the first scan line GL1b. As another example, the first scan line GL1a connected to the gate electrode of the switching transistor SW and the first scan line GL1b connected to the gate electrode of the sensing transistor ST may be commonly connected.

The sensing line VREF may be connected to the data driver. In this case, the data driver may sense the sensing node of the subpixel during the non-display period of the real time image, or the N frame (N is an integer of 1 or more) and generate the sensing result value. The switching transistor SW and the sensing transistor ST can be turned on at the same time. In this case, the sensing operation through the sensing line (VREF) and the data output operation for outputting the data signal are separated (separated) based on the time division system of the data driver.

In addition, the object to be compensated based on the sensing result value may be a digital data signal, an analog data signal, gamma, or the like. The compensation circuit for generating the compensation signal (or compensation voltage) based on the sensing result value may be implemented in the interior of the data driver, in the timing controller, or in a separate circuit.

A light blocking layer LSd is formed on the lower or upper layer corresponding to the channel region of the driving transistor DR. The light blocking layer LSd exists to protect and stabilize the driving transistor DR from external light. The light blocking layer LSd serves to cut off external light, and may also be disposed on the lower layer of the switching transistor SW, the sensing transistor ST, and the like.

3, a sub-pixel of a 3T (Capacitor) structure including a switching transistor SW, a driving transistor DR, a capacitor Cst, an organic light emitting diode OLED, and a sensing transistor ST However, if the compensation circuit CC is added, it can be composed of 3T2C, 4T2C, 5T1C, 6T2C, and the like.

As shown in FIG. 4, the display panel 150 includes a pixel P positioned between the substrate 150a and the protective substrate (or film) 150b. The area where the pixel P is arranged is defined as the display area AA and the outline of the display area AA where the pixel P is not arranged is defined as the non-display area NA.

The pixel P is composed of four subpixels of red (R), white (W), blue (B) and green (G) And may consist of more than three subpixels. The red (R), white (W), blue (B) and green (G) subpixels are arranged horizontally or vertically. The arrangement order of the subpixels can be variously changed according to the light emitting material, the light emitting area, the structure (or structure) of the compensation circuit, and the like. Therefore, hereinafter, the first subpixel to the third subpixel or the first subpixel to the fourth subpixel will be referred to.

As shown in FIGS. 5 (a) and 5 (b), in the first subpixel to the third subpixel SP1 to SP3 and the first to fourth subpixels SP1 to SP4, And a circuit area DRA.

The light emitting area EMA corresponds to the light emitting area, and the organic light emitting diode is located in this area. The circuit region DRA corresponds to a region that does not emit light, and a driving transistor or the like for driving the organic light emitting diode is located in this region.

The ratio of the light emitting region EMA to the circuit region DRA and the shape thereof can be variously changed depending on the light emitting material, the light emitting area, the characteristics of the transistor, the structure (or structure) of the compensation circuit,

The structure and shape of the subpixels may vary depending on the implementation and manufacturing method of the display panel. However, when reflection, interference, or color mixing of light occurs between adjacent subpixels, And the like.

Hereinafter, a description will be given of embodiments of the present invention for solving the problem of the conventional structure and solving the problems.

- Conventional structure -

FIG. 6 is a plan view of a subpixel to explain the problem of the conventional structure, FIG. 7 is a sectional view of the region A1-A2 of FIG. 6, and FIG. 8 is a sectional view of the region B1-B2 of FIG.

As shown in FIG. 6, the first to fourth sub-pixels SP1 to SP4 are disposed on the display panel. The first to fourth subpixels SP1 to SP4 may be arranged in the order of red (R), white (W), blue (B), and green (G) subpixels, for example. However, the arrangement order of the subpixels can be variously changed depending on the light emitting material, the light emitting area, the structure (or structure) of the compensation circuit, and the like.

The first scan line GL1a and the first scan line GL1b are arranged in the horizontal direction of the first to fourth sub-pixels SP1 to SP4. A first power supply line (EVDD), a sensing line (VREF), and data lines (DL1 to DL4) are arranged in the longitudinal direction of the first to fourth subpixels (SP1 to SP4).

The first power line EVDD may be disposed on the left side of the first sub-pixel SP1 and the first data line DL1 may be disposed on the right side. The second data line DL2 may be disposed on the left side of the second subpixel SP2 and the sensing line VREF may be disposed on the right side thereof. The sensing line VREF may be disposed on the left side of the third subpixel SP3 and the third data line DL3 may be disposed on the right side. A fourth data line DL4 may be disposed on the left side of the fourth subpixel SP4, and a first power line (not shown) may be disposed on the right side. Hereinafter, the description of the conventional structure will be specified with reference to cross-sectional views.

As shown in FIGS. 6 and 7, a first data line and a second data line DL1 and DL2 are disposed between the first sub-pixel SP1 and the second sub-pixel SP2. That is, two signal lines are disposed between the first sub-pixel SP1 and the second sub-pixel SP2.

Referring to the sectional view of this region, a red color filter (CFR) exists under the planarization layer OC of the first sub-pixel SP1, but a color filter No filter is present.

A bank layer BNK is present above the planarization layer OC of the first sub-pixel SP1 and the second sub-pixel SP2. The bank layer BNK is structured such that the light emitting region EMA existing on the upper portion of the first sub pixel SP1 and the light emitting region EMA existing on the planarization layer OC of the second sub pixel SP2 It separates.

However, in the conventional structure, when the first sub-pixel SP1 corresponding to red displays an image, only the first sub-pixel SP1 should emit light, but the light is emitted toward the adjacent second sub-pixel SP2.

Accordingly, in the conventional structure, even if the first sub-pixel SP1 emits light and the second sub-pixel SP2 emits light or does not emit light, light emitted from the first sub- Emitting region EMA of the pixel SP2 and color mixing occurs.

As shown in FIGS. 6 and 8, a sensing line VREF is disposed between the second sub-pixel SP2 and the third sub-pixel SP3. That is, one signal line is disposed between the second sub-pixel SP2 and the third sub-pixel SP3.

Referring to the sectional view of this region, there is no color filter under the planarization layer OC of the second subpixel SP2, but a blue color filter CFB exists under the third subpixel SP3.

A bank layer BNK is present above the planarization layer OC of the second subpixel SP2 and the third subpixel SP3. The bank layer BNK is structured such that the light emitting region EMA existing on the upper portion of the second subpixel SP2 and the light emitting region EMA existing on the planarization layer OC of the third subpixel SP3 It separates.

However, in the conventional structure, when the third sub-pixel SP3 corresponding to the blue color displays an image, only the third sub-pixel SP3 should emit light, but the light is emitted toward the adjacent second sub-pixel SP2.

Accordingly, in the conventional structure, even if the third sub-pixel SP3 emits light and the second sub-pixel SP2 emits light or does not emit light, the light emitted from the third sub- Emitting region EMA of the pixel SP2 and color mixing occurs.

As described above, in the structure proposed in the related art, when reflection, interference, or color mixing of light occurs between adjacent subpixels, it is required to improve the problem that accurate color can not be realized or a problem that display quality is lowered .

- Structure of the first embodiment -

9 is a plan view of subpixels for explaining the structure of the first embodiment of the present invention, FIG. 10 is a sectional view of the C1-C2 region in FIG. 9, and FIG. 11 is a sectional view of the D1- And FIG. 12 is a sectional view for helping understanding of the light emitting region and the circuit region of FIG.

As shown in FIG. 9, the first to fourth sub-pixels SP1 to SP4 are disposed on the display panel. The first to fourth subpixels SP1 to SP4 may be arranged in the order of red (R), white (W), blue (B), and green (G) subpixels, for example. However, the arrangement order of the subpixels can be variously changed depending on the light emitting material, the light emitting area, the structure (or structure) of the compensation circuit, and the like.

The first scan line GL1a and the first scan line GL1b are arranged in the horizontal direction of the first to fourth sub-pixels SP1 to SP4. A first power supply line (EVDD), a sensing line (VREF), and data lines (DL1 to DL4) are arranged in the longitudinal direction of the first to fourth subpixels (SP1 to SP4).

The first power line EVDD may be disposed on the left side of the first sub-pixel SP1 and the first data line DL1 may be disposed on the right side. The second data line DL2 may be disposed on the left side of the second subpixel SP2 and the sensing line VREF may be disposed on the right side thereof. The sensing line VREF may be disposed on the left side of the third subpixel SP3 and the third data line DL3 may be disposed on the right side. A fourth data line DL4 may be disposed on the left side of the fourth subpixel SP4, and a first power line (not shown) may be disposed on the right side.

The barrier ribs BLW are arranged in the longitudinal direction in the boundary region of the first subpixel to the fourth subpixel SP1 to SP4. The partition wall layer BLW is arranged corresponding to the length of the emission area EMA of the first subpixel to the fourth subpixel SP1 to SP4. That is, the barrier rib BLW does not exist in the circuit area DRA of the first to fourth sub-pixels SP1 to SP4.

The barrier rib BLW may be disposed along a boundary region between all the subpixels, but may be disposed only between a specific subpixel and a specific subpixel. For example, only the boundary region between the white subpixel and the adjacent subpixel can be selectively disposed.

The light emitting layers included in the subpixels have different optical characteristics such as color expressiveness, lifetime, and brightness for each material. Therefore, there is a need for a design to implement similar or equal optical characteristics of subpixels or to compensate for the disadvantages of certain subpixels. Therefore, in the embodiment of the present invention, the subpixels are designed as follows in consideration of the optical characteristics of the light emitting layers, but the present invention is not limited thereto.

The boundary area of the subpixels may be a region having a straight line section (for example, the left side of SP1), a region protruding to the left side having a nonlinear section (for example, left side of SP2), a region protruding to the right side having a non- Right side of SP3) and the like may exist. Accordingly, the barrier rib BLW may have a region having a straight line section along a boundary region of subpixels and a region having a nonlinear section (an area including a slanting line and a straight line).

The partition wall layer (BLW) can be selected from a color pigment or metal material capable of blocking light. Hereinafter, the barrier rib layer BLW is selected as a metal material capable of blocking light.

Hereinafter, the structure of the first embodiment will be described with reference to cross-sectional views.

As shown in FIGS. 9 and 10, a first data line and a second data line DL1 and DL2 are disposed between the first sub-pixel SP1 and the second sub-pixel SP2. That is, two signal lines are disposed between the first sub-pixel SP1 and the second sub-pixel SP2.

Referring to the sectional view of this region, a red color filter (CFR) exists under the planarization layer OC of the first sub-pixel SP1, but a color filter No filter is present.

The planarization layer OC covering the first subpixel SP1 and the second subpixel SP2 is separated into one side and the other side in the boundary region between the first subpixel SP1 and the second subpixel SP2. That is, the planarization layer OC is separated to have mutually spaced spaces between the first data line and the second data line DL1 and DL2. The spacing space of the planarization layer OC may be formed by patterning by an etching method, but is not limited thereto.

The spacing distance between the planarization layers OC in this region is selectable within the line widths of the first and second data lines DL1 and DL2. However, when the spacing distance between the planarization layers OC is out of the outermost range of the line width of the first data line and the second data line DL1 and DL2, the light emitting area EMA becomes narrow. That is, the spacing distance between the planarization layers OC is related to the aperture ratio defining the light-emitting area EMA, and if the spacing is set too wide, the aperture ratio will decrease.

A partition wall layer (BLW) is disposed between the spacing spaces between the planarization layers (OC). The partition wall layer BLW is formed so as to cover the upper part of the separated planarization layer OC and the side wall. The barrier rib BLW serves as a barrier (or barrier) for preventing color mixture and interference (optical interference) between adjacent subpixels.

A bank layer BNK is present above the planarization layer OC of the first sub-pixel SP1 and the second sub-pixel SP2. The bank layer BNK is structured such that the light emitting region EMA existing on the upper portion of the first sub pixel SP1 and the light emitting region EMA existing on the planarization layer OC of the second sub pixel SP2 It separates.

As described above, in the structure of the first embodiment, there is a partition wall BLW serving as a shielding layer for blocking light in a space provided between the first subpixel SP1 and the second subpixel SP2. Therefore, even if the first sub-pixel SP1 emits light and the second sub-pixel SP2 emits light or non-emits light (or vice versa), the light emitted from the first sub-pixel SP1 A color mixing problem or the like emitted to the light emitting area EMA of the second subpixel SP2 does not occur.

As shown in FIGS. 9 and 11, a sensing line VREF is disposed between the second sub-pixel SP2 and the third sub-pixel SP3. That is, one signal line is disposed between the second sub-pixel SP2 and the third sub-pixel SP3. 10 and 11, the line width of the sensing line VREF corresponds to the line width of the first data line and the second data line DL1 and DL2, but this is only one example But is not limited thereto.

Referring to the sectional view of this region, there is no color filter under the planarization layer OC of the second subpixel SP2, but a blue color filter CFB exists under the third subpixel SP3.

The planarization layer OC covering the second subpixel SP2 and the third subpixel SP3 is separated in the boundary region between the second subpixel SP2 and the third subpixel SP3. That is, the planarization layers OC are separated to have mutually spaced spaces on the third data line DL3.

The spacing between the planarization layers OC in this region is selectable within the line width of the sensing line VREF. However, when the spacing distance between the planarization layers OC is out of the outermost range of the line width of the sensing line VREF, the emission area EMA becomes narrow. That is, the spacing distance between the planarization layers OC is related to the aperture ratio defining the light-emitting area EMA, and if the spacing is set too wide, the aperture ratio will decrease.

A partition wall layer (BLW) is disposed between the spacing spaces between the planarization layers (OC). The partition wall layer BLW may be formed to cover the upper part of the separated planarization layer OC and the sidewalls. The barrier rib BLW serves as a barrier (or barrier) for preventing color mixture and interference (optical interference) between adjacent subpixels.

A bank layer BNK is present above the planarization layer OC of the second subpixel SP2 and the third subpixel SP3. The bank layer BNK is structured such that the light emitting region EMA existing on the upper portion of the second subpixel SP2 and the light emitting region EMA existing on the planarization layer OC of the third subpixel SP3 It separates.

As described above, in the structure of the first embodiment, there is a partition wall BLW serving as a shielding layer for blocking light in a space provided between the second subpixel SP2 and the third subpixel SP3. Therefore, even if the third subpixel SP3 emits light and the second subpixel SP2 emits light or emits no light (or the opposite state), the light emitted from the third subpixel SP3 A color mixing problem or the like emitted to the light emitting area EMA of the second subpixel SP2 does not occur.

As described above, the structure of the first embodiment prevents the problem of light reflection, interference, color mixing, etc. between adjacent left and right subpixels, so that accurate color can be realized and the display quality can be further improved as a result. In addition, the structure of the first embodiment can prevent the problem of a light leakage problem in which light emitted through sub-pixels leaks to other sub-pixels (blocks light leakage), thereby improving brightness.

On the other hand, the barrier rib BLW may be formed together with the process of forming the metal layer included in the circuit area DRA of the sub-pixels SP1 to SP4, which will be described below.

As shown in FIGS. 10 to 12, the circuit region of the sub-pixels includes a driving transistor DR electrically connected to the organic light emitting diode OLED. The first electrode or the second electrode of the driving transistor DR is electrically connected to the anode electrode of the organic light emitting diode OLED. Hereinafter, a lamination structure of the driving transistor DR and the organic light emitting diode OLED will be described.

A gate metal layer 151 is formed on the substrate 150a. The gate metal layer 151 may be formed of one or an alloy selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni and Cu. And may be a single layer or a multilayer. The gate metal layer 151 may be a gate electrode of the driving transistor DR and may be patterned and separated into a scan line, a pad electrode, and the like.

A first insulating layer 152 is formed on the gate metal layer 151. The first insulating layer 152 serves to electrically isolate the gate metal layer 151. The first insulating layer 152 may be a single layer or multiple layers of a silicon oxide film (SiOx) or a silicon nitride film (SiNx).

A semiconductor layer 153 is formed on the first insulating layer 152. The semiconductor layer 153 is connected to the source electrode and the drain electrode of the transistor. The semiconductor layer 153 may be selected from a material such as an oxide (IGZO, TiO2, ZnO, WO3, SnO2) or silicon (a-Si, p-Si).

On the semiconductor layer 153, an etch stopper layer (ESL) is formed. The etch stopper layer (ESL) serves to expose a part of the active layer to be a source region and a drain region of the semiconductor layer 153, and to prevent over-etching at the time of patterning. The etch stopper layer (ESL) may be composed of an organic insulating film (photosensitive and non-photosensitive organic insulating film).

First source drain metal layers 154a and 154b (SD1) are formed on the etch stopper layer ESL. The first source and drain metal layers 154a and 154b are patterned and separated by the source and drain electrodes 154a and 154b of the driving transistor DR. The source electrode and the drain electrode 154a and 154b are in contact with the source region and the drain region of the semiconductor layer 153, respectively. The source and drain electrodes 154a and 154b are formed of a material selected from the group consisting of molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni) Or alloys thereof, and may be composed of a single layer or multiple layers.

A second insulating layer 155 is formed on the source drain metal layers 154a and 154b. The second insulating layer 155 serves as a protective film for protecting the source and drain electrodes 154a and 154b. The second insulating layer 155 may be a single layer or multiple layers of a silicon oxide film (SiOx) or a silicon nitride film (SiNx). The second insulating layer 155 has a contact hole exposing the source electrode 154a of the driving transistor DR.

On the second insulating layer 155, second source drain metal layers 156a and 156b (SD2) are formed. The second source and drain metal layers 156a and 156b are electrically connected to the connection electrode 156a in contact with the source electrode 154a of the driving transistor DR and the second gate electrode ). The second source drain metal layers 156a and 156b may be formed of the same material as the first source drain metal layers 154a and 154b, but are not limited thereto. The portion of the second gate electrode (or the upper gate electrode) 156b of the driving transistor DR also serves to block light entering from the top or the side.

A color filter CF is formed on the second gate electrode (or upper gate electrode) 156b. The color filter CF can be selected to be red, green or blue.

A planarization layer OC is formed on the second insulating layer 155 to cover the second source drain metal layers 156a and 156b and the color filter CF. The planarization layer OC serves to planarize the lower surface corresponding to the transistor array. The planarization layer OC has a contact hole exposing the connection electrode 156a in contact with the source electrode 154a. The planarization layer OC may be selected from organic insulating films such as photo-acryl, but is not limited thereto.

An anode electrode layer 157 is formed on the planarization layer OC. The anode electrode layer 157 is electrically connected to the connection electrode 156a. The anode electrode layer 157 may be made of a transparent oxide (e.g., ITO), but is not limited thereto.

On the planarization layer OC, a bank layer BNK defining a light emitting region is formed. The bank layer BNK forms an opening corresponding to the light emitting region of the subpixel or the like. The bank layer BNK may be selected as an organic insulating film or an inorganic insulating film.

An organic light emitting layer 158 is formed on the anode electrode layer 157. The organic light emitting layer 158 includes a light emitting layer that emits red, green, blue, or white light, and a functional layer (a hole injecting layer, a hole transporting layer, an electron transporting layer, an electron injecting layer, etc.) that assists in the recombination of holes and electrons. The organic light emitting layer 158 may be located on the bank layer BNK, but is not limited thereto.

A cathode electrode layer 159 is formed on the organic light emitting layer 158. The cathode electrode layer 159 may be made of an opaque metal (e.g., Al), but is not limited thereto. The cathode electrode layer 159 is formed in common on the entire surface of the display region of the display panel and is electrically connected to the second power supply line inside or outside the display region.

In the case where subpixels are formed with the lamination structure as described with reference to FIG. 12, the partition wall layer BLW described in FIGS. 9 to 11 is formed together with the process of forming the second source drain metal layers 156a and 156b . That is, the partition wall layer BLW may be formed by the same material and the same process as the second source drain metal layers 156a and 156b. However, this is only an example, and if the second source drain metal layers 156a and 156b are not present, they are formed through a separate process.

≪ Embodiment 2 >

13 is a plan view of subpixels for explaining the structure of a second embodiment of the present invention.

As shown in FIG. 13, the first to fourth sub-pixels SP1 to SP4 are disposed on the display panel. The first to fourth subpixels SP1 to SP4 may be arranged in the order of red (R), white (W), blue (B), and green (G) subpixels, for example. However, the arrangement order of the subpixels can be variously changed depending on the light emitting material, the light emitting area, the structure (or structure) of the compensation circuit, and the like.

The first scan line GL1a and the first scan line GL1b are arranged in the horizontal direction of the first to fourth sub-pixels SP1 to SP4. A first power supply line (EVDD), a sensing line (VREF), and data lines (DL1 to DL4) are arranged in the longitudinal direction of the first to fourth subpixels (SP1 to SP4).

The first power line EVDD may be disposed on the left side of the first sub-pixel SP1 and the first data line DL1 may be disposed on the right side. The second data line DL2 may be disposed on the left side of the second subpixel SP2 and the sensing line VREF may be disposed on the right side thereof. The sensing line VREF may be disposed on the left side of the third subpixel SP3 and the third data line DL3 may be disposed on the right side. A fourth data line DL4 may be disposed on the left side of the fourth subpixel SP4, and a first power line (not shown) may be disposed on the right side.

The barrier ribs BLW are arranged in the longitudinal direction in the boundary region of the first subpixel to the fourth subpixel SP1 to SP4. The partition wall layer BLW is arranged corresponding to the length of the emission area EMA of the first subpixel to the fourth subpixel SP1 to SP4. In addition, the barrier rib layer BLW is partially extended to the circuit area DRA of the first to fourth sub-pixels SP1 to SP4. That is, the barrier rib BLW exists in a part or whole length of the light emitting area EMA and the circuit area DRA of the first to fourth sub-pixels SP1 to SP4.

The barrier rib BLW may be disposed along a boundary region between all the subpixels, but may be disposed only between a specific subpixel and a specific subpixel. For example, only in the boundary region between the white subpixel and the adjacent subpixel.

The light emitting layers included in the subpixels have different optical characteristics such as color expressiveness, lifetime, and brightness for each material. Therefore, there is a need for a design to implement similar or equal optical characteristics of subpixels or to compensate for the disadvantages of certain subpixels. Therefore, in the embodiment of the present invention, the subpixels are designed as follows in consideration of the optical characteristics of the light emitting layers, but the present invention is not limited thereto.

The boundary area of the subpixels may be a region having a straight line section (for example, the left side of SP1), a region protruding to the left side having a nonlinear section (for example, left side of SP2), a region protruding to the right side having a non- Right side of SP3) and the like may exist. Accordingly, the barrier rib BLW may have a region having a straight line section along a boundary region of subpixels and a region having a nonlinear section (an area including a slanting line and a straight line).

Hereinafter, the cross-sectional view is similar to the structure of the first embodiment, and thus duplication of description is omitted in order to avoid duplication, so that the first embodiment will be referred to.

As described above, the present invention prevents the problem of light reflection, interference, color mixing (visible color unevenness) between adjacent left and right subpixels, thereby realizing accurate color and improving display quality. In addition, the present invention has an effect of preventing a problem of a light leakage failure (light blocking) by which light emitted through sub-pixels leaks to other sub-pixels, thereby improving brightness.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

110: image processor 120: timing controller
130: Data driver 140:
150: display panel SP1 to SP4: first to fourth sub-
EMA: Emissive area DRA: Circuit area
BLW: partition wall layer OC: planarization layer

Claims (10)

Subpixels located on a substrate;
At least one signal line located between boundary regions between the subpixels; And
And a barrier layer disposed in a boundary region between the subpixels and positioned on the at least one signal line. The method according to claim 1,
The partition wall layer
Pixels arranged in a vertical direction along a boundary region between the subpixels. The method according to claim 1,
The partition wall layer
A region having a straight line section along a boundary region between the subpixels,
And a region having a nonlinear section including a diagonal line and a straight line. The method according to claim 1,
The partition wall layer
Pixels arranged in a boundary region between the emission regions of the subpixels,
Wherein the light emitting region is an area where the organic light emitting diode emits light. 5. The method of claim 4,
The partition wall layer
Pixels to the circuit area of the subpixels,
Wherein the circuit region is an area where transistors for driving the organic light emitting diode are located. The method according to claim 1,
In the boundary region between the subpixels
An insulating layer located on the at least one signal line,
A planarization layer disposed on the insulating layer and separated from the signal line on one side and the other side,
And the barrier layer positioned in a spaced-apart space of the planarization layer. The method according to claim 6,
The partition wall layer
Wherein the planarization layer is located on a part of the upper part of the planarization layer and the side wall. Forming at least one signal line on the substrate;
Forming an insulating layer on the at least one signal line;
Forming a planarization layer on the insulating layer, patterning the planarization layer so as to have a space separated on one side and the other side on the signal line; And
And forming a barrier rib layer in the spacing space of the planarization layer. 9. The method of claim 8,
The partition wall layer
Wherein the plurality of subpixels are arranged in a boundary region between subpixels positioned on the substrate. 9. The method of claim 8,
The partition wall layer
Wherein the flattening layer is located in a part of the upper part of the planarizing layer and the sidewall of the flattening layer.

Images