KR20170027226A - A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for power amplification using MCP(Multi Chip Package) power control - Google Patents

Abstract

The present invention relates to a voltage converter for converting from alternating current and direct current power sources with high voltage into a direct current power source with low voltage. The voltage converter does not have an additional configuration of a common transformation circuit or a configuration of a Zener diode, but has a configuration of a depletion N-type metal oxide semiconductor (NMOS) field effect transistor (FET) having negative voltage between a gate and a source (negative Vgs). In other words, the voltage converter includes a negative threshold voltage five-terminal NMOS FET element. Accordingly, a low cost circuit can be realized by removing the configuration of the common transformation circuit (100) and a circuit region of the Zener diode (104), so as to remove the area occupied in the common transformation circuit (100) and the circuit region of the Zener diode (104).

Description

FIELD OF THE INVENTION [0001] The present invention relates to a power supply circuit device using a 5-terminal NMOS transistor device, and more particularly, to a power supply circuit device using MCP (Multi Chip Package) step connection for power amplification using MCP (Multi Chip Package) power control}

(EN) A voltage converting apparatus for converting a high voltage alternating current and a direct current power source into a low voltage direct current power source, the constitution of the circuit region of the transformer circuit (100) and the zener diode (104) ) And zener diode (104) circuit area, thereby realizing a low-cost circuit and preventing standby and operation power loss, thereby realizing a circuit without power consumption in standby and operation power supply state And a power supply circuit device capable of implementing a free voltage operation using a negative threshold voltage emmos transistor element.

In a voltage converting apparatus for converting a high voltage AC power source to a low voltage DC power source, the normal voltage transforming circuit 100 is a circuit region causing a large area and cost in the circuit configuration.

Therefore, it becomes an obstacle factor in constructing a low cost circuit. On the other hand, the circuit region of the Zener diode 104 is arranged in parallel with the output terminal of the rectifying circuit 102 in order to secure the output voltage characteristic of the constant voltage.

At this time, a constant current is allowed to flow through the Zener diode 104 in the standby or operating power supply state, thereby securing the output voltage characteristic of the constant voltage from the output voltage. Therefore, a certain amount of standby or operation power is lost in standby or operating power supply.

In order to solve such a problem, it is necessary to construct a circuit without power loss in standby and operation power supply states. Particularly, in terms of energy saving, a circuit configuration without power loss in a standby state is desperately needed.

In addition, a circuit having the same characteristics as described above is also required when converting the voltage of the DC power source such as the automobile power supply to a low voltage.

In recent years, the role of surge protection to protect the system from system transients and lightning-induced transients in the field of communication and ESD (electrostatic discharge) protection to protect circuits against static electricity in mobile communication terminals, notebook PCs, A PN varistor is required.

It is used as a surge absorbing element to prevent a sudden change in voltage (surge) to appliances such as various information devices and control devices. It is used in various parts ranging from power devices such as power plants, substations, and power stations to the core devices of lightning arresters for safeguarding equipment from lightning strikes.

Accordingly, there is a strong demand for protecting the system from power surges, ridiculous surges, and the like that occur in these devices.

A surge protection device (SPD, VTMS, or Transient Voltage Surge Suppressor: TVSS) is used in order to prevent surges from destroying or malfunctioning electronic equipment installed in the power system from such transient external surges. Should be installed.

The embodiment of the present invention has the following features.

First, the circuit area of the normal transformer circuit 100 and the zener diode 104 is removed to remove the area occupied in the circuit area of the transformer circuit 100 and the zener diode 104, Which makes it possible to implement a cost circuit.

Second, by eliminating the configuration of the circuit region of the normal transformer circuit 100 and the zener diode 104, it is possible to realize a circuit free from power consumption in standby and operation power supply state by interrupting standby and operation power loss .

Third, a negative threshold Vt depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) critical high voltage (about 1000V or higher) A free voltage operation can be realized.

Fourth, a depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) having a negative threshold Vt, that is, a negative Vgs characteristic, effect transistors, i.e., elements of a negative threshold 5-terminal NMOS FET, to enable stable operation in the operational characteristics of the circuit. .

Fifth, even when the voltage of the DC power source such as the automobile power source is converted into the DC voltage of the low voltage, the same circuit can be used to implement it.

Sixth, it is possible to realize the function of PN varistor as the role of power surge, Brain Brain surge, and electrostatic discharge (ESD) protection.

Seventh, when N negative threshold voltage 5-terminal NMOS FETs are constructed by the step connection method, the voltage of N times of Vgs and the voltage of N times of Vgs at the final stage are realized. . ≪ / RTI >

Eighth, N times of voltage is used as the power source of the control circuit to control the gate voltage of the negative threshold 5-terminal NMOS FET at a high voltage to amplify the power Amplification) is possible.

Ninth, power saving mode can be implemented by disabling (turning off) power supply of internal control circuit by setting power save mode by detecting power ON current state and OFF state of power load current .

Tenth, Negative Threshold Voltage of Power Save Driver We use 5-terminal NMOS FET device to supply leakage current component of Power Amp supply terminal to realize power saving mode. And the like.

In addition, it is a method used when a plurality of chips or dies are stacked on one package to vary power capacity output from one package.

That is, if N or more output stages of P0 output are connected in parallel for each die or die, the total output is a power supply device that realizes a power increase of N times by P0 × N.

A voltage converting apparatus for converting a high-voltage alternating current and a direct-current power source into a low-voltage direct-current power source, the configuration of the transformer circuit 100 is usually removed to save a large area and power consumption in the constitution of the transformer circuit 100 So that a low-cost circuit can be constituted. In addition, the structure of the Zener diode 104 circuit area is removed to reduce the area occupied in the circuit area of the Zener diode 104, and the standby and operation power consumption, And to realize a circuit without power loss in standby and operation power supply states.

In addition, since the input voltage of the high voltage AC and DC power supplies must operate over a wide voltage range, it is required to have such an operating characteristic that the same output voltage characteristics can be maintained in all voltage operating ranges. And a free voltage operation characteristic.

A depletion NMOS transistor having a negative threshold voltage, that is, a voltage between negative gate sources (negative Vgs), in a voltage converter for converting AC and DC power to a voltage of a DC power source, Includes a configuration of a field effect transistor (FET), that is, a configuration of a negative threshold 5-terminal NMOS FET. The negative threshold 5-terminal NMOS FET includes a drain D, a gate G, a source S, a body B, And a 5-terminal of a P-substrate (P-substrate). The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET may be a negative value such as -1V, -2V, -3V, -4V, . The gate is connected to the ground terminal of the P-substrate and the drain D is connected to the terminal to which power is supplied before the voltage conversion. -1 power supply terminal, respectively.

As described above, the embodiment of the present invention has the following effects.

First, the circuit area of the normal transformer circuit 100 and the zener diode 104 is removed to remove the area occupied in the circuit area of the transformer circuit 100 and the zener diode 104, Thereby enabling implementation of a cost circuit.

Second, by eliminating the configuration of the circuit region of the normal transformer circuit 100 and the zener diode 104, it is possible to realize a circuit free from power consumption in standby and operation power supply state by interrupting standby and operation power loss do.

Third, the input voltage of AC and DC power supplies of high voltage must operate over a wide voltage range. Therefore, it is required to have such an operating characteristic that the same output voltage characteristics can be maintained in all voltage operating ranges. (About 1000 V or more) power supply voltage range.

Fourth, a depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) having a negative threshold Vt, that is, a negative Vgs characteristic, transistor, or a negative threshold 5-terminal NMOS FET), so that a stable operation can be realized in the operational characteristics of the circuit. Effect.

Fifth, the same circuit can be used to convert a voltage of a DC power source such as a vehicle power source into a DC voltage of a low voltage.

Sixth, it is possible to implement a PN varistor function as a role of power surge, rational brace, and electrostatic discharge (ESD) protection.

Seventh, when N negative threshold voltage 5-terminal NMOS FETs are constructed by the step connection method, the voltage of N times of Vgs and the voltage of N times of Vgs at the final stage are realized. The present invention provides an effect that is feasible.

Eighth, N times of voltage is used as the power source of the control circuit to control the gate voltage of the negative threshold 5-terminal NMOS FET at a high voltage to amplify the power Amplification can be realized.

Ninth, power saving mode can be implemented by disabling (turning off) power supply of internal control circuit by setting power saving mode by detecting the ON (ON) state and the OFF (OFF) state of power load current Thereby providing a characteristic effect.

Tenth, Negative Threshold Voltage of Power Save Driver We use 5-terminal NMOS FET device to supply leakage current component of Power Amp supply terminal to realize power saving mode. The present invention provides an advantageous effect that it is possible.

In addition, it is a method used when a plurality of chips or dies are stacked on one package to vary power capacity output from one package.

That is, if N or more outputs connected in parallel to the output terminals of P0 are connected to each die or die, the total output provides an effect that Pout is N times the power increase of P0xN.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a configuration diagram of a voltage conversion circuit using a normal transformer circuit and a zener diode; Fig.
2 is a terminal block diagram of a negative threshold 5-terminal NMOS FET of the present invention.
3 is an operational characteristic diagram of a negative threshold 5-terminal NMOS FET of the present invention.
4 is a configuration diagram of a power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.
FIG. 5 is an operational waveform diagram of a power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention. FIG.
6 is a cross-sectional view of a MCP (Multi Chip Package) of a power amplification voltage conversion circuit using a negative threshold 5-terminal NMOS FET of the present invention.
7 is a connection arrangement diagram of an MCP (Multi Chip Package) of a power amplification voltage conversion circuit using a negative threshold 5-terminal NMOS FET of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a voltage conversion circuit using a normal transformer circuit and a zener diode.

A rectifying circuit 102 and a zener diode 104 in a voltage converting apparatus for converting an AC input power supply 100 into a low voltage DC power supply voltage do. The transformer circuit 100 is a circuit region for converting a high voltage input power source to a low voltage.

The rectifying circuit 102 is a circuit region composed of a half-wave or full-wave rectifying diode for converting an AC power source to a DC power source. The transformer circuit 100 is usually a circuit area that causes a large area and cost in the construction of the circuit.

Therefore, it becomes an obstacle factor in constructing a low cost circuit.

On the other hand, the circuit region of the Zener diode 104 is arranged in parallel with the output terminal 103 of the rectifying circuit 102 in order to secure the output voltage characteristic of the constant voltage.

The output terminal 103 of the rectifying circuit 102 is used as the final output Step-1 power supply terminal 105. [

At this time, a constant current flows to the Zener diode in the standby or operating power supply state, thereby securing the output voltage characteristic of the constant voltage from the output voltage. Therefore, a certain amount of standby or operation power is lost in standby or operating power supply.

2 is a terminal block diagram of a negative threshold 5-terminal NMOS FET of the present invention.

A configuration of a depletion NMOS field effect transistor (FET) having a negative threshold voltage Vt, that is, a voltage between negative gate sources (negative Vgs) And a configuration of a threshold voltage 5-terminal NMOS FET.

The negative threshold 5-terminal NMOS FET includes a drain D, a gate G, a source S, a body B, And a 5-terminal of a P-substrate (P-substrate).

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET may be a negative value such as -1V, -2V, -3V, -4V, .

The body (B) terminal may be connected to a common ground terminal for supplying a ground voltage of 0 V according to a design selection method, and to the source (S) terminal A second connection method is available which is used as an output terminal.

More specifically,

As a first method, the gate (G) terminal, the body (B) terminal and the P-substrate (P-sub) terminal are connected to a common ground terminal Respectively.

As another second selection method, the gate (G) terminal and the P-substrate (P-sub) terminal are respectively connected to a common ground terminal for supplying a ground voltage of 0V, (body: B) terminal is connected to the source (S) terminal and is used as an output terminal.

And the gate (G) terminal may be supplied with a separate control voltage.

The drain (D) terminal is a semiconductor doping region having an n-type semiconductor characteristic, and is a terminal configuration for connecting to a power supply. The drain (D) terminal is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

In addition, the drain (D) terminal region may surround the body (B) terminal and the source (S) terminal region and may be included in the drain (D) terminal region.

The drain (D) terminal region is directly contacted with a P-substrate (P-sub) terminal to form a PN varistor structure.

The PN varistor is connected in parallel to the drain (D) terminal region to be protected. The PN varistor acts as a nonconductor at a constant voltage or lower, but it does not affect the circuit. However, when a certain voltage or more is applied, the PN varistor connected in parallel becomes a conductor, - P-substrate (P-sub) terminal to protect the device from surge.

Additional operating characteristics of the PN varistor structure are as follows.

Varistors are short for variable resistors, sometimes called VDRs (Voltage-Dependent Resistors). The role of the PN varistor is a semiconductor device whose resistance varies according to the input voltage, as can be expected from the above name.

A typical PN varistor is characterized by a nonlinear I-V plot, which acts as an insulator for electricity until a certain breakdown voltage, but after the breakdown voltage it exhibits the nature of the conductor.

When a low voltage microprocessor is used in a system or device, a surge that occurs when a lightning strike or switch is opened can cause system stoppage, equipment burnout or deterioration, data transmission error, communication error, The failure of the system, such as inoperability, can occur momentarily. This is a big weakness of the system using the semiconductor. To protect this weak point, a PN varistor is needed.

The source S terminal is a semiconductor doping region having an n-type semiconductor characteristic and is used as an output terminal for obtaining a target output power supply voltage. The source (S) terminal may be connected to the body (B) terminal as an output terminal, or may be used as an output terminal using only the source (S) terminal. .

3 is an operational characteristic diagram of a negative threshold 5-terminal NMOS FET of the present invention.

A negative threshold voltage at the Vds between the gate (G) terminal and the source (S) terminal, Vgs, and the current between the drain (D) terminal and the source (S) A threshold voltage value of a voltage 5-terminal NMOS FET is characterized by having a negative value (VT).

4 is a configuration diagram of a power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.

The rectifying circuit 401 is a circuit region composed of a half-wave or full-wave rectifying diode for converting an AC power source into a DC power source. In addition, the present invention is also applicable to a rectifier diode configured to convert DC power to DC power.

That is, the present invention is characterized in that the rectifier diode can be used as a rectifier diode configured to be connected to a DC power source regardless of the polarity of the DC power source.

An input power supply 400 is connected to the input terminal of the rectifier circuit 401. The rectified output terminal 1 is connected to the rectified output terminal 402 of the rectifier circuit 401, The ground terminal (0) is connected to the common ground terminal (GND).

The rectifying output terminal 402 of the rectifying circuit 401 is connected to a drain of a plurality of N negative threshold 5-terminal NMOS FETs 403, 409, 415, D) terminals 404 (410; 416; 422).

The connection configuration of the first negative threshold voltage 5-terminal NMOS FET 403 is as follows.

The gate terminal G 405 of the negative threshold 5-terminal NMOS FET 403 and the P-substrate P-sub terminal 405 of the negative threshold voltage 5- 406 are respectively connected to a common ground terminal for supplying a ground voltage of 0V.

The source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403 is connected to a semiconductor doping (not shown) having n-type semiconductor characteristics 1 power supply terminal 408, which is an output terminal for obtaining a target output power supply voltage in a doping region.

The source S terminal 407 is commonly connected to the body (B) terminal of the negative threshold 5-terminal NMOS FET 403, And may have an optional characteristic that may be used as an output terminal using only the source (S) terminal 407. [

The drain (D) terminal 404 is a terminal configuration for connecting a power source to a semiconductor doping region having n-type semiconductor characteristics. The drain (D) terminal 404 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 403 is, for example, -1 V, -2 V, -3 V, And has a negative value.

The gate (G) terminal 405 and the P-substrate (P-sub) terminal 406 are connected to a common ground terminal for supplying a ground voltage of 0V, respectively.

The source (S) terminal 407 is a semiconductor doping region having an n-type semiconductor characteristic and has a step-1 power supply terminal 408 as an output terminal for obtaining a target output power supply voltage. Is used.

The connection configuration of the second negative threshold voltage 5-terminal NMOS FET 409 is as follows.

The gate terminal G 411 of the negative threshold 5-terminal NMOS FET 409 and the P-substrate (P-substrate) terminal 411 of the negative threshold voltage 5-terminal NMOS FET 409 412 are respectively connected to a common ground terminal for supplying a ground voltage of 0V.

The source (S) terminal 413 of the negative threshold 5-terminal NMOS FET 409 is a semiconductor doping having an n-type semiconductor characteristic 2 power supply terminal 414, which is an output terminal for obtaining a target output power supply voltage in a first-doping region.

The source (S) terminal 413 is connected in common to the body (B) terminal of the negative threshold 5-terminal NMOS FET 409, And may have an optional characteristic that may be used as an output terminal using only the source (S) terminal 413.

The drain (D) terminal 410 is a semiconductor doping region having an n-type semiconductor characteristic, and is a terminal configuration for connecting to a power supply. The drain (D) terminal 410 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 409 may be, for example, -1 V, -2 V, -3 V, And has a negative value.

The gate (G) terminal 411 of the negative threshold 5-terminal NMOS FET 409 is connected to the negative threshold voltage 5-terminal NMOS transistor (negative) (S) terminal 407 of the threshold 5-terminal NMOS FET 403 or the Step-1 power supply terminal 408 serving as an output terminal. The P-substrate (P-sub) terminal 412 is connected to a common ground terminal for supplying a ground voltage of 0V, respectively.

The source (S) terminal 413 is a semiconductor doping region having n-type semiconductor characteristics, and a Step-2 power supply terminal 414 serving as an output terminal for obtaining a target output power supply voltage. Is used.

The connection configuration of the Nth negative threshold voltage 5-terminal NMOS FET 415 is as follows.

The gate terminal G 417 of the negative threshold 5-terminal NMOS FET 415 and the P-substrate P-sub terminal 417 of the negative threshold voltage 5- 418 are respectively connected to a common ground terminal for supplying a ground voltage of 0V.

The source terminal 419 of the negative threshold 5-terminal NMOS FET 415 is connected to a semiconductor doping (not shown) having n-type semiconductor characteristics N power supply terminal 420, which is an output terminal for obtaining a target output power supply voltage as a power supply voltage and a doping region.

The source (S) terminal 420 is commonly connected to the body (B) terminal of the negative threshold 5-terminal NMOS FET 415, And may have an optional characteristic that may be used as an output terminal using only the source (S) terminal 420.

The drain (D) terminal 416 is a terminal configuration for connecting a power source to a semiconductor doping region having n-type semiconductor characteristics. The drain (D) terminal 416 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 415 is set to a value of, for example, -1 V, -2 V, -3 V, And has a negative value.

The gate (G) terminal 417 of the negative threshold 5-terminal NMOS FET 415 is connected to the negative threshold voltage 5-terminal NMOS transistor 415 (S) terminal 413 of the threshold 5-terminal NMOS FET 409 or the Step-2 power supply terminal 414 which is an output terminal.

The P-substrate (P-sub) terminal 418 is connected to a common ground terminal for supplying a ground voltage of 0V, respectively.

The source (S) terminal 419 is a semiconductor doping region having an n-type semiconductor characteristic and has a step-N power supply terminal 420 as an output terminal for obtaining a target output power supply voltage. Is used.

Multiple N means one or more natural numbers. The source terminal S (N-1) or the output terminal Step- (N-1) of the negative threshold 5-terminal NMOS FET The next step is to connect the gate to the gate (G) terminal of the threshold voltage 5-terminal NMOS FET.

The control circuit is constituted by using the N-folded Step-N power supply terminal voltage generated as the power source.

The control circuit is composed mainly of an amplifier (OP amplifier) 430.

The power supply of the control circuit such as the amplifier (OP amplifier) 430 is supplied through the power supply isolation switch 453.

The power insulated switch 453 is configured as an ON / OFF switch and is operated so that the ON and OFF states are controlled by a power saving mode control signal 451.

In the normal operation mode, the power insulator switch 453 is in the ON state and the power insulator switch 453 is in the OFF state in the power save mode.

The power save mode control (451) circuit area is a circuit configuration for controlling the power save mode.

The power saving mode control 451 circuit area generates an activation and deactivation signal according to a signal of a load current ON / OFF sensing circuit 450.

The signal of the load current ON / OFF sensing (450) circuit is a circuit configuration for detecting whether the load current of the power amplifier supply terminal (426) is used or not.

It generates a deactivation (OFF) signal when no load current is present and an ON (ON) signal when there is a load current.

When there is no load current, the power insulated switch 453 is in the OFF state in the power saving mode, so that the power amp supply terminal 426 is disconnected from the current supply.

In this power saving mode, a power saving driver 465 is configured to supply a leakage current component of the power amplifier supply terminal 426. The configuration of the Power Save Driver 465 consists of a negative threshold 5-terminal NMOS FET 465.

 The gate (G) terminal 467 of the negative threshold 5-terminal NMOS FET 465 is connected to the Power Save Driver Gate Bias Control.

The Power Save Driver Gate Bias Control circuit is used to set the voltage of the source (S) terminal 469 of the negative threshold 5-terminal NMOS FET 465 Bias voltage is generated.

The drain (D) terminal 466 of the negative threshold 5-terminal NMOS FET 465 is common to the rectifying output terminal 402 of the rectifying circuit 401 Lt; / RTI >

The source (S) terminal 469 of the negative threshold 5-terminal NMOS FET 465 is connected to a semiconductor doping (not shown) having n-type semiconductor characteristics amp; power supply terminal 426, which is an output terminal for obtaining a target output power supply voltage in a " doping " region.

The source (S) terminal 469 is commonly connected to the body (B) terminal of the negative threshold 5-terminal NMOS FET 465, And may have an optional feature that may be used as the Power Amp power supply terminal 426 using only the source (S) terminal 469.

A P-substrate (P-sub) terminal 468 is connected to a common ground terminal for supplying a ground voltage of 0V, respectively.

The reference voltage REF 441 is input to one terminal of the control circuit amplifier (OP amplifier) 430, and the other terminal is directly connected to the power amplifier terminal 426, which is a final power output terminal, One sensing voltage Vs 429 is input.

The reference voltage REF 441 is the voltage of the intermediate connection line in the serial connection configuration of the resistor element R 442 and the Zener diode 440.

The other terminal of the resistance element R1 442 is connected to the Step-N power supply terminal through the power isolation switch 453 and to the other ground terminal of the Zener diode 440.

Meanwhile, the other terminal of the resistor R1 442 is connected to any one of the Step-1 power supply terminal, the Step-2 power supply terminal, or the Step-N power supply terminal.

The control output voltage of the Zener diode 440 is equal to the reference voltage REF 441.

The resistance element R1 442 serves as a control resistance element for supplying a minimum bias voltage for generating the control output voltage of the Zener diode 440. [

The voltage of the output terminal 431 of the control circuit amplifier (OP amplifier) 430 is a negative threshold 5-terminal NMOS FET 421, which is a power amplifier element. To the gate (G) terminal 423 of the flip-flop.

The negative (D) terminal 422 of the negative threshold 5-terminal NMOS FET 421 is common to the rectified output terminal 402 of the rectifying circuit 401 Lt; / RTI >

The source (S) terminal 425 of the negative threshold 5-terminal NMOS FET 421 is a semiconductor doping having an n-type semiconductor characteristic amp; power supply terminal 426, which is an output terminal for obtaining a target output power supply voltage in a " doping " region.

The source (S) terminal 425 is connected in common to the body (B) terminal of the negative threshold 5-terminal NMOS FET 421, And may have an optional feature that may be used as the Power Amp power supply terminal 426 using only the source (S) terminal 425. [

The Power Amp power supply terminal 426 is applied to a high current supply capability and a high power consumption load. Accordingly, the negative threshold 5-terminal NMOS FET 421 becomes a device of a power amplifier having a high power driving capability.

The P-substrate (P-sub) terminal 424 of the negative threshold 5-terminal NMOS FET 421 is connected to a ground terminal Respectively, to a common ground terminal.

5 is an operational waveform diagram of a power amplification voltage conversion circuit using the negative threshold voltage 5-terminal NMOS FET of the present invention.

The input power source 500 passes through a rectifier circuit and is input to a drain (D) terminal 404 of a negative threshold 5-terminal NMOS FET 403.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 403 is, for example, -1 V, -2 V, -3 V, And has a negative value.

The gate (G) terminal 405 and the P-substrate (P-sub) terminal 406 are connected to a common ground terminal for supplying a ground voltage of 0V, respectively.

The voltage of the Step-1 power supply terminal 508 of the source S terminal 407 is lower than the threshold voltage Vt of the negative threshold 5-terminal NMOS FET : + 1V, + 2V, + 3V, + 4V, and the like, respectively, corresponding to the output voltage Vgs.

Further, the voltage is increased by the threshold voltage (Vgs) of the negative threshold voltage 5-terminal NMOS FET for each step.

Therefore, when N negative threshold voltage 5-terminal NMOS FETs are constructed in this way, voltages of N times of Vgs and voltages of N times Vgs can be obtained at the final stage .

Power Amp power supply terminal 526 is applied to high current supply capability and high power consumption load. Therefore, by designing to have the Power Amp power supply terminal 526 that is lower than the voltage of Step-N power supply terminal 520 which is N times the voltage, it is designed to be a device of Power Amplifier having high power driving capability under high Vgs voltage driving condition .

6 is a cross-sectional view of an MCP (Multi Chip Package) of a power amplification voltage conversion circuit using a negative threshold 5-terminal NMOS FET of the present invention.

A method of stacking a plurality of chips or dies on a single package may be classified into an internal stack module (ISM) in which a plurality of chips are stacked in one package, There is a stacked PoP (Package on Package).

The reason why a plurality of chips or dies are stacked in one package is a method used to vary the power capacity output from one package.

That is, if N or more outputs connected in parallel to the output terminal of P0 output for each die or die, Pout can predict N times power increase by P0xN.

 For example, a Step-1 power supply terminal (Die-Level 1), a Step-1 power supply terminal (Die-Level 2), a Step-1 power supply terminal (Die- 1 power supply terminal (Die-LevelN) are connected together to obtain an integrated Step-1 power supply terminal (PKG). At this time, the output of the integrated Step-1 power supply terminal PKG is connected to the Step-1 power supply terminal Die-Level 1, the Step-1 power supply terminal Die-Level 2, The supply terminal (Die-Level 3), and the Step-1 power supply terminal (Die-Level N).

7 is a connection configuration diagram of an MCP (Multi Chip Package) of a power amplification voltage conversion circuit using a negative threshold 5-terminal NMOS FET of the present invention.

Step-1 power supply terminals (Die-Level 1), Step-1 power supply terminals (Die-Level 2), Step-1 power supply terminals (Die- (Die-Level N) are connected together to obtain an integrated Step-1 power supply terminal (PKG). At this time, the output of the integrated Step-1 power supply terminal PKG is connected to the Step-1 power supply terminal Die-Level 1, the Step-1 power supply terminal Die-Level 2, The supply terminal (Die-Level 3), and the Step-1 power supply terminal (Die-Level N).

Step-2 power supply terminals (Die-Level 1), Step-2 power supply terminals (Die-Level 2), Step-2 power supply terminals By integrating and connecting the supply terminals (Die-Level N), an integrated Step-2 power supply terminal (PKG) can be obtained. At this time, the output of the integrated Step-2 power supply terminal PKG is connected to the Step-2 power supply terminal Die-Level 1, the Step-2 power supply terminal Die-Level 2, The supply terminal (Die-Level 3), and the Step-2 power supply terminal (Die-Level N).

Each die has a power amplifier power supply terminal (Die-Level 1), a Power Amp power supply terminal (Die-Level 2), a Power Amp power supply terminal (Die-Level 3), and a Power Amp power supply terminal -LevelN) can be integrated to provide an integrated Power Amp power supply terminal (PKG). At this time, the output of the integrated power amplifier power supply terminal PKG is connected to the power amplifier terminal (Die-Level 1), the power amplifier power supply terminal (Die-Level 2), the power amplifier power supply terminal -Level 3), and Power Amp power supply terminal (Die-Level N).

100 input power
101 transformer circuit
102 rectifier circuit
104 Zener diode
105 Step-1 Power supply terminal
400 input power
401 rectifier circuit
403 negative threshold voltage 5-terminal NMOS FET with negative threshold
404 drain (D) terminal
405 gate (G) terminal
406 P-substrate (P-sub) terminal
407 source (S) terminal
408 Step-1 power supply terminal
414 Step-2 power supply terminal
420 Step-N power supply terminal
426 Power Amp power supply terminal

Claims (4)

1. A power supply apparatus for converting a high-voltage AC or DC input power supply to an output voltage of low voltage,
An internal stack module (ISM) configuration in which a plurality of dies are stacked in one package; And
Step-1 power supply terminals (Die-Level 1), Step-1 power supply terminals (Die-Level 2), Step-1 power supply terminals One Package Integrated Step-1 power supply terminal (PKG) connecting the supply terminal (Die-Level N); And
Step-2 power supply terminal (Die-Level 3), Step-2 power supply terminal (Die-Level 3), and Step-2 power supply terminal One package integrated Step-2 power supply terminal (PKG) for connecting the supply terminal (Die-Level N); And
A plurality of dies are provided with respective power amplifier power supply terminals Die-Level 1, Power Amp power supply terminals Die-Level 2, Power Amp power supply terminals Die-Level 3, and Power Amp power supply terminals Die And a Package Integrated Power Amp power supply terminal (PKG) for connecting the power supply voltage (-LevelN). The method according to claim 1,
The package type is an MCP (Multi Chip Package) power supply device based on TSV (Through Silicon Via). The method according to claim 1,
The package type is a Multi Chip Package (MCP) power supply based on a PoP (Package on Package) basis. 1. A power supply apparatus for converting a high-voltage AC or DC input power supply to an output voltage of low voltage,
An internal stack module (ISM) configuration in which a plurality of dies are stacked in one package; And
Step-1 power supply terminals (Die-Level 1), Step-1 power supply terminals (Die-Level 2), Step-1 power supply terminals One Package Integrated Step-1 power supply terminal (PKG) connecting the supply terminal (Die-Level N); And
Step-2 power supply terminal (Die-Level 3), Step-2 power supply terminal (Die-Level 3), and Step-2 power supply terminal One package integrated Step-2 power supply terminal (PKG) for connecting the supply terminal (Die-Level N); And
A plurality of dies are provided with respective power amplifier power supply terminals Die-Level 1, Power Amp power supply terminals Die-Level 2, Power Amp power supply terminals Die-Level 3, and Power Amp power supply terminals Die And a package integrated power amp power supply terminal (PKG) that connects the power supply voltage (-LevelN) to the power supply terminal (PKG).

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