KR20170005102A - N-계승 전압 모드 드라이버 - Google Patents

N-계승 전압 모드 드라이버 Download PDF

Info

Publication number
KR20170005102A
KR20170005102A KR1020167034948A KR20167034948A KR20170005102A KR 20170005102 A KR20170005102 A KR 20170005102A KR 1020167034948 A KR1020167034948 A KR 1020167034948A KR 20167034948 A KR20167034948 A KR 20167034948A KR 20170005102 A KR20170005102 A KR 20170005102A
Authority
KR
South Korea
Prior art keywords
wires
wire
current flow
voltage sources
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020167034948A
Other languages
English (en)
Korean (ko)
Inventor
쇼이치로 센고쿠
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20170005102A publication Critical patent/KR20170005102A/ko
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0278—Arrangements for impedance matching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/20—Arrangements affording multiple use of the transmission path using different combinations of lines, e.g. phantom working

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)
KR1020167034948A 2014-05-15 2015-05-11 N-계승 전압 모드 드라이버 Withdrawn KR20170005102A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/278,682 2014-05-15
US14/278,682 US9710412B2 (en) 2014-05-15 2014-05-15 N-factorial voltage mode driver
PCT/US2015/030227 WO2015175439A1 (en) 2014-05-15 2015-05-11 N-factorial voltage mode driver

Publications (1)

Publication Number Publication Date
KR20170005102A true KR20170005102A (ko) 2017-01-11

Family

ID=53277048

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020167034948A Withdrawn KR20170005102A (ko) 2014-05-15 2015-05-11 N-계승 전압 모드 드라이버

Country Status (6)

Country Link
US (1) US9710412B2 (https=)
EP (1) EP3143740A1 (https=)
JP (1) JP2017519418A (https=)
KR (1) KR20170005102A (https=)
CN (1) CN106462527B (https=)
WO (1) WO2015175439A1 (https=)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9288089B2 (en) 2010-04-30 2016-03-15 Ecole Polytechnique Federale De Lausanne (Epfl) Orthogonal differential vector signaling
US9251873B1 (en) 2010-05-20 2016-02-02 Kandou Labs, S.A. Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communications
CN110166217B (zh) 2013-04-16 2022-05-17 康杜实验室公司 高带宽通信接口方法和系统
JP6317474B2 (ja) 2014-02-02 2018-04-25 カンドウ ラボズ ソシエテ アノニム 制約ｉｓｉ比を用いる低電力チップ間通信の方法および装置
EP3672176B1 (en) 2014-02-28 2022-05-11 Kandou Labs, S.A. Clock-embedded vector signaling codes
US9509437B2 (en) 2014-05-13 2016-11-29 Kandou Labs, S.A. Vector signaling code with improved noise margin
US11240076B2 (en) 2014-05-13 2022-02-01 Kandou Labs, S.A. Vector signaling code with improved noise margin
US9112550B1 (en) 2014-06-25 2015-08-18 Kandou Labs, SA Multilevel driver for high speed chip-to-chip communications
CN106797352B (zh) 2014-07-10 2020-04-07 康杜实验室公司 高信噪特性向量信令码
US9432082B2 (en) 2014-07-17 2016-08-30 Kandou Labs, S.A. Bus reversable orthogonal differential vector signaling codes
US9461862B2 (en) 2014-08-01 2016-10-04 Kandou Labs, S.A. Orthogonal differential vector signaling codes with embedded clock
EP3314835B1 (en) 2015-06-26 2020-04-08 Kandou Labs S.A. High speed communications system
US10055372B2 (en) 2015-11-25 2018-08-21 Kandou Labs, S.A. Orthogonal differential vector signaling codes with embedded clock
CN109417521B (zh) * 2016-04-28 2022-03-18 康杜实验室公司 低功率多电平驱动器
EP3610576B1 (en) 2017-04-14 2022-12-28 Kandou Labs, S.A. Pipelined forward error correction for vector signaling code channel
CN110945830B (zh) 2017-05-22 2022-09-09 康杜实验室公司 多模式数据驱动型时钟恢复电路
US10116468B1 (en) 2017-06-28 2018-10-30 Kandou Labs, S.A. Low power chip-to-chip bidirectional communications
US10693587B2 (en) 2017-07-10 2020-06-23 Kandou Labs, S.A. Multi-wire permuted forward error correction
KR102349415B1 (ko) * 2017-08-07 2022-01-11 삼성전자주식회사 펄스 진폭 변조 송신기 및 펄스 진폭 변조 수신기
US10496583B2 (en) 2017-09-07 2019-12-03 Kandou Labs, S.A. Low power multilevel driver for generating wire signals according to summations of a plurality of weighted analog signal components having wire-specific sub-channel weights
US10467177B2 (en) 2017-12-08 2019-11-05 Kandou Labs, S.A. High speed memory interface
CN116614338B (zh) 2017-12-28 2026-04-21 康杜实验室公司 同步切换多输入解调比较器的方法和装置
US10554450B2 (en) * 2018-03-14 2020-02-04 Samsung Display Co., Ltd. High resolution voltage-mode driver
US11831472B1 (en) 2022-08-30 2023-11-28 Kandou Labs SA Pre-scaler for orthogonal differential vector signalling
US12063034B2 (en) 2022-08-30 2024-08-13 Kandou Labs SA Line driver impedance calibration for multi-wire data bus

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3360861B2 (ja) * 1993-03-02 2003-01-07 株式会社ソニー木原研究所 シリアルディジタルデータの伝送方法及び伝送装置
US6005895A (en) * 1996-12-20 1999-12-21 Rambus Inc. Apparatus and method for multilevel signaling
US6556628B1 (en) * 1999-04-29 2003-04-29 The University Of North Carolina At Chapel Hill Methods and systems for transmitting and receiving differential signals over a plurality of conductors
US6452420B1 (en) * 2001-05-24 2002-09-17 National Semiconductor Corporation Multi-dimensional differential signaling (MDDS)
US7167527B1 (en) * 2002-05-02 2007-01-23 Integrated Memory Logic, Inc. System and method for multi-symbol interfacing
US7358869B1 (en) 2003-08-20 2008-04-15 University Of Pittsburgh Power efficient, high bandwidth communication using multi-signal-differential channels
JP2005086662A (ja) * 2003-09-10 2005-03-31 Seiko Epson Corp 半導体装置
US7227382B1 (en) 2005-02-01 2007-06-05 Advanced Micro Devices, Inc. Transmit based equalization using a voltage mode driver
US7567616B2 (en) * 2005-02-17 2009-07-28 Realtek Semiconductor Corp. Feedback equalizer for a communications receiver
US8222917B2 (en) * 2005-11-03 2012-07-17 Agate Logic, Inc. Impedance matching and trimming apparatuses and methods using programmable resistance devices
US7746937B2 (en) * 2006-04-14 2010-06-29 Formfactor, Inc. Efficient wired interface for differential signals
US7983347B2 (en) * 2006-04-27 2011-07-19 Panasonic Corporation Multiple differential transmission system including signal transmitter and signal receiver connected via three signal lines
WO2008151251A1 (en) * 2007-06-05 2008-12-11 Rambus, Inc. Techniques for multi-wire encoding with an embedded clock
EP2208327A4 (en) * 2007-10-01 2012-01-04 Rambus Inc SIMPLIFIED RECEIVER FOR USE IN MULTI-WIRE COMMUNICATION
US8848810B2 (en) * 2008-03-05 2014-09-30 Qualcomm Incorporated Multiple transmitter system and method
US7710144B2 (en) * 2008-07-01 2010-05-04 International Business Machines Corporation Controlling for variable impedance and voltage in a memory system
WO2010111619A2 (en) 2009-03-27 2010-09-30 Rambus, Inc. Voltage mode transmitter equalizer
US20110133773A1 (en) 2009-12-04 2011-06-09 Uniram Technology Inc. High Performance Output Drivers and Anti-Reflection Circuits
ES2909145T3 (es) 2010-02-02 2022-05-05 Nokia Technologies Oy Generación de señales diferenciales
US8208578B2 (en) * 2010-06-21 2012-06-26 North Carolina State University Systems, methods, and computer readable media for fractional pre-emphasis of multi-mode interconnect
US9071220B2 (en) 2013-03-07 2015-06-30 Qualcomm Incorporated Efficient N-factorial differential signaling termination network

Also Published As

Publication number Publication date
US20150331820A1 (en) 2015-11-19
US9710412B2 (en) 2017-07-18
EP3143740A1 (en) 2017-03-22
JP2017519418A (ja) 2017-07-13
CN106462527A (zh) 2017-02-22
WO2015175439A1 (en) 2015-11-19
CN106462527B (zh) 2019-08-02

Similar Documents

Publication Publication Date Title
KR20170005102A (ko) N-계승 전압 모드 드라이버
EP3167579B1 (en) Data link power reduction technique using bipolar pulse amplitude modulation
KR102349415B1 (ko) 펄스 진폭 변조 송신기 및 펄스 진폭 변조 수신기
EP3826248B1 (en) N-phase polarity output pin mode multiplexer
US9048824B2 (en) Programmable equalization with compensated impedance
US12028191B2 (en) Multi pulse amplitude modulation signaling decision feedback equalizer having power differentiating modes and tap-weight re-configuration
US9961174B2 (en) Analog behavior modeling for 3-phase signaling
US9590610B2 (en) Driver circuit for signal transmission and control method of driver circuit
US9590595B2 (en) Driver circuit with feed-forward equalizer
US20130076404A1 (en) Low voltage differential signal driving circuit and electronic device compatible with wired transmission
CN107070826B (zh) 数据发射装置、数据接收装置、数据发射和接收系统
US20080218292A1 (en) Low voltage data transmitting circuit and associated methods
WO2015146510A1 (ja) 送信装置および通信システム
US20100079172A1 (en) Differential output circuit
CN202168062U (zh) 片上终端电阻和校准环路
EP3831023B1 (en) Low power physical layer driver topologies
CN203445862U (zh) 推挽式源极串联端接发射机设备和系统
JP5085382B2 (ja) 伝送装置及び二重伝送方式
JP2013009157A (ja) 情報処理装置および情報処理装置の制御方法

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20161213

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination