KR20160110788A - Method and circuit for qc-ldpc codes in nand flash memory - Google Patents

Method and circuit for qc-ldpc codes in nand flash memory Download PDF

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KR20160110788A
KR20160110788A KR1020150034564A KR20150034564A KR20160110788A KR 20160110788 A KR20160110788 A KR 20160110788A KR 1020150034564 A KR1020150034564 A KR 1020150034564A KR 20150034564 A KR20150034564 A KR 20150034564A KR 20160110788 A KR20160110788 A KR 20160110788A
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redundancy
parity
input
decoding
flash memory
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KR1020150034564A
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Korean (ko)
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KR101775969B1 (en
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이현빈
강태근
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한밭대학교 산학협력단
한밭대학교 산학협력단
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/16—Flash programming of all the cells in an array, sector or block simultaneously

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

The present invention relates to a method and a circuit for creating a quasi-cyclic low-density parity-check (QC-LDPC) code in a NAND flash memory. The method for creating a QC-LDPC code in a NAND flash memory comprises: a step of initializing internal information and external information in response to a range of a parity-check matrix depending on a redundancy extension step; a step of refreshing the external information; a step of determining each bit of a code word; and a step of determining whether to extending a decoding step depending on a parity-check result of a code word, thereby the present invention can raise an error correction rate by increasing a size of redundancy, and extend a lifetime of a NAND flash memory by raising the error correction rate.

Description

METHOD AND CIRCUIT FOR QC-LDPC CODES IN NAND FLASH MEMORY FIELD OF THE INVENTION [0001]

The present invention relates to a QC-LDPC (Quasi-Cyclic-Low Density Parity Check) code generation method, and more particularly, to a QC-LDPC code generation method and circuit for a NAND flash memory that increases a redundancy size and increases an error correction rate .

Various digital devices are equipped with a storage device for storing data. The storage device is based on a NAND flash memory.

However, NAND flash memory has a limited number of write / erase operations. According to a method of storing data in a cell, a cell is classified into a single level cell (SLC), a multi level cell (MLC), and a triple level cell (TLC) . Due to the technique of storing a plurality of bit information in one cell, the number of write / erase operations is gradually decreasing.

However, as the number of write / erase operations increases, the bit error rate that can occur in the NAND flash memory gradually increases. In particular, when a plurality of bit information (2 bits, 3 bits) is stored in one cell, . An error correction code (ECC) is applied to a storage device based on a NAND flash memory. It is necessary to increase the error correction rate of the error correction code in order to cope with an increasing error rate depending on the use period.

Korean Registered Patent No. 10-1307733 (Notification date 2013.09.11.) Korean Patent Publication No. 10-2013-0135746 (published on December 11, 2013).

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a redundancy extended QC-LDPC code decoder for a NAND flash memory that expands the size of redundancy used for decoding in decoding failure, And to provide a QC-LDPC code generation method and circuit of a NAND flash memory capable of increasing a correction rate.

According to another aspect of the present invention, there is provided a method of generating a QC-LDPC code of a NAND flash memory, comprising: (a) initializing internal information and external information corresponding to a range of a parity- (b) updating the external information; (c) determining each bit of the codeword; And (d) determining whether to extend the decoding step according to a parity-check result of the codeword.

The step (b) performs a check node update and a compliant node update corresponding to the parity-check matrix. At this time, the check node update is updated through a min-sum algorithm.

Wherein if the decoding fails in the step (d) and the number of decoding iterations has not reached the maximum, the process proceeds to the step (b), the decoding fails in the step (d) If the maximum expansion step has not been reached, the redundancy used for the decoding is extended, and then the process proceeds to step (a).

Therefore, the parity check matrix can be configured to have a portion corresponding to the redundancy in a diagonal form, thereby maintaining the existing parity-check row when redundancy is expanded.

Meanwhile, in the QC-LDPC code generation circuit of the NAND flash memory of the present invention, XOR is successively connected so that the corresponding output becomes the XOR input of the next stage, and m 1 , m 2 , m 3 ,. , M i - and (message bits or the parity is code for generating a respective redundancy bit decoded code word bits for checking), and a bit corresponding to the redundancy is respectively input, the XOR that the m 1 inputs m 0 The output of the XOR to which the bit corresponding to the redundancy is input is input to the multiplexer and the output of the XOR to which the m i is input is input to the multiplexer.

As described above, according to the QC-LDPC code generation method and circuit of the NAND flash memory according to the present invention, the error correction rate can be increased by extending the redundancy, and the life of the NAND flash memory can be improved Can be extended.

1 is a diagram illustrating a configuration of a redundancy extended QC-LDPC code parity-check matrix according to an embodiment of the present invention.
2 is a conceptual diagram illustrating a process of obtaining a code matrix from a parity-check matrix according to an embodiment of the present invention.
3 is a flowchart illustrating a redundancy extended QC-LDPC code decoding algorithm according to an embodiment of the present invention.
4 is a QC-LDPC code generation circuit shared by an encoder and a decoder according to an embodiment of the present invention.

Hereinafter, a QC-LDPC code generation method and a circuit of a NAND flash memory according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating a configuration of a redundancy extended QC-LDPC code parity-check matrix according to an embodiment of the present invention. FIG. 2 illustrates a process of obtaining a code matrix from a parity-check matrix according to an embodiment of the present invention. Fig.

Referring to FIGS. 1 and 2, the present invention provides a QC-LDPC code generation method and circuit that can be expanded step by step according to an increase in errors of a NAND flash memory. of NAND Flash Memory and Circuit). Redundancy Enhancement In QC-LDPC code, the size of the message indicating the actual data is fixed, and the error correction rate is increased by increasing the redundancy used for decoding in the case of decoding failure due to an increase in error rate. With the expansion of redundancy, the memory and data computation used for decoding increases by an increased extent of the parity-check matrix applied to decoding. Since the error rate is not high at the beginning of the life time of the NAND flash memory, the error is corrected by maintaining the maximum performance through the short redundancy, and the redundancy length is gradually increased as the error rate increases. The size of the parity-check matrix applied to the decoding by the extended redundancy size is as follows.

expansion

Figure pat00001
Number of rows in step =
Figure pat00002
--- Equation 1

expansion

Figure pat00003
Number of columns in step =
Figure pat00004
--- Equation 2

(

Figure pat00005
The length of the message,
Figure pat00006
: Length of the redundancy of the first step,
Figure pat00007
: The size of one block)

The part corresponding to the redundancy in the parity-check matrix of FIG. 1 is configured as a diagonal type. In this form, in the process of obtaining the code matrix from the parity-check matrix (decoding matrix) of FIG. 2

Figure pat00008
. The code matrix can be obtained by making the portion corresponding to the redundancy to be a unit matrix form by gauss-elimination of the parity-check matrix, and by inverting the rest of the unit except for the unit matrix portion. This means that the configuration of the entire code matrix can be changed when each parity check of the parity-check matrix is changed. That is, the sign matrix is dependent on the parity-check matrix.

Therefore, when the existing parity-check row changes in the redundancy extension, the existing redundancy pattern is also changed. Therefore, a code circuit for generating redundancy of different patterns as many as the number of decoding steps is required. (Codeword) must be stored in memory. In order to solve this problem, in the QC-LDPC code structure of the present invention, by configuring a portion corresponding to redundancy in the parity-check matrix as a diagonal type, it is possible to prevent a change in the existing parity- Prevent change.

3 is a flowchart illustrating a redundancy extended QC-LDPC code decoding algorithm according to an embodiment of the present invention.

The decoding order of the redundancy extended QC-LDPC code decoder is as follows.

First, the terms used in FIG. 3 are summarized as follows.

CHK Parity-check result (1: failure, 0: success) ITR Current iteration count ITR_MAX Maximum number of iterations LEV Current number of decodes LEV_MAX Maximum number of decodes

S1: Initialization

- initialize internal information and external information for decoding by the extent of the parity-check matrix according to the redundancy extension step.

S2: Check-Node Updating (CN Updating)

- update the external information through the min-sum algorithm by the extent of the parity-check matrix according to the redundancy extension step.

S3: Variable-Node Updaing (VN Updating)

- Updating the extrinsic information for next decoding by the extent of the parity-check matrix according to the redundancy extension step and determining each bit of the code word.

S4: Parity Check

- Parity of the decoded codeword - It is divided into the following four cases according to the check result.

a. If decryption is successful: Decode completion after declaring read success

b. If decoding fails and the number of decoding iterations has not reached the maximum: Repeat from 2

c. If the decoding fails and the number of decoding iterations reaches the maximum but the expansion step does not reach the maximum:

d. If the decoding fails and the number of decoding iterations and the expansion step reaches the maximum:

4 is a QC-LDPC code generation circuit shared by an encoder and a decoder according to an embodiment of the present invention.

Referring to FIG. 4, a parity-check matrix may be constructed as shown in FIG. 1 to share a circuit for generating redundancy bits in an encoder and a circuit for performing an overall parity-check (syndrome calculation) in a decoder . As shown in FIG. 4, the hardware configuration is such that the output is connected to an XOR input so as to be the next stage XOR input, and each XOR has m 1 , m 2 , m 3 , ... , m i and redundancy are input, m 0 is inputted to XOR where m 1 is input, the output of XOR where redundancy corresponding bits are input is input to the multiplexer, and X i Is input to the multiplexer.

In Fig. 4, m 0 , m 1 , m 2 , m 3 , ... , the input corresponding to m i will be the message bits to be coded to produce each redundancy bit or the decoded codeword bits for parity-check. The input corresponding to r becomes the bit corresponding to redundancy in the decoded codeword. When the s signal is '1', the parity check result is output including the r signal. When the signal is '0', the redundancy bits generated in the coding process are not output because the r signal is not included.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention.

Claims (7)

(a) initializing internal information and external information corresponding to a range of a parity-check matrix according to a redundancy extension step;
(b) updating the external information;
(c) determining each bit of the codeword; And
(d) determining whether to extend the decoding step according to the parity-check result of the codeword.
The method according to claim 1,
The step (b)
And performing a check node update and a permissible node update in response to the parity-check matrix.
3. The method of claim 2,
Wherein the check node update is updated through a min-sum algorithm.
The method according to claim 1,
The QC-LDPC code generation method of the NAND flash memory proceeding to the step (b) if decoding fails in the step (d) and the number of decoding iterations has not reached the maximum.
The method according to claim 1,
If the number of decoding iterations reaches the maximum number of decoding times in the step (d) and the maximum expansion step has not been reached, the redundancy used for decoding is extended, and then the QC of the NAND flash memory proceeding to the step (a) -LDPC code generation method.
The method as claimed in any one of claims 1 to 5, wherein a part corresponding to the redundancy in the parity-check matrix is configured as a diagonal type so that QC-LDPC of a NAND flash memory maintaining an existing parity- How to generate code.
The corresponding output is connected to XOR so as to be the XOR input of the next stage,
Each XOR has m 1 , m 2 , m 3 , ... , m i and redundancy bits, respectively,
M 0 is input to the XOR where m 1 is input,
An output of the XOR to which the bit corresponding to the redundancy is input is input to the multiplexer,
And an output of the XOR to which the m i is input is input to the multiplexer.
(Where m is the message bits to be coded to generate each redundancy bit or the decoded codeword bits for parity-check).
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Publication number Priority date Publication date Assignee Title
CN108809330A (en) * 2018-05-07 2018-11-13 中山大学 A kind of LDPC code interpretation method for NAND-Flash storage mediums
CN111722956A (en) * 2019-03-19 2020-09-29 西部数据技术公司 LDPC code length adjustment
KR20210004897A (en) * 2019-07-05 2021-01-13 한양대학교 산학협력단 A method and apparatus for fast decoding a linear code based on bit matching

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KR102144732B1 (en) 2019-05-10 2020-08-14 한양대학교 산학협력단 A method and apparatus for fast decoding a linear code based on soft decision

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KR20130135746A (en) 2012-06-01 2013-12-11 한국전자통신연구원 Low density parity check code for terrestrial cloud trasmission

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US7543212B2 (en) 2004-09-13 2009-06-02 Idaho Research Foundation, Inc. Low-density parity-check (LDPC) encoder
CN101350625B (en) 2007-07-18 2011-08-31 北京泰美世纪科技有限公司 High-efficiency all-purpose decoder for QC-LDPC code and decoding method thereof

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
KR101307733B1 (en) 2012-03-02 2013-09-11 인하대학교 산학협력단 Apparatus and method for decoding block layered based non-binary qc-ldpc
KR20130135746A (en) 2012-06-01 2013-12-11 한국전자통신연구원 Low density parity check code for terrestrial cloud trasmission

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108809330A (en) * 2018-05-07 2018-11-13 中山大学 A kind of LDPC code interpretation method for NAND-Flash storage mediums
CN108809330B (en) * 2018-05-07 2020-09-22 中山大学 LDPC code decoding method for NAND-Flash storage medium
CN111722956A (en) * 2019-03-19 2020-09-29 西部数据技术公司 LDPC code length adjustment
CN111722956B (en) * 2019-03-19 2024-04-09 西部数据技术公司 LDPC code length adjustment
KR20210004897A (en) * 2019-07-05 2021-01-13 한양대학교 산학협력단 A method and apparatus for fast decoding a linear code based on bit matching

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