CN111782438B - Improved anti-radiation reinforced matrix code decoding circuit - Google Patents

Improved anti-radiation reinforced matrix code decoding circuit Download PDF

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CN111782438B
CN111782438B CN201910271188.6A CN201910271188A CN111782438B CN 111782438 B CN111782438 B CN 111782438B CN 201910271188 A CN201910271188 A CN 201910271188A CN 111782438 B CN111782438 B CN 111782438B
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bits
bit
check
information
syndrome
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CN111782438A (en
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施宇根
李少甫
周明长
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Southwest University of Science and Technology
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

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Abstract

An improved decoding circuit of radiation-resistant reinforced matrix code is designed to correct the error of the reversed bit of 6-bit data width of memory. The decoding circuit completes decoding error correction of the data bits through two iterations. The core of the decoding circuit is to obtain new check bits and syndromes for the received information bits and redundant bits, and to correct errors in the data by comparing the updated syndromes with the initial syndromes.

Description

Improved anti-radiation reinforced matrix code decoding circuit
Technical Field
The invention relates to a matrix code decoding circuit with improved radiation hardening resistance for a memory.
Background
Under the environment of space irradiation, the memory can be subjected to multi-bit upset by high-energy particles. The memory has a higher probability of soft errors with a data width of 2-5 bits, and has a very small probability of data bit flipping with more width. In general, the memory can also perform error correction by using BCH codes, RS codes, and codewords having a strong LDPC error correction capability. However, the high performance of the code word complicates the circuit implementation, not only the check matrix needs to be stored, but also the check matrix is prone to error in the radiation environment to cause decoding failure, and the decoding process has serious delay and hard hardware overhead.
A two-dimensional matrix code is constructed according to error characteristics in a radiation environment, one word is logically divided into a matrix form by the two-dimensional matrix code, error correction can be performed on memory inversion with specified data width, and the circuit structure of the memory does not need to be changed except for adding redundant circuits. The matrix code circuit is simple to realize, and can better reinforce the radiation resistance of the memory, but along with the reduction of the process size of the circuit, the memory needs an error correcting code with stronger error correcting capability.
The invention provides a matrix code construction method through retrieval of a DOI (direction of arrival) number 10.16708/j.cnki.1000-758X.2018.0070, and designs an improved decoding circuit, so that error correction can be carried out on the inversion of the 6-bit data width of a single code word after the inversion of the 6-bit data width is divided for multiple times.
The matrix code logically divides the word of the memory into a plurality of 4-order matrixes, and the check bit of the matrix code is generated as follows, wherein formula 3 and formula 4 jointly check the checked information bits, such as the information bits
Figure 526138DEST_PATH_IMAGE001
When flipped, the state of equation 3 should be denoted as '1110'.
Figure 309155DEST_PATH_IMAGE002
（1）
Figure 363699DEST_PATH_IMAGE003
（2）
Figure 59122DEST_PATH_IMAGE004
（3）
Figure 831906DEST_PATH_IMAGE005
（4）
Disclosure of Invention
The problem to be solved by the invention is to provide an improved decoding circuit for increasing the error correction performance of matrix codes.
In order to achieve the above purpose, the present invention provides the following implementation schemes:
step 1: data receiving information bits are based on generating 14 new parity bits
Figure 107030DEST_PATH_IMAGE006
Thereby obtaining a syndrome
Figure 32392DEST_PATH_IMAGE007
:
Figure 164296DEST_PATH_IMAGE008
（5）
Step 2: and correcting errors of partial information bits in the information matrix, wherein the error correction formula is as follows:
Figure 362059DEST_PATH_IMAGE009
（6）
Figure 237611DEST_PATH_IMAGE010
（7）
step 3, updating the corrected information bit to obtain a new check bit
Figure 266747DEST_PATH_IMAGE011
And syndrome
Figure 821750DEST_PATH_IMAGE012
And correcting error of part of the remaining information bits according to the new syndrome:
Figure 506809DEST_PATH_IMAGE013
（8）
Figure 920473DEST_PATH_IMAGE014
（9）
Figure 69694DEST_PATH_IMAGE015
（10）
and 4, step 4: updating the correction result of the information bit in the step 3, and generating a new check bit after updating
Figure 746663DEST_PATH_IMAGE016
And thus obtain a new syndrome
Figure 715756DEST_PATH_IMAGE017
。
Figure 949423DEST_PATH_IMAGE018
（11）
And 5: check state of remaining information bits
Figure 687571DEST_PATH_IMAGE019
Can be based on the updated syndrome
Figure 535442DEST_PATH_IMAGE020
And obtaining 3 regions of information bits which can be corrected through the verification state:
Figure 991831DEST_PATH_IMAGE021
（12）
wherein
Figure 12877DEST_PATH_IMAGE022
Representing information bits
Figure 120379DEST_PATH_IMAGE023
An or operation of all cases of the check state is possible according to equations 3 and 4 within a specified data width. And completing error correction of the residual information bits, and completing decoding by an error correction algorithm.
The invention has the following excellent effects: the invention provides an improved matrix code decoding circuit, which divides a turnover bit through multiple iterations for continuous errors generated by an information bit; each iteration updating reduces the error digit of the check bit; therefore, the decoding performance of the error correcting code is improved while not increasing too much power consumption and time delay overhead.
Drawings
For a better understanding of the objects, details and advantages of the invention, reference is made to the accompanying drawings, in which:
FIG. 1 is a decoding flow diagram;
FIG. 2 is a logical matrix arrangement of 16bit wide words
FIG. 3 is a block diagram of a logical matrix divided into 3 parts when encoding a codeword;
FIGS. 4-19 illustrate various information bit error correction circuits for words of 16bit width.
Detailed Description
Referring to the logical arrangement structure of code words in fig. 2, the present invention uses a 16-bit wide word as a preferred embodiment, and comprises the following specific steps:
step 1: data receiving information bits are based on generating 14 new parity bits
Figure 873571DEST_PATH_IMAGE006
Thereby obtaining a syndrome
Figure 817256DEST_PATH_IMAGE007
:
Figure 641993DEST_PATH_IMAGE024
（13）
Step 2: referring to each partition position in fig. 3, error correction is first performed on partial information bits of the 1-partition and the 2-partition in the information matrix, and the error correction formula is as follows:
Figure 354734DEST_PATH_IMAGE025
（6）
Figure 544407DEST_PATH_IMAGE026
（7）
step 3, updating the corrected sum to obtain a new check bit
Figure 726121DEST_PATH_IMAGE011
And syndrome
Figure 823390DEST_PATH_IMAGE012
The remaining information bits of zone 1 and zone 2 in fig. 3 are error corrected according to the new syndrome:
Figure 656216DEST_PATH_IMAGE027
（8）
Figure 813528DEST_PATH_IMAGE028
（9）
Figure 669489DEST_PATH_IMAGE029
（10）
and 4, step 4: updating the 3-zone check bit according to the correction result of the information bit in the step 3, and generating a new check bit after updating
Figure 810927DEST_PATH_IMAGE016
And thereby obtaining a new syndrome
Figure 763840DEST_PATH_IMAGE017
。
Figure 92053DEST_PATH_IMAGE030
（11）
And 5: check state of remaining information bits
Figure 435309DEST_PATH_IMAGE019
Can be based on the updated syndrome
Figure 139960DEST_PATH_IMAGE020
And obtaining 3 regions of information bits which can be corrected through the verification state:
Figure 432532DEST_PATH_IMAGE031
（12）
wherein
Figure 134909DEST_PATH_IMAGE022
Representing information bits
Figure 762200DEST_PATH_IMAGE023
An or operation of all cases of the check state is possible according to equations 3 and 4 within the 6-bit data width. And completing error correction of the residual information bits, and completing decoding by an error correction algorithm.
The corresponding circuit for each information bit is shown in FIGS. 4-19.
The above detailed description of the embodiments is intended to be illustrative only and is not intended to be limiting, as various changes in form and detail can be made therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims (2)

1. An improved radiation-resistant reinforced matrix code decoding circuit is designed to correct the error of the reversed bit of the data width of 6 bits in a memory, and the decoding circuit completes the decoding and error correction of the data bits through two iterations; the core of the decoding circuit is that new check bits and syndromes are obtained from received information bits and redundant bits, and data are corrected through comparison between the updated syndromes and the initial syndromes;
the coding mode of the designed decoding circuit is that a code word is logically divided into n 4-order matrixes, 16 information bits in the matrixes are sequentially arranged, and 14 check bits are obtained from the 16 information bits; the sign bit is defined as:
Figure 234759DEST_PATH_IMAGE001
is an initial information bit;
Figure 776599DEST_PATH_IMAGE002
is an initial check bit;
Figure 478976DEST_PATH_IMAGE003
a check bit generated for receiving the information bit;
Figure 106266DEST_PATH_IMAGE004
calculating a syndrome for the received information bits and the initial check bits;
Figure 863876DEST_PATH_IMAGE005
the check bits are obtained after the first iteration of part of the information bits;
Figure 525801DEST_PATH_IMAGE006
obtaining a new syndrome for the check bit and the initial information bit after the first iteration;
Figure 399079DEST_PATH_IMAGE007
the check bits are obtained after the second iteration of the partial information bits;
Figure 248087DEST_PATH_IMAGE006
obtaining a syndrome for the check bit after the second iteration and the initial information bit;
Figure 294540DEST_PATH_IMAGE008
is the modified information bit;
step 1: data receiving information bits are based on generating 14 new parity bits
Figure 827284DEST_PATH_IMAGE003
Thereby obtaining a syndrome
Figure 871463DEST_PATH_IMAGE004
:
Figure 207766DEST_PATH_IMAGE009
（13）
Step 2: and correcting errors of partial information in the information matrix, wherein the error correction formula is as follows:
Figure 792331DEST_PATH_IMAGE010
（6）
Figure 163270DEST_PATH_IMAGE011
（7）
step 3, updating the corrected information bits to obtain new check bits
Figure 439004DEST_PATH_IMAGE005
And syndrome
Figure 528183DEST_PATH_IMAGE012
And correcting error of part of the remaining information bits according to the new syndrome:
Figure 916439DEST_PATH_IMAGE013
（8）
Figure 407463DEST_PATH_IMAGE014
（9）
Figure 793445DEST_PATH_IMAGE015
（10）
and 4, step 4: updating the correction result of the information bit in the step 3, and generating a new check bit after updating
Figure 855073DEST_PATH_IMAGE016
And thus obtain a new syndrome
Figure 47020DEST_PATH_IMAGE017
；
Figure 392551DEST_PATH_IMAGE018
（11）
And 5: check state of remaining information bits
Figure 949434DEST_PATH_IMAGE019
Can be based on the updated syndrome
Figure 747626DEST_PATH_IMAGE020
And obtaining, the residual information bits can be corrected through the check state:
Figure 992531DEST_PATH_IMAGE021
（12）
wherein
Figure 192568DEST_PATH_IMAGE022
Representing information bits
Figure 920353DEST_PATH_IMAGE023
An or operation of all cases of the check state may be obtained according to equations 3 and 4 within the 6-bit data width; and completing error correction of the residual information bits, and completing decoding by an error correction algorithm.
2. The improved radioresistant reinforced matrix code decoding circuit of claim 1 wherein: the circuit divides the reversed bit through multiple iterations for continuous errors of the information bit, and the error bit of the check bit is reduced through each iteration updating.
CN201910271188.6A 2019-04-04 2019-04-04 Improved anti-radiation reinforced matrix code decoding circuit Expired - Fee Related CN111782438B (en)

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