CN111782438A - Improved anti-radiation reinforced matrix code decoding circuit - Google Patents

Improved anti-radiation reinforced matrix code decoding circuit Download PDF

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Publication number
CN111782438A
CN111782438A CN201910271188.6A CN201910271188A CN111782438A CN 111782438 A CN111782438 A CN 111782438A CN 201910271188 A CN201910271188 A CN 201910271188A CN 111782438 A CN111782438 A CN 111782438A
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Prior art keywords
bit
bits
information
check
syndrome
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CN111782438B (en
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施宇根
李少甫
周明长
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Southwest University of Science and Technology
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Southwest University of Science and Technology
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

Abstract

The invention relates to an improved matrix error correction code decoding circuit, which designs a matrix error correction code decoding circuit with a reinforced radiation resistance of a memory, and the designed decoding circuit can correct the error of the reversed bit of the 6-bit data width of the memory. The decoding circuit completes decoding error correction of the data bits through two iterations. The core of the decoding circuit is to obtain new check bits and syndromes for the received information bits and redundant bits, and to correct errors in the data by comparing the updated syndromes with the initial syndromes.

Description

Improved anti-radiation reinforced matrix code decoding circuit
Technical Field
The invention relates to a matrix code decoding circuit with improved radiation hardening resistance for a memory.
Background
Under the environment of space irradiation, the memory can be subjected to multi-bit upset by high-energy particles. The memory has a higher probability of soft errors with a data width of 2-5 bits, and has a very small probability of data bit flipping with more width. In general, the memory can also perform error correction by using BCH codes, RS codes, and codewords having a strong LDPC error correction capability. However, the high performance of the code word complicates the circuit implementation, not only the check matrix needs to be stored, but also the check matrix is prone to error in the radiation environment to cause decoding failure, and the decoding process has serious delay and hard hardware overhead.
A two-dimensional matrix code is constructed according to error characteristics in a radiation environment, one word is logically divided into a matrix form by the two-dimensional matrix code, error correction can be performed on memory inversion with specified data width, and the circuit structure of the memory does not need to be changed except for adding redundant circuits. The matrix code circuit is simple to realize, and can better reinforce the radiation resistance of the memory, but along with the reduction of the process size of the circuit, the memory needs an error correcting code with stronger error correcting capability.
The invention provides a matrix code construction method through retrieval of a DOI (direction of arrival) number 10.16708/j.cnki.1000-758X.2018.0070, and designs an improved decoding circuit, so that error correction can be carried out on the inversion of the 6-bit data width of a single code word after the inversion of the 6-bit data width is divided for multiple times.
The matrix code logically divides the word of the memory into a plurality of 4-order matrixes, and the check bit of the matrix code is generated as follows, wherein formula 3 and formula 4 jointly check the checked information bits, such as the information bits
Figure RE-460590DEST_PATH_IMAGE001
When flipped, the state of equation 3 should be denoted as '1110'.
Figure RE-285326DEST_PATH_IMAGE002
（1）
Figure RE-466909DEST_PATH_IMAGE003
（2）
Figure RE-922161DEST_PATH_IMAGE004
（3）
Figure RE-884301DEST_PATH_IMAGE005
（4）
Disclosure of Invention
The problem to be solved by the invention is to provide an improved decoding circuit for increasing the error correction performance of matrix codes.
In order to achieve the above purpose, the present invention provides the following implementation schemes:
step 1: data receiving information bits are based on generating 14 new parity bits
Figure RE-450411DEST_PATH_IMAGE006
Thereby obtaining a syndrome
Figure RE-548817DEST_PATH_IMAGE007
:
Figure RE-174971DEST_PATH_IMAGE008
（5）
Step 2: and correcting errors of partial information bits in the information matrix, wherein the error correction formula is as follows:
Figure RE-624407DEST_PATH_IMAGE009
（6）
Figure RE-728629DEST_PATH_IMAGE010
（7）
step 3, updating the corrected information bit to obtain a new check bit
Figure RE-947121DEST_PATH_IMAGE011
And syndrome
Figure RE-744175DEST_PATH_IMAGE012
And correcting error of part of the remaining information bits according to the new syndrome:
Figure RE-429977DEST_PATH_IMAGE013
（8）
Figure RE-603469DEST_PATH_IMAGE014
（9）
Figure RE-676467DEST_PATH_IMAGE015
（10）
and 4, step 4: updating the correction result of the information bit in the step 3, and generating after updatingNovel check bitAnd thus obtain a new syndrome
Figure RE-740555DEST_PATH_IMAGE017
。
Figure RE-248897DEST_PATH_IMAGE018
（11）
And 5: check state of remaining information bits
Figure RE-379664DEST_PATH_IMAGE019
Can be based on the updated syndrome
Figure RE-580838DEST_PATH_IMAGE020
And obtaining 3 regions of information bits which can be corrected through the verification state:
Figure RE-164266DEST_PATH_IMAGE021
（12）
wherein
Figure RE-476299DEST_PATH_IMAGE022
Representing information bits
Figure RE-461572DEST_PATH_IMAGE023
An or operation of all cases of the check state is possible according to equations 3 and 4 within a specified data width. And completing error correction of the residual information bits, and completing decoding by an error correction algorithm.
The invention has the following excellent effects: the invention provides an improved matrix code decoding circuit, which divides a turnover bit through multiple iterations for continuous errors generated by an information bit; each iteration updating reduces the error digit of the check bit; therefore, the decoding performance of the error correcting code is improved while not increasing too much power consumption and time delay overhead.
Drawings
For a better understanding of the objects, details and advantages of the invention, reference is made to the accompanying drawings, in which:
FIG. 1 is a decoding flow diagram;
FIG. 2 is a logical matrix arrangement of 16bit wide words
FIG. 3 is a block diagram of a logical matrix divided into 3 parts when encoding a codeword;
FIGS. 4-19 illustrate various information bit error correction circuits for words of 16bit width.
Referring to the logical arrangement structure of code words in fig. 2, the present invention uses a 16-bit wide word as a preferred embodiment, and comprises the following specific steps:
step 1: data receiving information bits are based on generating 14 new parity bits
Figure RE-833648DEST_PATH_IMAGE006
Thereby obtaining a syndrome
Figure RE-904372DEST_PATH_IMAGE007
:
Figure RE-20096DEST_PATH_IMAGE024
（13）
Step 2: referring to each partition position in fig. 3, first, error correction is performed on partial information bits of the 1-partition and the 2-partition in the information matrix, the error correction formula is as follows 14 and 15, and the corrected corresponding information bits
Figure RE-859876DEST_PATH_IMAGE025
Reference is made to fig. 4 to 7.
Figure RE-402852DEST_PATH_IMAGE026
（14）
Figure RE-760540DEST_PATH_IMAGE027
（15）
Step 3, for corrected
Figure RE-617638DEST_PATH_IMAGE028
And
Figure RE-374241DEST_PATH_IMAGE029
updating to obtain new check bit
Figure RE-25802DEST_PATH_IMAGE011
And syndrome
Figure RE-133436DEST_PATH_IMAGE012
Error correction is performed on the remaining information bits of the regions 1 and 2 in fig. 3 based on the new syndrome, and the corresponding information bits corrected according to equations 16 to 18
Figure RE-528645DEST_PATH_IMAGE025
Referring to fig. 8 to 11, wherein the circuit diagram receives the information bits updated in step 2 for error correction.
Figure RE-139755DEST_PATH_IMAGE030
（16）
Figure RE-227796DEST_PATH_IMAGE031
（17）
Figure RE-494830DEST_PATH_IMAGE032
（18）
And 4, step 4: updating the 3-zone check bit according to the correction result of the information bit in the step 3, and generating a new check bit after updating
Figure RE-490468DEST_PATH_IMAGE016
And thus obtain a new syndrome
Figure RE-159346DEST_PATH_IMAGE017
。
Figure RE-480606DEST_PATH_IMAGE033
（19）
And 5: check state of remaining information bits
Figure RE-969356DEST_PATH_IMAGE019
Can be based on the updated syndrome
Figure RE-34264DEST_PATH_IMAGE020
And obtaining 3 regions of information bits which can be corrected through the verification state:
Figure RE-557650DEST_PATH_IMAGE034
（20）
wherein
Figure RE-784232DEST_PATH_IMAGE022
Representing information bits
Figure RE-25857DEST_PATH_IMAGE035
An or operation of all cases of the check state is possible according to equations 3 and 4 within the 6-bit data width.
Corresponding check state pair information bits of the syndrome obtained according to equation 3 after iteration
Figure RE-631806DEST_PATH_IMAGE036
Circuit for correction referring to fig. 12 to 15, the corresponding check state of the syndrome obtained according to equation 4 after iteration is applied to the information bits
Figure RE-9698DEST_PATH_IMAGE036
Circuits for performing correction referring to fig. 16 to 19, wherein each circuit receives the information bits updated in step 2 to step 4 to perform error correction on the remaining information bits, and the error correction algorithm completes decoding.
The corresponding circuit for each information bit is shown in FIGS. 4-19.
The above detailed description of the embodiments is intended to be illustrative only and is not intended to be limiting, as various changes in form and detail can be made therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims (3)

1. The invention designs a matrix code error correction code decoding circuit for radiation hardening resistance of a memory, and the designed decoding circuit can correct the error of the reversed bit of the 6-bit data width of the memory. The decoding circuit completes decoding error correction of the data bits through two iterations. The core of the decoding circuit is to obtain new check bits and syndromes for the received information bits and redundant bits, and to correct errors in the data by comparing the updated syndromes with the initial syndromes.
The coding mode of the designed decoding circuit is that a code word is logically divided into n 4-order matrixes, 16 information bits in the matrixes are sequentially arranged, and 14 check bits are obtained from the 16 information bits.
The sign bit is defined as:
Figure RE-DEST_PATH_IMAGE002
is an initial information bit;
Figure RE-DEST_PATH_IMAGE004
is an initial check bit;
Figure RE-DEST_PATH_IMAGE006
a check bit generated for receiving the information bit;
Figure RE-DEST_PATH_IMAGE008
calculating a syndrome for the received information bits and the initial check bits;
Figure RE-DEST_PATH_IMAGE010
the check bits are obtained after the first iteration of part of the information bits;
Figure RE-DEST_PATH_IMAGE012
obtaining a new syndrome for the check bit and the initial information bit after the first iteration;
Figure RE-DEST_PATH_IMAGE014
the check bits are obtained after the second iteration of the partial information bits;
Figure RE-DEST_PATH_IMAGE016
obtaining a syndrome for the check bit after the second iteration and the initial information bit;
Figure RE-DEST_PATH_IMAGE018
is the modified information bits.
2. According to the solution of claim 1, the inventive solution comprises the following steps:
1) data receiving information bit based on generation of new check bit
Figure RE-DEST_PATH_IMAGE006A
According to the new check bit
Figure RE-DEST_PATH_IMAGE006AA
And an initial parity bit
Figure RE-RE-DEST_PATH_IMAGE020
Obtaining the syndrome
Figure RE-DEST_PATH_IMAGE008A
；
2) According to the syndrome
Figure RE-DEST_PATH_IMAGE008AA
Correcting errors of partial information bits in the information matrix;
3) updating the corrected information bits by the updated information bitsInformation bit obtaining new check bit
Figure RE-DEST_PATH_IMAGE010A
And syndrome
Figure RE-DEST_PATH_IMAGE012A
After the first iteration updating is finished, error correction is carried out according to partial information bits in the uncorrected information bits of the new syndrome;
4) updating the check bit according to the correction result of the information bit in the step 3), performing second iteration, and generating a new check bit after iterative update
Figure RE-DEST_PATH_IMAGE022
And thus obtain a new syndrome
Figure RE-DEST_PATH_IMAGE024
。
5) Checking the state
Figure RE-DEST_PATH_IMAGE026
Can be based on the updated syndrome
Figure RE-DEST_PATH_IMAGE024A
And obtaining the residual information bits for error correction through the verification state.
3. The decoding step of claim 2, wherein: the circuit divides the turning bit by multiple iterations for continuous errors of the information bit; each iteration updating reduces the error digit of the check bit; therefore, the decoding performance is increased while not increasing too much power consumption and time delay overhead.
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Citations (6)

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Publication number Priority date Publication date Assignee Title
US20120144262A1 (en) * 2010-12-01 2012-06-07 Electronics And Telecommunications Research Institute Method of producing and decoding error correction code and apparatus therefor
US20140365843A1 (en) * 2013-06-07 2014-12-11 Alcatel-Lucent Usa Inc. Error correction for entangled quantum states
US20150169401A1 (en) * 2013-12-12 2015-06-18 Phison Electronics Corp. Decoding method, memory storage device, and memory controlling circuit unit
US20150278008A1 (en) * 2014-03-25 2015-10-01 Texas Instruments Incorporated Crc-based forward error correction circuitry and method
US20150358036A1 (en) * 2014-06-10 2015-12-10 Phison Electronics Corp. Decoding method, memory storage device and memory control circuit unit
CN106328209A (en) * 2015-06-30 2017-01-11 中国科学院电子学研究所 Storage single event multiple bit upset fault-tolerance method and circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120144262A1 (en) * 2010-12-01 2012-06-07 Electronics And Telecommunications Research Institute Method of producing and decoding error correction code and apparatus therefor
US20140365843A1 (en) * 2013-06-07 2014-12-11 Alcatel-Lucent Usa Inc. Error correction for entangled quantum states
US20150169401A1 (en) * 2013-12-12 2015-06-18 Phison Electronics Corp. Decoding method, memory storage device, and memory controlling circuit unit
US20150278008A1 (en) * 2014-03-25 2015-10-01 Texas Instruments Incorporated Crc-based forward error correction circuitry and method
US20150358036A1 (en) * 2014-06-10 2015-12-10 Phison Electronics Corp. Decoding method, memory storage device and memory control circuit unit
CN106328209A (en) * 2015-06-30 2017-01-11 中国科学院电子学研究所 Storage single event multiple bit upset fault-tolerance method and circuit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
施宇根: "存储器抗辐射加固的矩阵纠错码研究", 《中国空间科学技术》 *
施宇根: "存储器抗辐射加固的矩阵纠错码研究", 《中国空间科学技术》, vol. 39, no. 1, 19 November 2018 (2018-11-19), pages 67 - 72 *

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