KR101307733B1 - Apparatus and method for decoding block layered based non-binary qc-ldpc - Google Patents

Abstract

PURPOSE: An apparatus of encoding non-binary based QC-LDPC codes and a method thereof are provided to improve a whole transfer rate of a decoder. CONSTITUTION: A check node processing is performed by using a min-max algorithm which has a minimum value among maximum values of a check node operation unit. The check node operation unit comprises a min-max operation block which operates each row of a parity check matrix by one block layer. The check node operation unit performs a merge processing at the mini-max algorithm in two directions, classifies a merge operation as a left merging (L-merge) operation and a right merging (R-merge) operation and performs the L-merge operation and the R-merge operation. In a unit matrix forming the parity check matrix, elements positioned in a diagonal direction of the matrix comprise the elements of Galois-field and the rest elements of the matrix comprise 0. [Reference numerals] (AA,EE,JJ,NN) Switch network 2; (BB,FF,KK,OO) Smallest-largest calculation block; (CC) Backward metric; (DD) Backward memory bank; (GG) L-combination; (HH,PP) Shift register; (II) Forward metric; (LL) Forward memory bank; (MM) R-combination

Description

Decoding device and method thereof for non-binary PCC-LDPC code based on block layer {APPARATUS AND METHOD FOR DECODING BLOCK LAYERED BASED NON-BINARY QC-LDPC}

Embodiments of the present invention are a forward error correction (FEC) system that corrects an error occurring in data during a data transmission process at a transmitter in a digital communication system, and is based on a block layer based non-binary QC-LDPC (QC). -LDPC: relates to a decoding apparatus and method of a Quasi Cyclic Low-Density Parity Check) code.

Recently, with the increase of the transmission bandwidth in broadband networks and the emergence of new communication services, the Internet traffic continues to grow, and the wired and wireless communication systems are rapidly changing to enable high-speed data transmission.

In particular, the optical transmission system, which is the main communication network, is currently commercialized in the 100Gbps class, and is expected to develop in the direction of increasing the transmission rate to 1-Tbps within a decade. In addition, the development of a system for wireless transmission of high-volume applications such as VOD, HDTV, 3D-TV in high-speed wireless communication system is also in progress. The evolution of such communication systems has led to the need for high performance forward error correction circuits.

Non-Binary Quasi Cyclic Low-Density Parity Check (LDPC) code is an extension of the existing LDPC code, the first block code proposed by Davey and MacKay. In the non-binary LDPC code, elements other than '0' in the parity check matrix ( H ) are allocated as elements of Galois-Field. In a typical communication system, if the code length is short or higher-order modulation technique is applied, the non-binary LDPC code shows better error correction performance than the LDPC code.

Research into the application of non-binary LDPC codes has been carried out on various communication systems. First, it is reported to have a significantly superior error correction performance compared to the most widely used Reed-Solomon (RS) codes. In addition, non-binary LDPC codes show much better error correction performance than conventional LDPC codes when MIMO (Multiple Input Multiple Output) technology is applied in a wireless communication system.

Attempts have also been made to apply non-binary LDPC codes in optical communication systems. In particular, the importance of FEC performance is emerging in optical communication systems, and the method of improving optical signal to noise ratio (OSNR) performance on optical transmission lines is considered the most efficient solution by applying FEC with strong error correction performance. Because. For this reason, studies are being conducted to apply non-binary LDPC codes as FECs for optical transmission, and it is predicted that regular non-binary LDPC codes with high code rates can be applied as FECs for next-generation optical communications.

The decoding algorithm of a non-binary LDPC code can be decoded by applying a probability-based sum-product algorithm. The sum-product algorithm is an optimal decoding algorithm, but the computational complexity is quite large. To solve this problem, an extended min-sum algorithm and a min-max algorithm have been proposed. The above two algorithms perform decoding using the log likelihood ratio (LLR) value of the received symbol for non-binary LDPC decoding. This greatly reduces the computational complexity of the decoder because complex multiplication operations in probability-based algorithms can be implemented using addition operations.

In particular, when applying the minimum-maximum algorithm for the implementation of the check node operator of the non-binary LDPC decoder, the addition operation when the extended minimum-sum algorithm is applied satisfies a parity check matrix for each row. It is converted to be calculated by taking the minimum of the maximum values of. In order to calculate the minimum-maximum algorithm, forward metrics and backward metrics are first calculated and merged. However, since the computation process of the minimum-maximum algorithm is performed in a recursive manner, the delay of the check node operation unit of the decoder becomes long, which makes it difficult to increase the data throughput of the decoder. .

Block-layer-based decoder structure that processes non-overlapping rows at once in regular non-binary QC-LDPC code decoder design and 2-way merging to reduce the delay time of check node operation that takes the most computational delay (2 The present invention provides a method for implementing a decoder of a fast normal non-binary LDPC code including a check node operation unit applying a minimum-maximum algorithm and structure.

The decoding apparatus of the non-binary QC-LDPC code includes a check node calculating unit which performs check node processing using a min-max algorithm. In this case, the check node calculator is composed of a min-max block of a structure for calculating each row of the parity check matrix as one block layer. Merge Processing can be performed in two directions.

According to an aspect, the minimum-maximum operation block may include a minimum-maximum operation part, which is a basic operation unit that finds the minimum value among the log likelihood ratio (LLR) values of the received symbols, as the number of elements of the Galois.

According to another aspect, the check node operator may receive two input vectors for each operation cycle, and may input LLR values for each input vector as many as the number of elements of the Galois body.

According to another aspect, the decoding apparatus of the non-binary QC-LDPC code may further include a scheduler that controls scheduling of the input vector of the check node calculator.

, 수학식 2:According to another aspect, the minimum-maximum algorithm includes forward metrics, backward metrics, and merge processing, with the minimum-maximum computation being mathematical in the forward and backward metrics. And a switch network that controls to calculate the combination generated by Equation 1 and calculates the combination generated by Equation 2 in a merge operation. Equation 1:

, Equation 2:

(여기서, a, a', a"는 갈루아 체의 원소를 나타내고, h_{m ,n} 은 패리티 검사 행렬의 원소를 나타낸다.)

(Where a, a ', a "represents an element of a galois, and h _{m , n} represents an element of a parity check matrix.)

According to another aspect, the check node operation unit performs a first check node block for forward metric operation, a second check node block for backward metric operation, and an L-merge operation at the same time as the forward metric operation. And a fourth check node block for an R-merging operation at the same time as the L-merge operation.

According to another aspect, the first check node block and the second check node block recursively use a result of a switch network, forward metric operation, or backward metric operation for adjusting an input value in each operation cycle in a next operation cycle. And a register for storing the result of the minimum-maximum operation block, forward metric operation, or backward metric operation of the structure.

According to another aspect, the third check node block and the fourth check node block recursively use a result of a switch network, an L-merge operation, or an R-merge operation to adjust an input value in each calculation cycle in a next calculation cycle. It may include the minimum-maximum operation block of the enemy structure.

According to another aspect, the check node calculator performs a forward metric operation and a backward metric operation for a predetermined operation cycle (the order of the check nodes: d _c ), and the L− from the midpoint of the operation cycle (d _c / 2). Merge operation and R-merge operation may proceed.

According to another aspect, the check node calculator may further include a memory for storing the operation result up to the intermediate point (d _c / 2) among the results of the forward metric operation and the backward metric operation. In this case, the operation result after the intermediate point d _c / 2 may be input to the third check node block and the fourth check node block.

According to an embodiment of the present invention, in the implementation of the decoder of the non-binary QC-LDPC code, the non-overlapping rows of the parity check matrix may be treated as block-layers to improve the overall data rate of the decoder.

According to an embodiment of the present invention, by applying the 2-way merge minimum-maximum algorithm and structure, the computation delay time of the check node operation unit can be reduced by half, and thus it can be applied to the implementation of a fast non-binary QC-LDPC decoder. have.

1 is a flowchart illustrating a decoding process of a general non-binary LDPC decoder.
2 is an exemplary diagram showing a parity check matrix of a normal non-binary QC-LDPC 225, 165 defined in the GF 2 ⁴ for explaining the present invention.
3 is an exemplary diagram of a circulant permutation matrix (CPM) corresponding to α ³ defined in GF 2 ⁴ for explaining the present invention.
4 is a diagram illustrating a structure of a minimum-maximum calculation unit according to an embodiment of the present invention.
5 is a diagram illustrating a structure of a minimum-maximum operation block according to an embodiment of the present invention.
6 is a diagram illustrating a scheduling method of a switch network 1 for a minimum-maximum calculation unit according to an embodiment of the present invention.
FIG. 7 is a diagram illustrating a calculation sequence of a forward metric, a backward metric, an R-merge, and an L-merge in a 2-way merging minimum-maximum algorithm according to an embodiment of the present invention.
FIG. 8 is a diagram illustrating how computational delay is reduced when applying a 2-way merge minimum-maximum algorithm according to an embodiment of the present invention.
9 is a diagram illustrating the structure of a check node block-1 for calculating a forward metric and a backward metric according to an embodiment of the present invention.
FIG. 10 is a diagram illustrating a structure of a check node block-2 for calculating an R-merge and an L-merge according to an embodiment of the present invention.
FIG. 11 is a diagram illustrating scheduling of a switch network 2 applied to check node block-1 and check node block-2 according to an embodiment of the present invention.
12 is a diagram illustrating a structure of a check node calculator to which a 2-way merging minimum-maximum algorithm is applied according to an embodiment of the present invention.
FIG. 13 is a diagram of the entire structure of a block-layer based non-binary QC-LDPC decoder according to an embodiment of the present invention.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to or limited by the embodiments.

In the present embodiment, a description is made based on the non-binary QC-LDPC (225, 165) code, in which the order of variable nodes defined in GF (2 ⁴ ) is 3 and 4, and the order of check nodes is 14, and the present invention provides various communication. The same applies to the implementation of non-binary QC-LDPC codes for the system. Like reference symbols in the drawings denote like elements.

Since Shannon published the theory of noise channel coding in 1948, channel codes have evolved progressively to reach Shannon's theoretical limits. Originally discovered by Gallagher in the 1960s, the LDPC code has received a lot of attention over the past 20 years due to its robust error correction performance and is now being adopted and used in many communications systems. Recently, interest has increased due to the discovery of non-binary LDPC codes defined by Galois parity check matrix by Davey and Mackay. Non-binary LDPC codes show robust error correction capabilities that reach the limits of Shannon even at a proper code length than conventional LDPC codes.

As an algorithm for decoding a non-binary LDPC code, a computation process of a probability-based sum-product algorithm requires a large amount of multiplication, which causes a considerable problem for the actual implementation. Algorithms using LLR values have been proposed to replace this, and representatively, there are extended minimum-sum algorithm and minimum-maximum algorithm. Both algorithms operate using LLR, but the paper reported that the min-max algorithm shows less SNR reduction than the extended min-sum algorithm. Therefore, when considering the hardware implementation, it is advantageous to apply the minimum-sum algorithm.

1 is a flowchart illustrating a decoding process of a general non-binary LDPC decoder.

과

의 뺄셈 연산으로 복호 과정이 시작된다. 이에 따라 생성된 α_m,n(a) 값이 체크 노드 연산부로 입력되어 체크 노드 연산부의 연산이 진행된다.

_m,n(a)값이 체크 노드 연산부의 결과로써 출력이 되어 메모리에 저장되며, 동시에 후위 메세지 연산

_m,n(a) 의 α_m,n(a) 덧셈이 진행된다. 최종적으로,

값이 정규화 과정을 거쳐 생성된

값이 변수 노드 연산부로 다시 입력되는 반복 복호 과정을 거치게 된다.The symbol of the codeword received from the channel is converted into the LLR value and input to the variable node calculator and stored in the memory.

and

The decoding process begins with the subtraction operation of. Thus, the generated α _{m, n} ( a ) value is input to the check node calculator and the check node calculator performs the calculation.

_{The m, n} ( a ) value is output as a result of the check node operator and stored in the memory.

_{m, n} ( a ) addition of _{m, n} ( a ) proceeds. Finally,

Value is generated by normalization

The value is input to the variable node calculator again and iteratively decoded.

2 is an exemplary diagram showing a parity check matrix of a normal non-binary QC-LDPC 225, 165 defined in the GF 2 ⁴ for explaining the present invention.

Several types of non-binary LDPC codes have been proposed. In particular, for an embodiment of the present invention, a non-binary LDPC code may be generated through a parity check matrix using a row-constrained (RC-constrained) array expansion method.

3 is an exemplary diagram of a cyclic substitution matrix corresponding to α ³ defined in GF (2 ⁴ ) for explaining the present invention.

The cyclic substitution matrix is a sub-matrix that is used as a base unit in generating the non-binary LDPC code used in the present invention. The elements of the defined galois form an element in a diagonal direction, and the others are filled with zero elements. Square matrix.

Equation 1 shows the operation of the block-layer based minimum-maximum algorithm. Likewise, a block-layer-based decoding method that processes non-overlapping rows in a block unit as well as LDPC codes can be applied. This method enables the operation of many rows at once. This has the advantage of improving the convergence speed. In the present invention, one block unit may process 15 rows at a time because the cyclic substitution matrix constituting the parity check matrix is 15 × 15.

4 is a diagram illustrating a structure of a minimum-maximum calculation unit according to an embodiment of the present invention. The embodiment of the present invention may apply the minimum-maximum operator according to the minimum-maximum algorithm in implementing the check node calculator.

In the check node operation, the minimum-maximum operation occurs throughout the forward metric, backward metric, and merge operations as shown in equations (2), (3) and (4).

The minimum-maximum decoding algorithm for non-binary LDPC codes is an algorithm for finding the minimum value among the maximum values satisfying a specific condition in the check node operation. The minimum-maximum operation part receives LLR values as many as the number of elements of the Galois defined, and continuously stores the minimum value in the register (D) through a continuous calculation process. Galois defined in the present invention is a GF (2 ⁴ ) receives a total of 16 inputs and proceeds with the operation.

FIG. 5 is a diagram illustrating a structure of a minimum-maximum calculation block including the minimum-maximum calculation unit described with reference to FIG. 4.

In an embodiment of the present invention, a minimum-maximum calculation block including 15 minimum-maximum calculation units is designed and applied to process 15 rows at a time in order to perform a check node operation on a block-layer basis. The 15 min-max computations that are applied are all of the same structure, but the control of switch network 1 is determined by the elements of the parity check matrix corresponding to each computation cycle.

6 is a diagram illustrating a scheduling method of a switch network 1 for a minimum-maximum calculation unit according to an embodiment of the present invention.

Equation 5 is an equation used to control the switch network 1 used in the forward metric and the backward metric.

Equation 6 is an equation used to control the switch network 1 used in the merge operation.

A, a 'and a "in Equations 5 and 6 represent the elements in the galois. Switch network 1 determines the value of a determined when the elements h _{m and n} of the corresponding parity check matrix are determined. You can do this by looking for a combination of and a ". For example, suppose h _{m , n} is defined as α ⁵ , and you operate on a = 0, a = α ⁰ , ..., a = α ¹⁴ , two unknown symbols h _{m , n} and a Since we can determine the symbol combinations of a 'and a "by substituting all Galois symbols.

Equation 7 is an equation for the method to be obtained when it is defined as h _{m , n =} α ⁵ , f (α ¹ ) in the manner described above. Through this, all combinations of a 'and a "0-α ¹¹ , α ⁰ -α ¹⁴ , α ¹ -0, α ² -α ⁰ , ..., α ¹⁴ -α ² can be found.

The minimum-maximum algorithm of the conventional non-binary LDPC code is performed through a forward metric, a backward metric, and a merge operation as defined in Equations 2, 3, and 4. Each operation is performed in a recursive manner. In other words, the merge operation cannot be calculated until the operation of the forward metric and the backward metric is finished. Therefore, it takes as long as d _c × 2 cycles (one cycle is the operation time of the minimum maximum operation block), which causes a long delay in the operation of the decoder.

Equation 8 shows the operation of the 2-merge minimum-maximum algorithm for reducing the delay of the check node calculation unit in the present invention.

FIG. 7 is a diagram illustrating a calculation sequence of a forward metric, a backward metric, an R-merge, and an L-merge in a 2-way merging minimum-maximum algorithm according to an embodiment of the present invention.

In the implementation of the check node operation unit, if two operation blocks can be used for the merge operation, the two-merger minimum-maximum algorithm proposed by the present invention may be applied. For example, since the order of the check node is 14 in the parity check matrix used in the present invention, the forward metric is calculated from F1 to F13, and the backward metric is calculated from B14 to B2, and then a merge operation is performed. As a result of applying the two-merger minimum-maximum algorithm, the operation delay of the check node operation unit is reduced according to the conventional minimum-maximum by independently dividing and executing the R-merge operation and the L-merge operation after the middle of the forward and backward metrics. It can be cut in half compared to the algorithm.

FIG. 8 is a diagram illustrating how computational delay is reduced when applying a 2-way merge minimum-maximum algorithm according to an embodiment of the present invention.

While the forward metric and the backward metric are computed during the d _c -1 cycle, the R-merge operation and the L-merge operation are simultaneously performed from the middle, and the merge operation is also terminated simultaneously when the forward metric and the backward metric operation are finished. Becomes An additional operation block is required to simultaneously process an R-merge and an L-merge operation for a merge operation, but it has an advantage of reducing the computational delay of the check node operation unit in half.

9 is a diagram illustrating the structure of a check node block-1 for calculating a forward metric and a backward metric according to an embodiment of the present invention.

The structure of check node block-1 consists of one switch network 2 and one minimum-maximum operation block. The operation of the forward metric and the backward metric is a recursive structure that uses the output value in the next calculation cycle. In Switch Network 2, it allows you to adjust the input value at every calculation cycle. It also contains a register (D) for storing the result of the calculation.

10 is a diagram illustrating the structure of a check node block-2 for calculating an R-merge and an L-merge according to an embodiment of the present invention.

The basic structure is the same as that of the check node block-1, but the register D of the last stage is removed because there is no need to store and use the operation result again.

FIG. 11 is a diagram illustrating scheduling of a switch network 2 applied to check node block-1 and check node block-2 according to an embodiment of the present invention.

The check node block-1 and the check node block-2 include 15 minimum-maximum arithmetic blocks to operate 15 rows corresponding to the block-layer at a time. Therefore, the input should be adjusted according to the values of h _{m and n} of the parity check matrix for every operation cycle.

For example, consider the first row of the first block layer as an example: the 14th (α ¹⁴ ) output in the min-max operation block corresponds to the ^13th (α ¹³ ) min-max operation block in the next calculation cycle. Used as input of In the next arithmetic cycle, the 13th (α ¹³ ) output is used as the input for the ^7th (α ⁷ ) minimum-maximum arithmetic block. In this way, the control signal of the switch network 2 can be generated according to the corresponding h _{m , n} values for all rows of the block-layer until the last 15th operation cycle.

12 is a diagram illustrating a structure of a check node calculator to which a 2-way merging minimum-maximum algorithm is applied according to an embodiment of the present invention.

Two check node blocks-1 (FIG. 9) are used for forward metric and backward metric operations, and two check node blocks-2 (FIG. 10) are used for R-Merge and L-Merge operations. The check node operator receives two input vectors A0 to A14 and B0 to B14 for each operation cycle. As a result of the seventh operation during the operation of the forward metric and the backward metric, F1 to F7 are stored in the forward metric memory and B14 to B8 are stored in the backward metric memory. Subsequent forward metric and backward metric calculations are performed, and the R-merge and L-merge operations are immediately followed, finally ending the d _c -1 calculation cycle.

The control signal of the MUX in the dotted line box is kept at '1' for at least 7-operation cycles, and then converted to '0', so that the result of the calculation of the forward and backward metrics is F8 to F13 and B7 to B2. Can be used for Merge and L-Merge operations. In addition, since the depth of the memory to store the operation result of the forward metric and the backward metric is (d _c / 2) -1, it is enough to reduce the size of the memory in half.

FIG. 13 is a diagram of the entire structure of a block-layer based non-binary QC-LDPC decoder according to an embodiment of the present invention.

Since the parity check matrix applied in the present invention is defined in the Galois GF (2 ⁴ ), the complexity is increased by about 16 times compared to the conventional LDPC code. The decoder operates after the LLR value of the symbol received from the first channel is stored in the variable node memories 0 to 14. Shift register blocks are also used as buffering and pipeline registers for addition and subtraction operations that occur during the decoding process. Since the check node calculator applied to the present invention receives two input vectors in every calculation cycle, a check node calculator scheduler for controlling the check node operator is required.

The operation result of the check node operation unit is stored in the check node memory, and after the normalization process through the previous operation value and the addition operation, is stored in the variable node memory again. The decoding process ends when the parity check is completed or the maximum number of repeated decoding is reached.

As described above, the decoder structure of the non-binary QC-LDPC code is designed based on block-layer to enable fast convergence of the decoder. In addition, by implementing a check node operator by applying a 2-way merge minimum-maximum algorithm, the delay of the check node operator may be reduced by half. Therefore, one embodiment of the present invention has the potential to be applied to the decoder implementation of a non-binary QC-LDPC code that can be developed in the future.

As described above, the present invention has been described by way of limited embodiments and drawings, but the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains various modifications and variations from such descriptions. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the equivalents of the claims, as well as the claims.

Claims (10)

In the decoding device of non-binary QC-LDPC (Non-Binary Quasi Cyclic Low-Density Parity Check) code,
Check node processing unit that performs check node processing using a min-max algorithm that finds the minimum value among the maximum values
Lt; / RTI >
The check node calculator,
It consists of a min-max block of a structure that calculates each row of the parity check matrix as one block layer. In the 2-way direction, the merging operation is divided into an L-merging operation and a R-merging operation to simultaneously perform the L-merging operation and the R-merging operation.
The unit matrix constituting the parity check matrix is an N × N square matrix in which elements located in a diagonal direction of the matrix are composed of Galois-Field elements and the remaining elements of the matrix are 0.
The minimum-maximum calculation block,
The minimum-maximum operation part, which is a basic operation unit for finding the minimum value among the log likelihood ratio (LLR) values of the received symbols, is composed of the number of elements of the Galois, and the unit matrix for performing the check node operation based on a block layer Consisting of N min-max operators to process N at a time by N rows
A decoding apparatus of a non-binary QC-LDPC code, characterized in that. delete The method of claim 1,
The check node calculator,
Two input vectors are input for each operation cycle, and a log likelihood ratio (LLR) value is input for each of the input vectors by the number of elements of the Galois.
A decoding apparatus of a non-binary QC-LDPC code, characterized in that. The method of claim 3,
The decoding apparatus of the non-binary QC-LDPC code,
A scheduler for controlling scheduling of the input vector of the check node calculator
Decoding device of a non-binary QC-LDPC code further comprising. The method of claim 1,
The minimum-maximum algorithm is
Includes forward metrics, backward metrics, and merge processing,
The minimum-maximum calculation unit,
And a switch network that controls to calculate the combination generated by Equation 1 in the forward metric and the backward metric, and calculates the combination generated by Equation 2 in the merge operation.
A decoding apparatus of a non-binary QC-LDPC code, characterized in that.
Equation 1:

Equation 2:

(Where a, a '. A "represents an element of the Galois body, and h _{m, n} represents an element of the parity check matrix.) The method of claim 1,
The check node calculator,
A first check node block for forward metric calculation,
A second check node block for calculating backward metrics simultaneously with the operation of the forward metric;
A third check node block for an L-merge operation,
A fourth check node block for an R-merging operation simultaneously with the L-merge operation;
Memory for storing results of the forward metric operation and the backward metric operation
Including,
The forward metric operation and the backward metric operation are performed for a predetermined operation cycle d _c , and the L-merge operation and the R-merge operation are simultaneously performed from an intermediate point d _c / 2 of the operation cycle. The L-merge operation and the R-merge operation are terminated at the same time when the forward metric operation and the backward metric operation are terminated.
Among the results of the forward metric operation and the backward metric operation, the operation result up to the intermediate point d _c / 2 is stored in the memory, and the operation result after the intermediate point d _c / 2 is the third. Input to a check node block and the fourth check node block
A decoding apparatus of a non-binary QC-LDPC code, characterized in that. The method according to claim 6,
The first check node block and the second check node block,
Switch network to adjust input value in each operation cycle,
A minimum-maximum operation block of a recursive structure that uses the result of the forward metric operation or the backward metric operation in a next operation cycle,
A register for storing a result of the forward metric operation or the backward metric operation
Decoding device of a non-binary QC-LDPC code comprising a. The method according to claim 6,
The third check node block and the fourth check node block,
Switch network to adjust input value in each operation cycle,
Minimum-maximum computation block of a recursive structure that uses the result of the L-merge operation or the R-merge operation in the next computation cycle
Decoding device of a non-binary QC-LDPC code comprising a. delete delete

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