CN110113058B - Coding and decoding method, device, equipment and computer readable storage medium - Google Patents
Coding and decoding method, device, equipment and computer readable storage medium Download PDFInfo
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- CN110113058B CN110113058B CN201910481125.3A CN201910481125A CN110113058B CN 110113058 B CN110113058 B CN 110113058B CN 201910481125 A CN201910481125 A CN 201910481125A CN 110113058 B CN110113058 B CN 110113058B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
Abstract
The embodiment of the invention provides a coding and decoding method, a device, equipment and a computer readable storage medium, wherein the coding method comprises the following steps: acquiring data to be stored, and performing Turbo Product Code (TPC) encoding treatment on the data to be stored to obtain a two-dimensional TPC codeword matrix; arranging the two-dimensional TPC codeword matrix into a one-dimensional TPC code sequence; performing BCH coding treatment on the one-dimensional TPC code sequence to obtain a coding result corresponding to the data to be stored; writing the coding result corresponding to the data to be stored into a memory; the decoding of the stored data can be realized by a corresponding decoding method. The embodiment of the invention provides a TPC code cascade BCH code mode, which not only utilizes the advantages of low complexity and strong error correction capability of TPC codes, but also overcomes the defect of high level of TPC code errors through cascade BCH codes, and can meet the requirement of low implementation complexity and reduce the error rate of data storage through the TPC code cascade BCH code mode.
Description
Technical Field
Embodiments of the present invention relate to the field of computer technologies, and in particular, to a coding and decoding method, device, apparatus, and computer readable storage medium.
Background
With the rapid development of semiconductor technology, semiconductor memories using semiconductor circuits as storage media have also been rapidly developed. The Nand Flash memory is used as a nonvolatile memory, and has many advantages such as fast erasing speed, low power consumption, large capacity, low cost, etc., so it has become the most commonly used storage device in the data storage field. However, with the increase of storage density and the advent of multi-bit storage technology, the problem of bit error rate of Nand Flash memory during data storage is more and more serious.
Error correcting codes applied to NAND FLASH in the prior art are BCH codes (Bose, chaudhuri & Hocquenghem Type of code, bose-Chaudhuri-hockey black) and LDPC codes (Low Density Parity Check Code, low density parity check codes). Among them, the BCH code is a linear block code in a limited domain, has the ability to correct a plurality of random errors, has a simple construction, and is generally used for error correction coding in the fields of communication and storage. The LDPC code is a block error correction code with a sparse check matrix proposed in the doctor's paper in 1963 by Robert Gallager, the university of hemp and the university institute of technology. Its performance approaches shannon limit, and is the best error correcting code.
However, the error correction capability of the BCH code depends on the number of check bits, and the check bits cannot be too many due to the limitation of Flash memory, so that the error correction capability of the BCH code is limited. Under the condition that the check digits are the same, the error correction capability of the LDPC code is not as good as that of the LDPC code, and the LDPC code is complex in implementation and high in hardware cost. The existing coding and decoding method has high error rate for data storage under the condition of meeting the requirement of low implementation complexity.
Disclosure of Invention
The embodiment of the invention provides a coding and decoding method, a device, equipment and a computer readable storage medium, which are used for solving the problem that the error rate of data storage is high under the condition that the low implementation complexity requirement is met in the existing coding and decoding method.
In a first aspect, an embodiment of the present invention provides an encoding method, including:
obtaining data to be stored, and performing Turbo Product Code (TPC) coding treatment on the data to be stored to obtain a two-dimensional TPC codeword matrix;
arranging the two-dimensional TPC codeword matrix into a one-dimensional TPC code sequence;
performing bose-chaudhuri-hockey black-matrix BCH coding processing on the one-dimensional TPC code sequence to obtain a coding result corresponding to the data to be stored;
and writing the coding result corresponding to the data to be stored into a memory.
In a possible implementation manner, the two-dimensional TPC codeword matrix is a plurality, and the two-dimensional TPC codeword matrix corresponds to the one-dimensional TPC code sequence one by one;
the performing BCH encoding processing on the one-dimensional TPC code sequence to obtain an encoding result corresponding to the data to be stored, including:
combining a preset number of one-dimensional TPC code sequences;
and performing BCH coding on the one-dimensional TPC code sequences after the merging processing to obtain a coding result corresponding to the data to be stored.
In one possible implementation manner, the coding result corresponding to the data to be stored includes valid data bits, TPC check bits and BCH check bits.
In a second aspect, an embodiment of the present invention provides a decoding method, including:
reading encoded data stored in a memory, and performing BCH decoding processing on the encoded data;
arranging data obtained by BCH decoding into a two-dimensional TPC codeword matrix;
performing TPC decoding processing on the two-dimensional TPC codeword matrix to obtain a decoding result corresponding to the encoded data;
and outputting a decoding result corresponding to the encoded data.
In one possible implementation manner, the arranging the data obtained by the BCH decoding process into a two-dimensional TPC codeword matrix includes:
splitting data obtained by BCH decoding into a plurality of one-dimensional TPC code sequences;
for each one-dimensional TPC code sequence, arranging the one-dimensional TPC code sequence into a corresponding two-dimensional TPC code word matrix;
the performing TPC decoding processing on the two-dimensional TPC codeword matrix includes:
and performing TPC decoding processing on each two-dimensional TPC codeword matrix in sequence.
In a third aspect, an embodiment of the present invention provides an encoding apparatus, including:
the first coding module is used for acquiring data to be stored, and performing Turbo Product Code (TPC) coding processing on the data to be stored to obtain a two-dimensional TPC codeword matrix;
a first arrangement module, configured to arrange the two-dimensional TPC codeword matrix into a one-dimensional TPC code sequence;
the second coding module is used for carrying out bose-chaudhuri-hockey black matrix BCH coding processing on the one-dimensional TPC code sequence to obtain a coding result corresponding to the data to be stored;
and the writing module is used for writing the coding result corresponding to the data to be stored into the memory.
In a fourth aspect, an embodiment of the present invention provides an encoding apparatus, including: at least one processor and memory;
the memory stores computer-executable instructions;
the at least one processor executes computer-executable instructions stored in the memory such that the at least one processor performs the encoding method as described above in the first aspect and various possible implementations of the first aspect.
In a fifth aspect, an embodiment of the present invention provides a decoding apparatus, including: at least one processor and memory;
the memory stores computer-executable instructions;
the at least one processor executes computer-executable instructions stored by the memory such that the at least one processor performs the decoding method as described above in the second aspect and various possible implementations of the second aspect.
In a sixth aspect, an embodiment of the present invention provides a computer readable storage medium, where computer executable instructions are stored, when executed by a processor, to implement the encoding method according to the first aspect and the various possible implementation manners of the first aspect.
In a seventh aspect, an embodiment of the present invention provides a computer readable storage medium, where computer executable instructions are stored, where when executed by a processor, implement the decoding method according to the above second aspect and various possible implementation manners of the second aspect.
The coding and decoding method, the coding and decoding device, the coding and decoding equipment and the computer readable storage medium provided by the embodiment are used for obtaining data to be stored, and performing Turbo Product Code (TPC) coding treatment on the data to be stored to obtain a two-dimensional TPC codeword matrix; arranging the two-dimensional TPC codeword matrix into a one-dimensional TPC code sequence; carrying out Bose-Geoheli-Hokkonmer BCH coding processing on the one-dimensional TPC code sequence to obtain a coding result corresponding to data to be stored; the coding result corresponding to the data to be stored is written into the memory, so that the coding of the stored data can be realized; the decoding of the stored data can be realized by a corresponding decoding method. The embodiment of the invention provides a TPC code cascading BCH code mode, which not only utilizes the advantages of low complexity and strong error correction capability of TPC codes, but also overcomes the defect of high error leveling of TPC codes through cascading BCH codes, and reduces the error leveling.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of an encoding method according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a TPC coding data structure according to an embodiment of the present invention;
FIG. 3 is a flowchart of an encoding method according to another embodiment of the present invention;
fig. 4 is a schematic diagram of arranging two-dimensional TPC codeword matrices into one-dimensional TPC code sequences according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of the structure of encoded data according to an embodiment of the present invention;
FIG. 6 is a flow chart of a decoding method according to another embodiment of the present invention;
FIG. 7 is a flow chart of a decoding method according to another embodiment of the present invention;
fig. 8 is a flowchart of a Chase2 decoding algorithm according to an embodiment of the present invention;
fig. 9 is a block diagram of a serial iterative decoding structure of a Chase2 decoding algorithm according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of a storage system according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of an encoding device according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of a decoding device according to another embodiment of the present invention;
fig. 13 is a schematic hardware structure of an encoding device according to an embodiment of the present invention;
fig. 14 is a schematic hardware structure of a decoding device according to another embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 is a flowchart of an encoding method according to an embodiment of the invention. As shown in fig. 1, the method includes:
s101, acquiring data to be stored, and performing Turbo Product Code (TPC) coding processing on the data to be stored to obtain a two-dimensional TPC codeword matrix.
In this embodiment, the data to be stored is data that needs to be stored in the memory. The TPC encoding process is a process of encoding data in accordance with the encoding scheme of the TPC code. The two-dimensional TPC codeword matrix is a two-dimensional matrix obtained after TPC coding processing is carried out on data.
Alternatively, the TPC encoding process may pre-select two linear block codes C1 (n 1, k1, d 1) and C2 (n 2, k2, d 2), where n represents the codeword length, k represents the number of information bits, and d represents the minimum hamming distance. The specific encoding process may be: (1) Arranging k1×k2 information bits into a matrix C of k1×k2 order; (2) Carrying out row-by-row coding on k1 rows of the matrix C according to a coding rule of the row subcodes to obtain a k1 multiplied by n 2-order matrix C'; (3) And (3) carrying out column-by-column coding on n2 columns of the matrix C' according to the coding rule of the column subcodes to obtain an n1 multiplied by n 2-order matrix P shown in figure 2. The matrix P is a two-dimensional TPC codeword matrix, and comprises an information block, a row check block, a column check block and a check block for checking.
S102, arranging the two-dimensional TPC code word matrix into a one-dimensional TPC code sequence.
In this embodiment, BCH encoding is to encode one-dimensional data, so that two-dimensional TPC codeword matrices need to be arranged into one-dimensional TPC codeword sequences. The two-dimensional TPC codeword matrix may be one or more, and is not limited herein.
S103, carrying out Bose-Geoheli-Hokemel BCH coding processing on the one-dimensional TPC code sequence to obtain a coding result corresponding to the data to be stored.
In the present embodiment, the BCH encoding process is an encoding process performed on data in accordance with the encoding scheme of the BCH code. The BCH code is a linear block code in a finite field capable of correcting a plurality of random errors. When the number of symbols in which errors occur is less than or equal to the error correction capability of the BCH code, the BCH code can correct all the symbols in which errors occur.
Alternatively, the principle of the BCH encoding process is as follows: the polynomial m (x) corresponding to the valid data bits of length k can be noted as: m (x) =m0+m1 x 1+m2 x 2.+ mk-1 x k-1, wherein m0, m1, m2 … … mk-1 belong to {0,1}. If the generator polynomial g (x) of the BCH code is: g (x) =g0+g1 x≡1+g2 x≡2.+ gr ++x ζ where r represents the number of bits of the BCH parity bits and g0, g1, g2 … … gr-1 belong to {0,1}, the BCH parity bits can be determined by: shifting m (x) left by r bits, and dividing by a generator polynomial g (x), wherein the obtained remainder is a polynomial r (x) corresponding to the BCH check bit, i.e. r (x) =mod (x≡r m (x), g (x)), where mod represents the remainder of x≡r m (x) divided by g (x). The BCH code in this embodiment includes valid data bits and BCH check bits, for example, may be obtained by attaching the determined BCH check bits to the back of the valid data bits, that is, the polynomial expression corresponding to the BCH code may be: c (x) =x++r (x) +mod (x++r (x) m (x), g (x)), the length of the BCH code is (k+r).
It should be noted that, in this embodiment, the number of bits k of the valid data bits, the number of bits r of the BCH check bits, and the generator polynomial g (x) of the BCH code are not limited, and may be set according to specific requirements.
S104, writing the coding result corresponding to the data to be stored into a memory.
According to the embodiment of the invention, the data to be stored is obtained, and the data to be stored is subjected to the TPC encoding processing of the Turbo product code to obtain a two-dimensional TPC codeword matrix; arranging the two-dimensional TPC codeword matrix into a one-dimensional TPC code sequence; carrying out Bose-Geoheli-Hokkonmer BCH coding processing on the one-dimensional TPC code sequence to obtain a coding result corresponding to data to be stored; the coding result corresponding to the data to be stored is written into the memory, so that the coding of the stored data can be realized; the decoding of the stored data can be realized by a corresponding decoding method. The embodiment of the invention provides a TPC code cascade BCH code mode, which not only utilizes the advantages of low complexity and strong error correction capability of TPC codes, but also overcomes the defect of high error leveling of TPC codes through cascade BCH codes, reduces the error leveling of TPC codes, and can meet the requirement of low implementation complexity and reduce the error rate of data storage through the TPC code cascade BCH code mode because the cascade BCH codes do not occupy too many check bits and the increased calculated amount is small.
Fig. 3 is a flowchart of an encoding method according to another embodiment of the present invention. The specific implementation procedure of the BCH encoding process is described in detail in this embodiment. As shown in fig. 3, the method includes:
s301, obtaining data to be stored, and performing Turbo Product Code (TPC) coding processing on the data to be stored to obtain a two-dimensional TPC codeword matrix.
In this embodiment, S301 is similar to S101 in the embodiment of fig. 1, and will not be described here again.
S302, the two-dimensional TPC code word matrix is arranged into a one-dimensional TPC code sequence. The two-dimensional TPC code word matrixes are a plurality of, and the two-dimensional TPC code word matrixes are in one-to-one correspondence with the one-dimensional TPC code sequences.
In this embodiment, a plurality of two-dimensional TPC codeword matrices are obtained after TPC encoding processing. Each two-dimensional TPC codeword matrix is arranged into a corresponding one-dimensional TPC code sequence. The process of arranging the two-dimensional TPC codeword matrix into a one-dimensional TPC code sequence is shown in fig. 4, i.e., arranging a plurality of rows into one row for BCH encoding to follow. The process of arranging the one-dimensional TPC code sequence into a two-dimensional TPC code matrix during decoding is the inverse process of encoding.
S303, combining the preset number of one-dimensional TPC code sequences.
In this embodiment, the preset number may be set according to actual requirements, which is not limited herein. For example, the preset number may be 2,4,8, etc. N may be used to represent the preset number, and then the n one-dimensional TPC code sequences are combined into one sequence.
S304, performing BCH coding on the one-dimensional TPC code sequences after the merging processing to obtain a coding result corresponding to the data to be stored.
In this embodiment, BCH encoding is performed on the combined sequence to obtain an encoding result corresponding to the data to be stored. The coding result corresponding to the data to be stored may include a valid data bit, a TPC check bit, and a BCH check bit.
Fig. 5 is a schematic diagram of a structure of encoded data according to an embodiment of the present invention. As shown in fig. 5, the code element generated by the coding method provided in this embodiment sequentially includes: valid data bits, TPC check bits, and BCH check bits. Wherein, TPC check bits and BCH check bits are determined with reference to S301 and S304 described above, respectively.
S305, writing the coding result corresponding to the data to be stored into a memory.
According to the embodiment, the BCH codes are cascaded after the n TPC codes, the error leveling of TPC can be reduced through the cascaded BCH codes, the cascaded BCH codes occupy less check bits, the calculated amount is increased very little, the integral coding efficiency is not influenced, and the coding effect is ensured.
Fig. 6 is a flowchart of a decoding method according to another embodiment of the present invention. As shown in fig. 6, the method includes:
s601, reading the coded data stored in the memory, and performing BCH decoding processing on the coded data.
In this embodiment, the encoded data stored in the memory is data encoded according to the above-described encoding method. When retrieving data from memory, the encoded data in memory needs to be decoded. First, the coded data stored in the memory is read, and BCH decoding processing is performed on the coded data. The BCH decoding process may be: (1) calculating a syndrome s; (2) if s=0, decoding is correct; otherwise, finding out an error pattern e according to the syndrome s; (3) And carrying out bit exclusive OR on the input codeword r and the e to obtain a decoded output codeword r'.
S602, arranging data obtained by BCH decoding processing into a two-dimensional TPC codeword matrix.
In this embodiment, since TCP decoding is required to be performed on the data obtained by the BCH decoding processing subsequently, the data obtained by the BCH decoding processing is arranged into a two-dimensional TPC codeword matrix here. The two-dimensional TPC codeword matrix may be one or more, and is not limited herein. The arrangement process of step S602 is the inverse of the arrangement process of step S302, and will not be described in detail herein.
S603, performing TPC decoding processing on the two-dimensional TPC codeword matrix to obtain a decoding result corresponding to the encoded data.
In this embodiment, TPC decoding is performed on the two-dimensional TPC codeword matrix to obtain a decoding result corresponding to the encoded data. The specific manner of TPC decoding is not limited, and may be determined according to actual requirements.
S604, outputting a decoding result corresponding to the encoded data.
The embodiment reads the coded data stored in the memory and performs BCH decoding processing on the coded data; arranging data obtained by BCH decoding into a two-dimensional TPC codeword matrix; performing TPC decoding processing on the two-dimensional TPC codeword matrix to obtain a decoding result corresponding to the encoded data; the decoding result corresponding to the encoded data is outputted, so that the data encoded according to the encoding method can be decoded.
Fig. 7 is a flowchart of a decoding method according to another embodiment of the present invention. As shown in fig. 7, the method includes:
s701, reading the coded data stored in the memory, and performing BCH decoding processing on the coded data.
In this embodiment, S701 is similar to S601 in the embodiment of fig. 6, and will not be described here again.
S702, splitting data obtained by BCH decoding into a plurality of one-dimensional TPC code sequences.
In this embodiment, for the data encoded according to the encoding scheme provided in the embodiment of fig. 3, since n one-dimensional TPC code sequences are combined into one sequence in the encoding process, the data obtained after BCH decoding needs to be split into multiple one-dimensional TPC code sequences in the decoding process.
S703, for each one-dimensional TPC code sequence, arranging the one-dimensional TPC code sequence into a corresponding two-dimensional TPC code word matrix.
In this embodiment, the one-dimensional TPC code sequence corresponds to the two-dimensional TPC code matrix one by one. Each one-dimensional TPC code sequence is arranged into a corresponding two-dimensional TPC codeword matrix, respectively.
S704, performing TPC decoding processing on each two-dimensional TPC codeword matrix in sequence to obtain a decoding result corresponding to the encoded data.
In this embodiment, S704 is similar to S603 in the embodiment of fig. 6, and will not be described here again.
Optionally, decoding the two-dimensional TPC codeword matrix according to a Chase2 soft-input soft-output serial iterative decoding algorithm.
In this embodiment, a Chase2SISO (Soft Input Soft Output ) serial iterative decoding algorithm is used as a decoding method of TPC, and the decoding process is described as follows:
(1) Chase2 decoding is performed, as shown in fig. 8, using the reliability of the symbol, finding the least reliable bit to generate an error pattern set, then using a hard decision decoder to generate several candidate codewords according to different heuristic sequences, and then comparing them with the hard decision sequence to select a candidate codeword having the smallest euclidean distance from the hard decision sequence as the output codeword of the decoder.
(2) The soft output information is then calculated as input for the next iteration according to the following formula.
Wherein r is j For soft input of information, w j R is external information j ' is soft output information, r l Is the first bit, d, of the information sequence R l Is the first bit of the optimal codeword D.
(3) The decoding operation is continued according to the serial iterative decoding algorithm shown in fig. 9 until the maximum number of iterations is reached.
(4) And finishing iteration and outputting a decoding result.
Wherein, the serial iterative relation is: [ R ] in (m)]＝(1-α(m))[R in (m-1)]+α(m)[R out (m-1)]And [ R ] in (0)]For the channel raw information matrix R]M represents an mth iterative decoding unit, which may also be referred to as a half-iterative ordinal number, [ R ] in (m-1)]For the soft input matrix of the last iteration, [ R ] out (m-1)]For the soft output matrix of the last iteration, α (m) is a scaling factor, the value of which can also be determined experimentally or empirically.
The specific serial iterative decoding algorithm is as follows: after receiving the channel original information matrix [ R ], firstly performing row-by-row decoding by using a Chase2 decoding algorithm to obtain an optimal decision codeword, and then calculating corresponding soft output and external information, wherein when all rows in the [ R ] are decoded, the first half iteration is realized; the soft input for column decoding is then computed, the column decoding process being the same as the row decoding. When all columns in [ R ] are decoded, a second half iteration is realized, namely a complete iteration process of the two-dimensional TPC is completed.
And S705, outputting a decoding result corresponding to the encoded data.
As an example of implementation of the present invention, it is assumed that the effective data length k is 1034 bytes, and the code rate is required to be 0.85-0.9. If the coding and decoding method provided by the embodiment is adopted, the row subcodes and the column subcodes can be respectively selected to expand BCH code (128,120,4) and expanded BCH code (74,69,4), the two-dimensional TPC code length is 9472 bits, the effective data length is 8280 bits, the code rate is 0.87, and the maximum error correction capability t=max { n } 1 t 2 ,n 2 t 1 } = 128 bits, where n 1 ,n 2 ,t 1 ,t 2 The code length and error correction capability of the row and column subcodes, respectively. If the expanded BCH codes with the same code rate are adopted, the expanded BCH codes with the code length n of 9643 bits are selected according to the effective data length of 8272 bits, and then the minimum value 14 of m meeting the n| (2 m-1) can be determined, so that the error correction capability of the expanded BCH codes is improved
The bit is obviously smaller than the error correction capability of the TPC with the same code rate.
As still another embodiment of the present invention, the execution bodies of the encoding method and the decoding method may be the same apparatus capable of performing both the encoding method to encode the data to be stored and the decoding method to decode the encoded data in the memory, specifically: acquiring data to be stored, and performing Turbo Product Code (TPC) encoding treatment on the data to be stored to obtain a two-dimensional TPC codeword matrix; arranging the two-dimensional TPC codeword matrix into a one-dimensional TPC code sequence; carrying out Bose-Geoheli-Hokkonmer BCH coding processing on the one-dimensional TPC code sequence to obtain a coding result corresponding to data to be stored; and writing the coding result corresponding to the data to be stored into the memory. Reading the coded data stored in the memory, and performing BCH decoding processing on the coded data; arranging data obtained by BCH decoding into a two-dimensional TPC codeword matrix; performing TPC decoding processing on the two-dimensional TPC codeword matrix to obtain a decoding result corresponding to the encoded data; and outputting a decoding result corresponding to the encoded data.
As another embodiment example of the present invention, the encoding process is: performing TPC coding on effective data with the length of 1034 bytes to generate a 128 x 74 bit two-dimensional TPC codeword matrix; respectively arranging 4 two-dimensional TPC codeword matrixes into 4 one-dimensional TPC code sequences; and combining the 4 one-dimensional TPC codes and then performing BCH coding to generate a BCH code. The decoding process is to sequentially perform BCH decoding processing on the coded data; splitting and arranging the data subjected to BCH decoding into 4 two-dimensional TPC codeword matrixes; and performing TPC decoding processing on the 4 two-dimensional TPC codeword matrixes in sequence according to the improved Chase2SISO serial iterative decoding algorithm.
Fig. 10 is a schematic diagram of a storage system according to an embodiment of the present invention. As shown in fig. 10, in the memory system provided in this embodiment, the encoding circuit includes a TPC encoder and a BCH encoder that are sequentially connected, and the decoding circuit includes a BCH decoder and a TPC decoder that are sequentially connected. The input data generates TPC codes through a TPC coder, then generates BCH codes through a BCH coder, and stores the BCH codes into a memory. When data is read from the memory, firstly, the data passes through the BCH decoder and then the TPC decoder, and after a certain number of iterations, the input data which is stored at the beginning is obtained.
The traditional ECC (Error Correcting Code, error correction code) method applied to NAND FLASH comprises a BCH code and an LDPC code, but the error correction capability of the BCH code is limited by the number of check bits, and the LDPC code has complex realization and high hardware cost. Under the condition of the same code rate, the error correction capability of the TPC code is superior to that of the BCH code and is close to that of the LDPC code; and the implementation complexity is lower than that of the LDPC code. Although the TPC code error floor is higher, the NAND FLASH error location is generally more diffuse, somewhat weakening the impact of the TPC code disadvantage. The decoding performance and the implementation complexity are comprehensively considered, the TPC subcode selects and expands the BCH code, the least reliable bit number selects 2 bits, and the 2 bits are used because the complexity is not high and the performance is good.
Considering that the TPC error floor is high, the embodiment of the present invention proposes a method of concatenating BCH codes after n TPC codes, where n depends on Flash, possibly 2,4,8, etc. The error leveling is formed by uncorrectable errors after TPC decoding, and the error leveling of TPC codes can be reduced by cascading BCH codes, and meanwhile, too many check bits are not occupied, and too much calculated amount is not increased. The embodiment of the invention adds BCH decoding on the basis of adopting TPC decoding algorithm, on one hand, the decoding complexity is lower, on the other hand, the error leveling is reduced, and the error correction performance of the decoding system is ensured.
According to the embodiment of the invention, the data to be stored is obtained, and the data to be stored is subjected to the TPC encoding processing of the Turbo product code to obtain a two-dimensional TPC codeword matrix; arranging the two-dimensional TPC codeword matrix into a one-dimensional TPC code sequence; carrying out Bose-Geoheli-Hokkonmer BCH coding processing on the one-dimensional TPC code sequence to obtain a coding result corresponding to data to be stored; the coding result corresponding to the data to be stored is written into the memory, so that the coding of the stored data can be realized; the decoding of the stored data can be realized by a corresponding decoding method. The embodiment of the invention provides a TPC code cascade BCH code mode, which not only utilizes the advantages of low complexity and strong error correction capability of TPC codes, but also overcomes the defect of high error leveling of TPC codes through cascade BCH codes, reduces the error leveling of TPC codes, and can meet the requirement of low implementation complexity and reduce the error rate of data storage through the TPC code cascade BCH code mode because the cascade BCH codes do not occupy too many check bits and the increased calculated amount is small.
Fig. 11 is a schematic structural diagram of an encoding device according to an embodiment of the invention. As shown in fig. 11, the encoding apparatus 110 includes: a first encoding module 1101, a first arrangement module 1102, a second encoding module 1103, and a writing module 1104.
The first encoding module 1101 is configured to obtain data to be stored, and perform a Turbo product code TPC encoding process on the data to be stored to obtain a two-dimensional TPC codeword matrix.
A first permutation module 1102 is configured to rank the two-dimensional TPC codeword matrix into a one-dimensional TPC code sequence.
The second encoding module 1103 is configured to perform bose-chaudhuri-hockey black matrix BCH encoding processing on the one-dimensional TPC code sequence, so as to obtain an encoding result corresponding to the data to be stored.
The writing module 1104 is configured to write the encoding result corresponding to the data to be stored into a memory.
In the embodiment of the invention, a first coding module obtains a two-dimensional TPC codeword matrix by acquiring data to be stored and performing TPC coding processing on the data to be stored by a Turbo product code; the first arrangement module arranges the two-dimensional TPC codeword matrix into a one-dimensional TPC code sequence; the second coding module performs the Bose-Geoheli-Hockel black-mu BCH coding processing on the one-dimensional TPC code sequence to obtain a coding result corresponding to the data to be stored; the writing module writes the coding result corresponding to the data to be stored into the memory, so that the coding of the stored data can be realized; the decoding of the stored data can be realized by a corresponding decoding method. The embodiment of the invention provides a TPC code cascade BCH code mode, which not only utilizes the advantages of low complexity and strong error correction capability of TPC codes, but also overcomes the defect of high error leveling of TPC codes through cascade BCH codes, reduces the error leveling of TPC codes, and can meet the requirement of low implementation complexity and reduce the error rate of data storage through the TPC code cascade BCH code mode because the cascade BCH codes do not occupy too many check bits and the increased calculated amount is small.
Optionally, the two-dimensional TPC codeword matrix is plural, and the two-dimensional TPC codeword matrix corresponds to the one-dimensional TPC code sequence one by one; the second encoding module is used for:
combining a preset number of one-dimensional TPC code sequences;
and performing BCH coding on the one-dimensional TPC code sequences after the merging processing to obtain a coding result corresponding to the data to be stored.
Optionally, the coding result corresponding to the data to be stored includes valid data bits, TPC check bits and BCH check bits.
The encoding device provided by the embodiment of the invention can be used for executing the encoding method embodiment, and the implementation principle and the technical effect are similar, and the embodiment is not repeated here.
Fig. 12 is a schematic structural diagram of a decoding device according to another embodiment of the present invention. As shown in fig. 12, the decoding apparatus 120 includes: a first decoding module 1201, a second arrangement module 1202, a second decoding module 1203 and an output module 1204.
A first decoding module 1201, configured to read encoded data stored in the memory, and perform BCH decoding processing on the encoded data.
A second permutation module 1202, configured to rank the data obtained by the BCH decoding process into a two-dimensional TPC codeword matrix.
And the second decoding module 1203 is configured to perform TPC decoding processing on the two-dimensional TPC codeword matrix to obtain a decoding result corresponding to the encoded data.
And the output module 1204 is used for outputting the decoding result corresponding to the encoded data.
Optionally, the second arrangement module is configured to:
splitting data obtained by BCH decoding into a plurality of one-dimensional TPC code sequences;
for each one-dimensional TPC code sequence, arranging the one-dimensional TPC code sequence into a corresponding two-dimensional TPC code word matrix;
the second coding module is configured to:
and performing TPC decoding processing on each two-dimensional TPC codeword matrix in sequence.
Optionally, the second coding module is configured to:
and decoding the two-dimensional TPC codeword matrix according to a Chase2 soft input soft output serial iterative decoding algorithm.
The decoding device provided by the embodiment of the invention can be used for executing the decoding method embodiment, the implementation principle and the technical effect are similar, and the embodiment is not repeated here.
Fig. 13 is a schematic hardware structure of an encoding device according to an embodiment of the present invention. As shown in fig. 13, the encoding apparatus 130 provided in the present embodiment includes: at least one processor 1301 and a memory 1302. The encoding device 130 further comprises a communication component 1303. The processor 1301, the memory 1302, and the communication unit 1303 are connected via a bus 1304.
In a specific implementation, at least one processor 1301 executes computer-executable instructions stored in the memory 1302, so that the at least one processor 1301 performs the encoding method as described above.
The specific implementation process of the processor 1301 may refer to the above method embodiment, and its implementation principle and technical effects are similar, and this embodiment will not be described herein again.
In the embodiment shown in fig. 13 described above, it should be understood that the processor may be a central processing unit (english: central Processing Unit, abbreviated as CPU), or may be other general purpose processors, digital signal processors (english: digital Signal Processor, abbreviated as DSP), application specific integrated circuits (english: application Specific Integrated Circuit, abbreviated as ASIC), or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in a processor for execution.
The memory may comprise high speed RAM memory or may further comprise non-volatile storage NVM, such as at least one disk memory.
The bus may be an industry standard architecture (Industry Standard Architecture, ISA) bus, an external device interconnect (Peripheral Component, PCI) bus, or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, among others. The buses may be divided into address buses, data buses, control buses, etc. For ease of illustration, the buses in the drawings of the present application are not limited to only one bus or one type of bus.
Fig. 14 is a schematic hardware structure of a decoding device according to another embodiment of the present invention. As shown in fig. 14, the decoding apparatus 140 provided in this embodiment includes: at least one processor 1401, and memory 1402. The decoding device 140 further comprises a communication means 1403. Wherein the processor 1401, the memory 1402 and the communication unit 1403 are connected via a bus 1404.
In a specific implementation, at least one processor 1401 executes computer-executable instructions stored in the memory 1402, so that the at least one processor 1401 performs the decoding method as described above.
The specific implementation process of the processor 1401 may refer to the above-mentioned method embodiment, and its implementation principle and technical effects are similar, and this embodiment will not be described herein again.
In the embodiment shown in fig. 14 described above, it should be understood that the processor may be a central processing unit (english: central Processing Unit, abbreviated as CPU), or may be other general purpose processors, digital signal processors (english: digital Signal Processor, abbreviated as DSP), application specific integrated circuits (english: application Specific Integrated Circuit, abbreviated as ASIC), or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in a processor for execution.
The memory may comprise high speed RAM memory or may further comprise non-volatile storage NVM, such as at least one disk memory.
The bus may be an industry standard architecture (Industry Standard Architecture, ISA) bus, an external device interconnect (Peripheral Component, PCI) bus, or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, among others. The buses may be divided into address buses, data buses, control buses, etc. For ease of illustration, the buses in the drawings of the present application are not limited to only one bus or one type of bus.
The present application also provides a computer-readable storage medium having stored therein computer-executable instructions that, when executed by a processor, implement the encoding method as above.
The computer readable storage medium described above may be implemented by any type of volatile or non-volatile memory device or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk. A readable storage medium can be any available medium that can be accessed by a general purpose or special purpose computer.
An exemplary readable storage medium is coupled to the processor such the processor can read information from, and write information to, the readable storage medium. In the alternative, the readable storage medium may be integral to the processor. The processor and the readable storage medium may reside in an application specific integrated circuit (Application Specific Integrated Circuits, ASIC for short). The processor and the readable storage medium may reside as discrete components in a device.
The present application also provides a computer-readable storage medium having stored therein computer-executable instructions that, when executed by a processor, implement the decoding method as described above.
The computer readable storage medium described above may be implemented by any type of volatile or non-volatile memory device or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk. A readable storage medium can be any available medium that can be accessed by a general purpose or special purpose computer.
An exemplary readable storage medium is coupled to the processor such the processor can read information from, and write information to, the readable storage medium. In the alternative, the readable storage medium may be integral to the processor. The processor and the readable storage medium may reside in an application specific integrated circuit (Application Specific Integrated Circuits, ASIC for short). The processor and the readable storage medium may reside as discrete components in a device.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the method embodiments described above may be performed by hardware associated with program instructions. The foregoing program may be stored in a computer readable storage medium. The program, when executed, performs steps including the method embodiments described above; and the aforementioned storage medium includes: various media that can store program code, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (8)
1. A method of encoding, comprising:
obtaining data to be stored, and performing Turbo Product Code (TPC) coding treatment on the data to be stored to obtain a two-dimensional TPC codeword matrix; the two-dimensional TPC codeword matrix is a plurality of;
arranging the two-dimensional TPC codeword matrix into a one-dimensional TPC code sequence; the two-dimensional TPC codeword matrix corresponds to the one-dimensional TPC code sequence one by one;
combining a preset number of one-dimensional TPC code sequences;
performing BCH coding on the one-dimensional TPC code sequences after the merging processing to obtain a coding result corresponding to the data to be stored;
and writing the coding result corresponding to the data to be stored into a memory.
2. The method of claim 1, wherein the encoding results corresponding to the data to be stored include valid data bits, TPC parity bits, and BCH parity bits.
3. A method of decoding, comprising:
reading encoded data stored in a memory, and performing BCH decoding processing on the encoded data;
splitting data obtained by BCH decoding into a plurality of one-dimensional TPC code sequences;
for each one-dimensional TPC code sequence, arranging the one-dimensional TPC code sequence into a corresponding two-dimensional TPC code word matrix;
performing TPC decoding processing on each two-dimensional TPC codeword matrix in sequence to obtain a decoding result corresponding to the encoded data;
and outputting a decoding result corresponding to the encoded data.
4. An encoding device, comprising:
the first coding module is used for acquiring data to be stored, and performing Turbo Product Code (TPC) coding processing on the data to be stored to obtain a two-dimensional TPC codeword matrix; the two-dimensional TPC codeword matrix is a plurality of;
a first arrangement module, configured to arrange the two-dimensional TPC codeword matrix into a one-dimensional TPC code sequence; the two-dimensional TPC codeword matrix corresponds to the one-dimensional TPC code sequence one by one;
the second coding module is used for carrying out combination processing on a preset number of one-dimensional TPC code sequences; performing BCH coding on the one-dimensional TPC code sequences after the merging processing to obtain a coding result corresponding to the data to be stored;
and the writing module is used for writing the coding result corresponding to the data to be stored into the memory.
5. An encoding apparatus, comprising: at least one processor and memory;
the memory stores computer-executable instructions;
the at least one processor executing computer-executable instructions stored in the memory causes the at least one processor to perform the encoding method of claim 1 or 2.
6. A decoding apparatus, comprising: at least one processor and memory;
the memory stores computer-executable instructions;
the at least one processor executing computer-executable instructions stored in the memory causes the at least one processor to perform the decoding method of claim 3.
7. A computer readable storage medium having stored therein computer executable instructions which, when executed by a processor, implement the encoding method of claim 1 or 2.
8. A computer readable storage medium having stored therein computer executable instructions which when executed by a processor implement the decoding method of claim 3.
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