KR20210001927A - Generalized concatenated error correction coding scheme with locality - Google Patents

Abstract

An operation method of a memory controller for storing data in a memory device according to the technical idea of the present disclosure comprises the steps of: encoding data received from the outside; and storing the encoded data in a memory device. The encoding step includes a step of encoding the received data with two or more sub-codewords. The two or more sub-codewords constitute an outer codeword having a bit size larger than a bit size of at least one sub-codeword. Two or more outer codewords constitute a large codeword having a bit size larger than a bit size of at least one outer codeword. A large codeword corrects an error, which cannot be corrected by the outer codewords.

Description

Generalized concatenation error correction coding method using locality {GENERALIZED CONCATENATED ERROR CORRECTION CODING SCHEME WITH LOCALITY}

The present disclosure relates to error correction coding, in particular, to a generalized concatenation error correction coding method using locality.

Error correction coding has been developed as a method to ensure accurate digital communication in a noisy channel. Since data may be lost or transformed by a noise channel while data is being transmitted, error correction coding may be used to ensure accurate decoding even when some data is lost or transformed.

Recently, error correction coding has been used to store data in memory devices. Since data stored in the memory cell is likely to be lost or deformed before being read, error correction coding may be used to ensure that the correct data is stored in the memory device.

A common method of error correction coding is Reed-Solomon (RS) code. According to this method, a data block may be represented as a set of elements referred to as symbols. A certain number of check symbols may be added to the data so that incorrect or missing symbols may be corrected during data decoding.

Another common method of error correction coding is a Low-Density Parity-Check (LDPC) code. According to this scheme, parity check symbols can be added to the data. Parity check symbols can be generated using a sparse bipartite graph.

In the above-described error correction code schemes, data and check symbols are grouped into strings referred to as codewords. During decoding, the entire codeword should generally be received before the data contained in the codeword is decoded. This can lead to two trade-offs. According to the first trade-off, if the number of check symbols increases, accurate decoding is possible even if a large number of errors occur, and if the number of check symbols decreases, the overhead decreases, so the encoded data in a memory device having a fixed size Can be stored more and faster decoding is possible. According to the second tradeoff, if the length of the codeword is longer, the overhead is lower, so the encoded data can be stored more in the memory device, and more data must be received before the data is decoded. The latency to lead can be increased. Conversely, if the length of the codeword is shortened, the latency may be reduced, but since the overhead increases, the amount of data stored in the memory device decreases, and more computational resources may be required during decoding.

A problem to be solved by the technical idea of the present disclosure is to optimize the trade-off between decoding accuracy and latency by stepwise decoding codewords of different lengths.

In order to achieve the above object, a method of operating a memory controller for storing data in a memory device according to an aspect of the present disclosure includes encoding data received from the outside and storing the encoded data in the memory device. Including, and the encoding step includes the step of encoding the received data into two or more sub-codewords, wherein the two or more sub-codewords are an outer code having a bit size larger than that of at least one sub-codeword A word (outer codeword) is formed, and two or more outer codewords constitute a larger codeword having a bit size larger than at least one outer codeword, and the large codeword cannot be corrected by the outer codeword. One error is corrected.

A method of operating a memory controller for recovering data stored in a memory device includes: reading data stored in the memory device, decoding sub-codewords of the read data, and when sub-codewords of the read data are not decodeable. , Decoding a plurality of outer codewords, and each of the plurality of outer codewords includes two or more non-decodeable sub-codewords.

A method of operating a memory controller for storing data in a memory device according to another aspect of the present disclosure includes encoding data and storing the encoded data in a memory device, wherein the encoding step includes: in a first layer Encoding data into a plurality of sub-codewords, grouping a plurality of sub-codewords into a plurality of outer codewords in a second layer, and a plurality of outer codewords in a third layer, a plurality of outer codewords And grouping the codewords into at least one larger codeword having a bit size larger than that of an outer codeword of any one of the codewords.

In the data storage method and data recovery method according to an exemplary embodiment of the present disclosure, a problem to be solved by the technical idea of the present disclosure is to optimize the trade-off between decoding accuracy and latency by stepwise decoding codewords of different lengths. can do.

1 is a diagram illustrating data grouping according to exemplary embodiments of the present invention.
2 is a diagram illustrating a method of grouping data according to exemplary embodiments of the present invention.
3 is a flowchart illustrating a data encoding and decoding method according to exemplary embodiments of the present invention.
4 is a block diagram illustrating a memory system including a memory according to example embodiments.
5 is an exemplary computing system implementing a method and system in accordance with the present disclosure.

Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

Exemplary embodiments of the present invention may provide methods of encoding data when transmitted through a noise channel. Exemplary embodiments of the present disclosure may provide methods of storing data in a memory device and recovering data in a memory device. Exemplary embodiments of the present invention not only can encode a short codeword using fewer check symbols to lower latency, but also increase data accuracy and use more check symbols to correct more errors. You can also encode codewords. According to exemplary embodiments of the present invention, data may be encoded into short codewords or sub-codewords having relatively few check codewords. Short codewords or sub-codewords can be combined into a longer codeword or codeword group containing additional check symbols. The codeword group may be referred to as an outer codeword. Decoding can be performed as much as possible for short codewords or sub-codewords with few check symbols. If an excess error occurs due to insufficient check symbols and decoding fails due to an excess error, decoding may be performed again for a long codeword or codeword group.

A group of symbols included in short codewords may be referred to as a sub-codeword, and a group of symbols included in long codewords may be referred to as grouped-codewords. The grouped-codeword may be referred to as an outer codeword. Data can be encoded into sub-codewords, and sub-codewords can be decoded locally once all of the sub-codewords are received. Sub-codewords can be combined into a group-codeword. Since group-codewords are received when there are too many errors in a sub-codeword, data to be decoded after all of the group-codewords have been received cannot be accurately decoded even if they are decoded based on the sub-codewords. To reduce latency, data may be decoded when all sub-codewords have been received. However, if the data of a specific sub-codeword cannot be decoded, in order to increase the data accuracy, the data can be decoded when all the group-codewords have been received.

Furthermore, exemplary embodiments of the present invention may group a set of group-codewords into a codeword super-group. The codeword super-group may be referred to as a large codeword. Thus, if data cannot be correctly decoded from a sub-codeword or group-codeword, the data can be decoded after all of the codeword super-groups have been received. In order to increase the likelihood that data is correctly decoded in each step, more check symbols may exist. The codeword super-group can be grouped into the next level by grouping with additional check symbols. If the data cannot be correctly decoded by the codeword super-group, the data can be decoded from the next step group. The number of grouping steps may not be limited. For example, 2, 3, 4, 5, 6 or more grouping steps may be used. However, for clarity of explanation, exemplary embodiments of the present invention include a grouping step in which data is encoded into a sub-codeword, a grouping step in which a sub-codeword is encoded into a group-codeword, and a group-codeword is a codeword. For the grouping step encoded as a super-group, it may be described as adding one or more check symbols in each grouping step.

1 is a diagram illustrating data grouping according to exemplary embodiments of the present invention.

Referring to FIG. 1, data may be encoded into data symbols 11, and a plurality of data symbols 11 may be included in a sub-codeword 13 together with check symbols 12. The sub-codewords 13 may be included in the group-codeword 14 together with the check symbols 12. Accordingly, each sub-codeword 13 may be a symbol included in the group-codeword 14.

The group-codewords 14 may be included in the codeword super-group 15 together with the check symbols 12. Accordingly, each group-codeword 14 may be a symbol included in the codeword super-group 15. Any number of codeword supergroups 15 may be configured in the same manner.

Data can be encoded into data symbols using an appropriate coding scheme. For example, Reed-Solomon (RS) or Bose-Chaudhuri-Hocquenghem (BCH) may be used. That is, when using BCH encoding to encode data into sub-codewords, BCH encoding encodes sub-codewords into group-codewords, and encodes group-codewords into codeword super-groups. Can be used repeatedly.

According to another embodiment of the present invention, data may be encoded according to Reed-Solomon (RS) coding or similar encoding technology through a locally or generically decoding method as described above. have. Further, data may be encoded by grouping a plurality of data RS codes together with one or more redundant RS codes and generating a single parity check matrix for a set of data RS codes and redundancy RS codes.

2 is a diagram illustrating a method of grouping data according to exemplary embodiments of the present invention.

2, data is encoded into a set of primary data RS codes 21, one or more redundant RS codes 22 are grouped together with basic data RS codes 21, and single parity The check matrix 23 may be generated from basic data RS codes 21 and redundancy RS codes 22. In this way, data can be decoded at the RS code level, which is a local level, and if the data cannot be decoded correctly, when the entire set of RS codes (basic data and redundancy data) is received together with the parity check matrix. , Data that cannot be decoded at the local level may be decoded using redundancy data RS codes and a parity check matrix.

3 is a flowchart illustrating a data encoding and decoding method according to exemplary embodiments of the present invention.

Referring to FIG. 3, in S31, data may be received. In S32, the received data may be encoded according to the above-described nested fashions. In S33, the encoded data may be stored in the memory device. Thereafter, data stored in the memory device may be recovered. As part of the recovery, in S34, a first set of symbols may be recovered. In S35, it may be determined whether or not local decoding is successful. If the first set of symbols can only be decoded based on information about the first set of symbols, go to S36, and if the first set of symbols cannot be decoded based only on information about the first set of symbols, Go to S37.

In S36, data may be decoded without waiting for an entire group of sets of symbols to be recovered, and a next set of symbols may be recovered and decoded in the same manner.

In S37, a group of symbol sets including the first set of symbols may be recovered. In S38, after the entire group of symbols is recovered, the first set of symbols and other sets of symbols of the group based on the information on the symbol group of symbols) can be restored. Thereafter, additional data can be recovered and decoded in the same way.

As described above, exemplary embodiments of the present disclosure may encode data to be stored in a memory system and decode data recovered from the memory system.

4 is a block diagram illustrating a memory system including a memory according to example embodiments.

Referring to FIG. 4, the memory system 300 may include a memory controller 400 and a nonvolatile memory device 410.

The nonvolatile memory device 410 may be a flash memory device, a NAND flash memory device, a phase change RAM (PRAM), a ferroelectric RAM (FRAM), a magnetoresistive RAM (MRAM), or the like. However, it is not limited thereto. According to an exemplary embodiment of the present invention, the nonvolatile memory device 410 may include a plurality of NAND flash memory devices. The nonvolatile memory device 410 may have a planar structure or a three-dimensional (3D) memory cell structure having a stack of memory cells.

The nonvolatile memory device 410 may include a memory cell array 415, an X decoder 420, a voltage generator 414, an I/O buffer 417, a page buffer 416, and a control logic 412. have. In addition, the nonvolatile memory device 410 may include an input/output (I/O) pad 411.

The memory cell array 415 may include a plurality of word lines and a plurality of bit lines. Each memory cell included in the memory cell array 415 may be implemented as a nonvolatile memory cell. For example, each memory cell included in the memory cell array 415 may include a charge storage layer such as a floating gate or a charge trapping layer.

The memory cell array 415 may include a plurality of blocks and a plurality of pages. Each block may include a plurality of pages. For example, the first block 418 may include a first group of N-1 pages, the second block 419 may include a second group of N-1 pages, and N is 1 or more. It can be an integer. A page may be a unit of a program operation and a read operation, and a block may be a unit of an erase operation.

The control logic 412 may control the overall operation of the nonvolatile memory device 410. Upon receiving the command CMD from the memory controller 400, the control logic 412 interprets the command CMD and operates according to the interpreted command CMD (for example, a program operation, a read operation, a read retry operation, or an erase operation). The nonvolatile memory device 410 may be controlled to perform this operation.

The X decoder 420 is controlled by the control logic 412 and may drive at least one of word lines included in the memory cell array 415 according to a row address.

The voltage generator 414 is controlled by the control logic 412, generates one or more voltages required for a program operation, a read operation, or an erase operation, and provides the generated voltages to one or more columns selected by the X decoder 420. I can.

The page buffer 416 is controlled by the control logic 412 and may operate as a sense amplifier or a write driver according to an operation mode (eg, a read operation or a program operation).

The I/O pad 411 and the I/O buffer 417 operate as an I/O path for data exchanged between an external device (for example, the memory controller 400 or host) and the nonvolatile memory device 410 can do.

The memory controller 400 includes a microprocessor 401, a read-only memory (ROM) 403, a random access memory (RAM) 402, an encoder 404, and a decoder 405. ), a memory interface 406 and a bus 407. Components 401 to 406 included in the memory controller 400 may be electrically connected to each other through a bus 407.

The microprocessor 401 may control the overall operation of the memory system 300 including the memory controller 400. The microprocessor 401 may be a circuit that controls other components by generating a control signal. When power is supplied to the memory system 300, the microprocessor 401 drives the firmware stored in the ROM 403 on the RAM 402 to operate the memory system 300, and the overall operation of the memory system 300 Can be controlled. According to at least one exemplary embodiment, the microprocessor 401 includes other components of the memory controller 400, for example, the ROM 403, the RAM 402, the encoder 404, the decoder 405, A command may be issued to control the operation of at least one of the memory interface 406 and the bus 407. According to at least one exemplary embodiment, operations performed by the memory controller 400 may be performed by the microprocessor 401 or may be performed under control of the microprocessor 401. According to at least one exemplary embodiment, the operations performed by the memory controller 410 are included in the program code stored in the ROM 403 and are performed by the microprocessor 401 executing instructions corresponding to the operations. Or it may be performed under the control of the microprocessor 401.

The driving firmware code of the memory system 300 may be stored in the ROM 403, but is not limited thereto. The Permuair code may be stored in a portion of the nonvolatile memory device 410. Accordingly, the control or intervention of the microprocessor 401 may include direct control of the microprocessor 401 as well as the intervention of firmware, which is software driven by the microprocessor 401.

The RAM 402, which is a memory acting as a buffer, may store an initial command received from the host or microprocessor 401, data, and various variables, or data output from the nonvolatile memory device 410. The RAM 402 may store data, various parameters, and variables output to the nonvolatile memory device 410 or received from the memory device 410.

The memory interface 406 may operate as an interface between the memory controller 400 and the nonvolatile memory device 410. The memory interface 406 is connected to the I/O pad 411 of the nonvolatile memory device 410 and may exchange data with the I/O pad 411. Furthermore, the memory interface 406 may generate a command suitable for the nonvolatile memory device 410 and provide the generated command to the I/O pad 411 of the nonvolatile memory device 410. The memory interface 406 may provide a command to be executed by the nonvolatile memory device 410 and an address (address, ADD) of the nonvolatile memory device 410.

According to at least one exemplary embodiment, the decoder 405 is an error correcting code (ECC) decoder that decodes data according to the above-described method, and the encoder 404 encodes data according to the above-described method. It may be an ECC encoder. According to at least one exemplary embodiment, the decoder 405 and the encoder 404 may perform error bit correction according to the above-described method. The encoder 404 may generate data to which one or more parity bits or redundancy bits are added by performing error correction encoding on data before the data is provided to the nonvolatile memory device 410. One or more parity bits or redundancy bits may be stored in the nonvolatile memory device 410.

The decoder 405 may perform error correction decoding on the output data, determine whether error correction decoding has been successfully performed based on a result of the error correction decoding, and output a command signal based on the determination result. The read data is transmitted to the decoder 405, and the decoder 405 may correct error bits in the data using one or more parity bits or redundancy bits. When the number of error bits exceeds the correctable limit error bits, the decoder 405 may decode according to a higher level of data organization, as described above. In an exemplary embodiment, the encoder 404 and the decoder 405 may perform error correction using a method of modifying the Bose-Chaudhuri-Hocquenghem (BCH) adjusted to operate as described above.

Exemplary embodiments of the present invention may use a method of modifying BCH called Super Bose-Chaudhuri-Hocquenghem (SBCH). The SBCH may be a multilevel algebraic code composed of BCH codes, which are short binary codes, and Reed-Solomon (RS) codes instead of binary codes. In the message-passing decoding algorithm of low density parity check (LDPC) codes, a large amount of soft information needs to be repeatedly exchanged between variables and check nodes, whereas SBCH code In its decoding algorithm, it is entirely algebraic by using standard algebraic decoding modes for short BCH and RS codes. Therefore, the power consumption of the SBCH decoder is very small compared to the power consumption of the LDPC decoder.

이고, 길이가

인 리드-솔로몬(Reed-Solomon, RS) 코드들은

일 수 있다. 위 코드들과 관련된 SBCH 코드는 모든 이진 매트릭스

일 수 있다. 여기서, 모든 i에 대해

이고, 모든 j=1,...,L에 대해

일 수 있다. 여기서,

는 소위 델타 신드롬(delta syndromes)으로 지칭될 수 있다.According to the SBCH scheme, binary codes of length n are

And the length is

In Reed-Solomon (RS) codes

Can be SBCH codes related to the above codes are all binary matrices

Can be Where, for all i

And for all j=1,...,L

Can be here,

Can be referred to as so-called delta syndromes.

According to exemplary embodiments of the present disclosure, RS codes may glue rows of codewords. In order to properly use RS codes in the decoding process, it is possible to access all of the received words. However, as described above, exemplary embodiments of the present invention may perform partial decoding. The frame error rate (FER) may decrease as larger chunks of received words are accessed.

10^-11로 디코딩될 수 있다. 1/4 블록의 디코딩이 실패하는 경우, 완전한 4KB 블록이 리드될 수 있다.According to example embodiments of the present disclosure, partial decoding may be performed through locality. For example, if the block length is 4 KB, 1 KB ("1/4 block") is decoded as FER10 ^-3 , and a complete 4 KB block is FER

It can be decoded as 10 ^-11 . If the decoding of the 1/4 block fails, a complete 4KB block can be read.

In this way, the latency can be reduced with a substantially high probability. As described above, this method can be implemented by gluing the rows of SBCH words with an external RS code. In order to obtain locality, RS codes can be replaced with codes having locality. Due to locality, each group of rows may be glued locally. Thus, various words included in a group of rows can help each other by using the locality of local codes replacing the RS code, without using rows not included in the group. However, certain groups of rows may still be linked by global dependencies of local codes. Thus, when decoding for a local group fails, successful decoding can be performed by accessing all rows.

As described above, exemplary embodiments of the present invention can be classified into several embodiments. For example, Example 1 (A1) and Example 2 (A2) may be provided. These two embodiments can describe two optional algorithms that can be used to implement the present invention.

은

의 서로 다른 0이 아닌 구성요소들(distinct nonzero 디드순)이고,

은 K의 구별될 필요가 없는 0이 아닌 구성요소들이다. F에 대한 일반화된 리드-솔로몬(Generalized Reed-Solomon, GRS) 코드는 패리티-체크 매트릭스

를 갖는 선형

코드 C이다.According to Example 1 (A1), q is the power of a prime,

silver

Are different non-zero components of (distinct nonzero order),

Are non-zero components of K that need not be distinguished. The generalized Reed-Solomon (GRS) code for F is the parity-check matrix.

Linear with

Code C.

이고, H는 RS에서 [수학식 1]과 같이 정의될 수 있다.here,

And H may be defined as in [Equation 1] in RS.

을 갖는 MDS일 수 있다. r이 정수이고,

일 때, 최종적인 GRS 코드는

로 표현될 수 있다. 체크 매트릭스

는 [수학식 2]와 같이 정의될 수 있다.The final code is the minimum distance

It may be an MDS having. r is an integer,

When, the final GRS code is

It can be expressed as Check matrix

Can be defined as in [Equation 2].

는,

및 F의 0이 아닌 서로 다른 구성요소들인

을 만족하도록, 양의 정수 파라미터들인 q,

,

, b, c를 결정함으로써 정의될 수 있다.

이고,

인 i에 대해

일 수 있다. 따라서,

이다.

의 구성요소들은

에 포함된다.

인 i에 대해 [수학식 3] 내지 [수학식 6]과 같이 정의될 수 있다. Code definition. Linear code

Is,

And the non-zero components of F

To satisfy, positive integer parameters q,

,

It can be defined by determining, b, c.

ego,

About i

Can be therefore,

to be.

The components of

Included in

For i, it may be defined as [Equation 3] to [Equation 6].

는 a+b 에러를 정정할 수 있는

에 대한 RS의 체크 매트릭스일 수 있다.here,

A+b error can be corrected

It may be a check matrix of RS for.

에 대하여, [수학식 7]과 같이 정의될 수 있다.to the next,

With respect to, it can be defined as [Equation 7].

는

에 대하여, 또는

인 경우

에 대하여,

이고,

일 수 있다.here,

Is

Against, or

If

about,

ego,

Can be

에 대하여, [수학식 8]과 같이 정의될 수 있다.

With respect to, it can be defined as in [Equation 8].

이면

이고,

이므로,

일 수 있다.In other words,

Back side

ego,

Because of,

Can be

이고, 수신 워드(received word)는

일 수 있다. 디코더는 각 서브-간격(sub-interval)

마다 표준 RS 디코딩 방식(standard RS decoding method)을 적용할 수 있다. 디코더는 각 서브-간격(sub-interval)

마다

를 만족하는 i개의 에러와 j개의 소거(erasure)의 조합을 정정할 수 있다. 정정이 수행될 때, 서브-간격들 중 일부에서 모든 에러들을 초기화(clear)될 수 있다. 결과 워드(resulting word)는

일 수 있다.

이므로, RS 디코더는

를 만족하는 i개의 잔여 에러(remaining errors)와 j개의 잔여 소거(remaining erasures)의 조합을 정정하기 위해 z를 적용할 수 있다. 이는 하나의 서브-워드 이외의 모든 서브-워드들이 제1 단계(first round)에 디코딩되고, 디코딩되지 않은 하나의 서브-워드에 포함된 에러의 개수가 b+c를 초과하지 않는 경우 효과적일 수 있다. decoding. The transmitted word is

And the received word is

Can be Decoder each sub-interval

Each standard RS decoding method can be applied. Decoder each sub-interval

each

It is possible to correct a combination of i errors and j erasures satisfying the. When correction is performed, all errors can be cleared in some of the sub-intervals. The resulting word is

Can be

So, the RS decoder

Z can be applied to correct the combination of i remaining errors and j remaining erasures satisfying. This may be effective when all sub-words other than one sub-word are decoded in a first round, and the number of errors included in one undecoded sub-word does not exceed b+c. have.

의 그룹은

코드워드가 될 수 있다. 코드의

계열(family)에 대한 설명은 후술된다.

계열에서, RS는 내부 코드(inner code)와 외곽 코드(outer code) 모두에서 사용될 수 있다.As described above, in Example 2 (A2),

Group of

It can be a codeword. Of code

A description of the family will be described later.

In the series, RS can be used in both an inner code and an outer code.

는

에 대한 선형 코드 C일 수 있다.

는 소수 거듭제곱인 q, 양의 정수들인 T, J, m, 정수열(integer sequence)

, 체크 매트릭스들인

에 의해 결정될 수 있다. C는 내부 코드(internal codes)인

를 포함하고, 여기서,

이고,

이다.

Is

May be a linear code C for

Is a decimal power q, positive integers T, J, m, integer sequence

, Check matrices

Can be determined by C is the internal codes

Including, where,

ego,

to be.

에 관한 x의 첫 t개의 신드롬들이 0이 되는 것은

에 대한 조건일 수 있다. 실질적으로,

는 t개의 에러를 정정할 수 있는 BCH 또는 t/2개의 에러를 정정할 수 있는 RS일 수 있다. 코드워드

는

일 수 있다. 여기서,

이고,

는

에 포함될 수 있다. 즉,

는 확장 필드

에 대한 RS 워드이고, 길이가 J이고 차원이 J-R(t)일 수 있다. 이 RS 코드는

를 만족하는 i개의 에러과 j개의 소거의 조합을 정정할 수 있다.

는 리던던시를 위해 R(t) K-심볼을 갖고, 이는 일반적으로 일반적으로 코드 C의 리던던시를 위해

개의 심볼을 필요로 한다. 따라서, 전체적인 리던던시는 F에 대해

개의 심볼들일 수 있다.

The first t syndromes of x about become 0

May be a condition for realistically,

May be a BCH capable of correcting t errors or an RS capable of correcting t/2 errors. Codeword

Is

Can be here,

ego,

Is

Can be included in In other words,

Is an extended field

Is an RS word for, length J and dimension JR(t). This RS code is

It is possible to correct a combination of i errors and j erasures satisfying.

Has an R(t) K-symbol for redundancy, which is generally used for redundancy in code C.

It requires two symbols. Therefore, the overall redundancy is

It may be a number of symbols.

워드인

각각이 높은 확률로 자립형 방식(standalone manner)으로 디코딩되도록

를 함께 그룹화할 수 있다. 그러나, 전체 그룹에 추가적인 리던던시를 부가함으로써,

를 포함하는 더 큰 코드워드가 형성될 수 있고, 디코딩 성공 확률이 더 높아질 수 있다. 추가된 리던던시는 코드워드들의 일부 정보 심볼들을 대체할 수 있다.Thus, exemplary embodiments of the present invention,

Word Inn

So that each is decoded in a standalone manner with a high probability

Can be grouped together. However, by adding additional redundancy to the entire group,

A larger codeword including a may be formed, and a decoding success probability may be higher. The added redundancy can replace some information symbols of codewords.

각각을 분리 디코딩(separate decoding)할 수 있다. 그룹 내 디코딩될 수 없는

에 대한 일부 GCC 워드들의 경우, 표준 RS 디코더가

에 대한 t개의 RS-코드워드, 즉

(

로 상술됨)에 적용될 수 있다.

에 대한 임의의

에 대한 디코딩이 실패하는 경우, 국부적(local) RS에 의해 보조되는 디코딩 방식이 사용될 수 있다. 예를 들어, RS 워드의 그룹인

에 대한 디코딩을 완료하기 위하여 상술한 두 가지 방식 중 어느 하나가 사용될 수 있다.This decoding method is an individual GCC codeword

Each can be separately decoded. Cannot be decoded within the group

For some GCC words for, the standard RS decoder

T RS-codewords for

(

Can be applied to).

For random

If the decoding for is failed, a decoding scheme assisted by a local RS may be used. For example, a group of RS words

Any one of the above two methods may be used to complete the decoding for.

의 각 컴포넌트 코드워드를 개별적으로(separate) 디코딩하는 제2 단계(second round)에 추가되는 리던던시로서 기여할 수 있다.In another embodiment, when some of the component GCC words fail to be decoded in the first round, as described above, the decoded words are a group that is not decoded in the first round.

It may contribute as a redundancy added to a second round of decoding each component codeword of'separately'.

The present invention may be based on an Error Correction Code (ECC). In ECC technology, finite integer r=2, 3?? And a finite algebraic field F, and each symbol of F may include r bits. The [n k] linear code C is associated with a k'n parity check matrix whose entries are within F. Here, n and k may be positive integers, n may be greater than k, n may be a code length of a symbol, and k may be a code dimension. The codeword of C is a vector for n symbols for F, and the product of the parity check matrix and the vector may be 0.

For ease of explanation, a word may mean any vector of n symbols for F. The syndrome for a specific word may mean a scalar product of a row of a parity check matrix and a word. The first syndrome for a specific word may be a scalar product of the first row of the parity check matrix and the word. The second syndrome for a specific word may be a scalar product of the second row of the parity check matrix and the word. If the decoder acquires more syndromes, more errors can be corrected.

이라고 지칭될 수 있다. 각 서브-워드로부터 제2 신드롬이 수집될 때 동일한 방식이 적용될 수 있고, 수집된 코드워드는

일 수 있다. 실제적으로,

은 보통 제로 워드(zero word)이고, 이러한 RS 워드들의 코드 레이트는 증가할 수 있다.A key feature of the GCC code is that several small codewords (eg, BCH codes) sharing the same parity check matrix are grouped together, and each group may be referred to as a sub-word. Several codewords may be grouped in such a way that a codeword is formed in RS when the first syndrome is collected from each sub-word. This codeword is

May be referred to as. The same method can be applied when the second syndrome is collected from each sub-word, and the collected codeword is

Can be Practically,

Is usually a zero word, and the code rate of these RS words can increase.

(i) The GCC encoding process can be started by adding redundancy r bits when all syndromes for all small words are the same as any of the aforementioned symbols.

워드들을 케스케이딩(cascading)하는 추가적인 구조가 형성되도록 (i)을 사용할 수 있다. 이 방법은 디코딩될 수 없는 개별적인 GCC 워드가 발생하는 상황에서 유리하고, 디코딩될 수 없는 개별적인 GCC 워드가 그룹 내의 다른 GCC 워드와 협력함으로써 제2 단계(the second round)에서 대부분의 경우 성공적으로 디코딩될 수 있다.(ii) Further, some GCC words are grouped together and for t=1, 2, 3?? from each GCC codeword to generate a larger codeword.

(I) can be used to form an additional structure for cascading words. This method is advantageous in situations in which individual GCC words that cannot be decoded occur, and individual GCC words that cannot be decoded will in most cases be successfully decoded in the second round by cooperating with other GCC words in the group. I can.

Example of (ii). In the following simplified example, there are two GCC words, and each GCC word may include three small sub-codewords and three syndrome layers.

Syndromes associated with the first GCC word GCC_word_1 are as follows.

Syndromes associated with the second GCC word (GCC_word_2) are as follows.

이고,

이고,

은 RS 워드인

이고,

은 RS 워드인

일 수 있다. 나아가, 위 2개의 RS 워드들이 케스케이드되는 경우, 결과는 다음과 같다.In the example above,

ego,

ego,

Is the RS word

ego,

Is the RS word

Can be Furthermore, when the above two RS words are cascaded, the result is as follows.

은 RS 워드인

이고,

은 RS 워드인

일 수 있다. 위 2개의 RS 워드들이 케스케이드되는 경우, 결과는 다음과 같다.The above result may also be a codeword. Likewise,

Is the RS word

ego,

Is the RS word

Can be When the above two RS words are cascaded, the result is as follows.

The above result may also be a codeword.

Technically implemented, in general a GCC word may contain more sub-codewords and syndromes. Thus, for all parameters, the simplified example above is just an example.

Part (ii) may contain the main features of the present invention. Embodiment 1 (A1) and Embodiment 2 (A2) can be described as follows.

의 그룹은 더 큰 RS 워드가 될 수 있고, 실시 예2(A2)에서,

의 그룹은

코드워드가 될 수 있다.(iii) In Example 1 (A1),

The group of can be a larger RS word, and in embodiment 2 (A2),

Group of

It can be a codeword.

5 is an exemplary computer system implementing a method and system according to the present disclosure.

The method and system according to the present disclosure may be implemented in the form of a software application running on a computer system such as a main frame, a personal computer (PC), a handheld computer, and a server. The software application can be locally accessed by a computer system and stored on a recording medium that can be accessed via a hard wire or wireless connection to a network such as a local area network or the Internet.

The computer system referred to as the system 1000 includes, for example, a central processing unit (CPU) 1001, a random access memory (RAM) 1004, a printer interface 1010, and a display unit. (1011), a local area network (LAN) data transfer controller 1005, a LAN interface 1006, a network controller 1003, an internal bus 1002, and one or more such as a keyboard and a mouse. Input devices 1009 may be included. As shown, the system 1000 may be connected to a data storage device such as a hard disk 1008 through a link 1007.

The exemplary embodiments are provided for explanation, and various modifications may be made within the scope of the appended claims. For example, elements and features for the various exemplary embodiments may be replaced with or combined with each other within the scope of the disclosure and appended claims.

Claims (20)

A method of operating a memory controller for storing data in a memory device, comprising:
Encoding data received from the outside; And
Storing the encoded data in the memory device; Including,
The encoding step,
Encoding the received data into two or more sub-codewords; Including,
The two or more sub-codewords constitute an outer codeword having a bit size larger than that of at least one sub-codeword,
Two or more of the outer codewords constitute a larger codeword having a bit size larger than that of at least one outer codeword,
The large codeword, characterized in that for correcting an error that cannot be corrected by the outer codeword. The method of claim 1, wherein the large codeword,
A method comprising more redundancy data than the outer codeword. The method of claim 1, wherein the large codeword,
A method, characterized in that it is a Generalized Concatenated Code (GCC) codeword. The method of claim 1,
Each of the two or more sub-codewords,
It is a Generalized Concatenated Code (GCC) codeword,
The outer codeword and the large codeword,
Reed-Solomon (Reed-Solomon, RS) method, characterized in that the codeword. The method of claim 1,
The two or more sub-codewords represent a first layer of encoding,
The outer codeword represents a second layer of the encoding,
The large codeword represents a third layer of the encoding,
The first to third layers are codewords having different bit sizes. The method of claim 5,
A matrix including rows of a first group among the rows of the parity-check matrix of the large codeword,
And cascaded parity-check matrices of the plurality of outer codewords. The method of claim 1,
A plurality of layers are formed by the two or more sub-codewords being composed of outer codewords of different bit sizes,
Outer codewords corresponding to each layer among the plurality of layers are generalized concatenated code (GCC) codewords. A method of operating a memory controller for recovering data stored in a memory device, comprising:
Reading data stored in the memory device;
Decoding sub-codewords of the read data; And
If the sub-codewords of the read data cannot be decoded, decoding a plurality of outer codewords; Including,
Wherein each of the plurality of outer codewords includes two or more of the sub-codewords that cannot be decoded. The method of claim 8, wherein the plurality of outer codewords,
And constructing a larger codeword having a bit size larger than one of the plurality of outer codewords. The method of claim 9, wherein the large codeword,
And more redundancy data than the plurality of outer codewords. The method of claim 9, wherein the large codeword,
A method, characterized in that it is a Generalized Concatenated Code (GCC) codeword. The method of claim 9, wherein the two or more sub-codewords,
It is a Generalized Concatenated Code (GCC) codeword,
The plurality of outer codewords and the large codeword,
Reed-Solomon (Reed-Solomon, RS) method, characterized in that the codeword. The method of claim 9,
The two or more sub-codewords represent a first layer of encoding,
The plurality of outer codewords represent a second layer of the encoding,
The first to third layers are codewords having different bit sizes. The method of claim 13,
A matrix including rows of a first group among the rows of the parity-check matrix of the large codeword,
And a cascaded parity-check matrices of the plurality of codewords. The method of claim 9,
A plurality of layers are formed by the two or more sub-codewords being composed of outer codewords of different bit sizes,
Outer codewords corresponding to each layer among the plurality of layers are generalized concatenated code (GCC) codewords. A method of operating a memory controller for storing data in a memory device, comprising:
Encoding the data; And
Storing the encoded data in the memory device; Including,
The encoding step,
Encoding the data into a plurality of sub-codewords in a first layer;
Grouping the plurality of sub-codewords into a plurality of outer codewords having a bit size larger than that of any one of the plurality of sub-codewords in a second layer; And
And grouping the plurality of outer codewords into at least one larger codeword having a bit size larger than that of any one of the plurality of outer codewords in a third layer. How to do it. The method of claim 16, wherein the at least one large codeword,
And more redundancy data than the plurality of outer codewords. The method of claim 16, wherein the matrix including the rows of the first group among the rows of the parity-check matrix of the large codeword,
And a cascaded parity-check matrices of the plurality of codewords. The method of claim 16,
A plurality of layers are formed by the two or more sub-codewords being composed of outer codewords of different bit sizes,
Outer codewords corresponding to each layer among the plurality of layers are generalized concatenated code (GCC) codewords. The method of claim 16,
Reading data stored in the memory device;
Individually decoding the sub-codewords of read data; And
And decoding the plurality of outer codewords including the sub-codewords, which cannot be individually decoded, if any one of the sub-codewords is non-decodeable.

Images