KR20160070362A - Laminated ceramic electronic component - Google Patents

Laminated ceramic electronic component Download PDF

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Publication number
KR20160070362A
KR20160070362A KR1020140177190A KR20140177190A KR20160070362A KR 20160070362 A KR20160070362 A KR 20160070362A KR 1020140177190 A KR1020140177190 A KR 1020140177190A KR 20140177190 A KR20140177190 A KR 20140177190A KR 20160070362 A KR20160070362 A KR 20160070362A
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South Korea
Prior art keywords
electrode
ceramic body
internal electrode
internal
length
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KR1020140177190A
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Korean (ko)
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KR102048102B1 (en
Inventor
정진만
이병화
나은상
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삼성전기주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H01G4/2325—Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)

Abstract

The present disclosure relates to a ceramic body comprising a plurality of dielectric layers, the ceramic body having a first side and a second side at both longitudinal ends; A capacitor formed on the ceramic body so as to face each other with the dielectric layer interposed therebetween, and first and second internal electrodes exposed on the first surface and the second surface, respectively; A third internal electrode disposed above the capacitance forming portion and exposed to the first surface; A fourth internal electrode disposed below the capacitance forming portion and exposed to the second surface; A first outer electrode extending from the first surface to a portion of an upper surface of the ceramic body, the first outer electrode being connected to the first inner electrode and the third inner electrode; And a second external electrode extending from the second surface to a portion of a lower surface of the ceramic body, the second external electrode being connected to the second internal electrode and the fourth internal electrode.

Description

[0001] Laminated ceramic electronic component [0002]

This disclosure relates to a multilayer ceramic electronic component.

2. Description of the Related Art In recent years, with the trend toward miniaturization of electronic products, multilayer ceramic electronic components are also required to be miniaturized and increased in capacity.

Thus, when the micro-layered ceramic electronic part is manufactured, the length and width of the external electrode band become small, and finally, it becomes difficult to form a via at the time of mounting on the substrate.

To solve this problem, an external electrode band is formed on the upper and lower surfaces of the ceramic body.

In order to form an external electrode band on the upper and lower surfaces of the ceramic body, a dipping process is used, but another method is needed to improve the connection of the external electrodes.

Korean Patent Publication No. 2011-0101910

The present disclosure intends to provide a multilayer ceramic electronic device having a structure capable of eliminating a dipping process in forming an external electrode.

A multilayer ceramic electronic device according to an embodiment of the present disclosure includes a ceramic body including a plurality of dielectric layers and having a first surface and a second surface at both ends in the longitudinal direction; A capacitor formed on the ceramic body so as to face each other with the dielectric layer interposed therebetween, and first and second internal electrodes exposed on the first surface and the second surface, respectively; A third internal electrode disposed above the capacitance forming portion and exposed to the first surface; A fourth internal electrode disposed below the capacitance forming portion and exposed to the second surface; A first outer electrode extending from the first surface to a portion of an upper surface of the ceramic body, the first outer electrode being connected to the first inner electrode and the third inner electrode; And a second external electrode extending from the second surface to a portion of a lower surface of the ceramic body and connected to the second internal electrode and the fourth internal electrode.

Since the third and fourth internal electrodes are formed on the upper and lower portions of the capacitance forming portion of the electronic component according to one embodiment of the disclosure, the present invention has a structure capable of eliminating the dipping process in forming the external electrodes.

1 shows a schematic cross-sectional view of a multilayer ceramic electronic component according to an embodiment of the present disclosure.
Fig. 2 shows a schematic cross-sectional view of a multilayer ceramic electronic component according to another embodiment of the present disclosure.

The embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. Accordingly, the shapes and sizes of the elements in the drawings may be exaggerated for clarity of description, and the elements denoted by the same reference numerals in the drawings are the same elements.

Hereinafter, for the sake of clarity, the multilayer ceramic capacitor among the multilayer ceramic electronic components will be mainly described.

1 shows a schematic cross-sectional view of a multilayer ceramic electronic component according to an embodiment of the present disclosure.

Referring to FIG. 1, a multilayer ceramic electronic device according to an embodiment of the present disclosure includes a ceramic body 10 and external electrodes 31 and 32.

The ceramic body 10 is not particularly limited and may have, for example, a rectangular parallelepiped shape.

Meanwhile, in the multilayer ceramic capacitor of the present embodiment, 'longitudinal direction' is defined as 'L' direction in FIG. 1, and 'thickness direction' is defined as T direction. Here, the 'thickness direction' can be used in the same concept as the stacking direction of the dielectric layers, that is, the 'lamination direction'.

Both end portions in the longitudinal direction of the ceramic body 10 are referred to as a first surface 1 and a second surface 2, respectively.

The ceramic body 10 includes a capacitance forming portion in which the first and second internal electrodes 21 and 22 are formed and a cover portion disposed in the upper and lower portions of the capacitance forming portion.

The capacitance forming portion and the cover portion are formed by laminating the dielectric layer 11.

The internal electrodes 21, 22, 23, and 24 are printed on the dielectric layer 11, and the ceramic body 10 is formed by stacking, pressing, and firing the internal electrodes.

The dielectric layer 11 in the ceramic body 10 is integrated so that the boundaries can not be confirmed.

The first and second internal electrodes 21 and 22 are not particularly limited and may be made of a noble metal material such as palladium (Pd), a palladium-silver (Pd-Ag) alloy, The conductive paste may be formed using at least one of the conductive paste.

The first internal electrode 21 is exposed to the first surface 1 and can be electrically connected to the first external electrode 31 and the second internal electrode 22 is exposed to the second surface 2, And may be electrically connected to the second external electrode 32.

And the third and fourth internal electrodes 23 and 24 are respectively disposed on the cover portions located on the upper and lower portions of the capacitance forming portion.

The third and fourth internal electrodes 23 and 24 may be formed as a plurality of as required.

For example, the third inner electrode 23 is located on the cover portion and exposed to the first surface 1, and the fourth inner electrode 24 is located on the cover portion and exposed to the second surface 2 have.

The third internal electrode 23 and the fourth internal electrode 24 do not face each other with the dielectric layer 11 interposed therebetween and do not contribute to the formation of the capacitor capacitance.

The first outer electrode 31 may be disposed on the first surface 1 and extended to the upper surface of the ceramic body 10.

That is, the first external electrode 31 may be arranged to connect the first and third internal electrodes 21 and 23.

The first external electrode 31 may be formed using electroless plating.

Generally, a dipping process is required to form the external electrode. However, in the multilayer ceramic electronic device according to an embodiment of the present disclosure, the third internal electrode 23 is formed by the electroless plating of the first external electrode 31 It does not require an additional dipping step because it acts as a connection terminal.

Therefore, it is possible to reduce the cost of the process and to form the external electrode precisely at a desired portion as compared with the dipping process.

The second external electrode 32 may be disposed on the first surface 2 and extended to the lower surface of the ceramic body 10.

That is, the second external electrode 32 may be arranged to be connected to the second and fourth internal electrodes 22 and 24.

The second external electrode 32 may also be formed using electroless plating.

In general, in order to form the external electrode, a dipping process is required. However, in the multilayer ceramic electronic device according to the embodiment of the present disclosure, the fourth internal electrode 24 is formed by the second external electrode 32 by electroless plating It does not require an additional dipping step because it acts as a connection terminal.

Therefore, it is possible to reduce the cost of the process and to form the external electrode precisely at a desired portion as compared with the dipping process.

1, the first outer electrode 31 may be extended only to the upper surface of the ceramic body 10 and the second outer electrode 32 may be extended only to the lower surface of the ceramic body 10 have.

Table 1 below shows the occurrence of defects in the electroless plating process depending on the distances d1 and d2 between the first internal electrode (second internal electrode) and the third internal electrode (fourth internal electrode) which are adjacent to each other .

d1, d2 Bad occurrence 5 탆 Unplated occurrences 4 탆 Good 3 ㎛ Good 2 탆 Good 1 ㎛ Good

The third internal electrode 23 is formed to have a distance d1 to the adjacent first internal electrode 21 so that the third and fourth internal electrodes 23 and 24 serve as connection terminals in the electroless plating process. And the distance d2 to the adjacent second internal electrode 22 of the fourth internal electrode 24 should be 1 占 퐉 or more and 4 占 퐉 or less.

The lower limit of d1 (d2) is a limit according to the thickness of the dielectric layer 11, and when d1 (d2) is larger than 4 m, there is a problem that unplating occurs without forming external electrodes.

Assuming that the length of the first internal electrode 21 is L1, the length of the second internal electrode 22 is L2, the length of the third internal electrode 23 is L3, and the length of the fourth internal electrode 24 is L4 , L3 / L1 is 0.9 to 1.05, and L4 / L2 is 0.9 to 1.05.

The internal electrodes 21 and 22 included in the capacitance forming portion are formed so as to have the maximum area as long as a short circuit does not occur in the dielectric layer in order to secure a large capacitance. Therefore, if the lengths L3 and L4 of the third internal electrode 23 or the fourth internal electrode 24 exceed 1.05 times the length of the first internal electrode 21 or the second internal electrode 22, The probability of occurrence is very high.

On the contrary, when the lengths L3 and L4 of the third internal electrode 23 or the fourth internal electrode 24 are less than 0.95 times the length of the first internal electrode 21 or the second internal electrode 22, A step may be generated at the time of pressing during the manufacturing process of the main body 10, which may cause cracks.

Table 2 below shows the occurrence of defects according to the lengths (B1, B2) of the external electrode bands located on the upper or lower surface of the ceramic body and the length (A) of the multilayer ceramic electronic component.

A B1 (B2) B1 (B2) / A Bad occurrence 600 탆 310 탆 0.517 Poor chip tear (100%) 600 탆 320 탆 0.533 Chip Tear Failure (300%) 600 탆 330 탆 0.550 Good 600 탆 340 탆 0.567 Good 600 탆 350 탆 0.583 Good 600 탆 380 m 0.633 Good 600 탆 410 탆 0.683 Good 600 탆 440 탆 0.733 Good 600 탆 470 탆 0.783 Good 600 탆 500 탆 0.833 Good 600 탆 530 탆 0.883 Good 600 탆 560 탆 0.933 Good 600 탆 570 탆 0.950 Good 600 탆 580 탆 0.967 Short circuit failure 600 탆 590 탆 0.983 Short circuit failure

The length of the ceramic body 10 is denoted by A and the length of the first external electrode 31 on the top surface of the ceramic body 9 is denoted by B1 in order to prevent occurrence of defects. Electrode 932) on the bottom surface of the ceramic body 10 is B2, the following equation can be satisfied.

0.55? B1 / A? 0.95 - (1)

0.55? B2 / A? 0.95 - (2)

As shown in the formulas (1) and (2), when B1 / A (B2 / A) is less than 0.55, the external electrode can not support the ceramic body 1,

On the other hand, when B1 / A (B2 / A) is more than 0.95, the first and second external electrodes 31 and 32 may be short-circuited.

Fig. 2 shows a schematic cross-sectional view of a multilayer ceramic electronic component according to another embodiment of the present disclosure.

2, in the multilayer ceramic electronic device according to another embodiment of the present disclosure, the first seed layer 33 is disposed between the upper surface of the ceramic body 10 and the first external electrode 31, The second seed layer 33 may be disposed between the lower surface of the main body 10 and the second external electrode 32.

The first seed layer 33 and the second seed layer 34 may be formed of the same material as that of the inner electrode. When the electroless plating process is performed to form the outer electrode, the outer electrode So as to induce elongation.

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited only by the appended claims. It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. something to do.

10: Ceramic body
11: dielectric layer
21, 22, 23, 24: internal electrodes
31, 32: external electrodes
33, 34: seed layer

Claims (8)

A ceramic body including a plurality of dielectric layers, the ceramic body having a first surface and a second surface at both longitudinal ends;
A capacitor formed on the ceramic body so as to face each other with the dielectric layer interposed therebetween, and first and second internal electrodes exposed on the first surface and the second surface, respectively;
A third internal electrode disposed above the capacitance forming portion and exposed to the first surface;
A fourth internal electrode disposed below the capacitance forming portion and exposed to the second surface;
A first outer electrode extending from the first surface to a portion of an upper surface of the ceramic body, the first outer electrode being connected to the first inner electrode and the third inner electrode; And
And a second external electrode extending from the second surface to a portion of a lower surface of the ceramic body and connected to the second internal electrode and the fourth internal electrode.
The method according to claim 1,
The length of the ceramic body is A, the length of the first external electrode on the upper surface of the ceramic body is B1, and the length of the second external electrode on the lower surface of the ceramic body is B2. Lt; RTI ID = 0.0 > of: < / RTI >
0.55? B1 / A? 0.95
0.55? B2 / A? 0.95
The method according to claim 1,
A first seed layer is disposed between an upper surface of the ceramic body and the first external electrode,
And a second seed layer is disposed between the lower surface of the ceramic body and the second external electrode.
The method according to claim 1,
The distance between the first internal electrode disposed on the uppermost layer of the capacitance forming portion and the adjacent third internal electrode is not less than 1 탆 and not more than 4 탆,
Wherein a distance between the second internal electrode disposed at the lowermost layer of the capacitance forming section and the fourth internal electrode adjacent to the capacitance forming section is 1 占 퐉 or more and 4 占 퐉 or less.
The method according to claim 1,
When the length of the first internal electrode is L1, the length of the second internal electrode is L2, the length of the third internal electrode is L3, and the length of the fourth internal electrode is L4,
L3 / L1 is from 0.95 to 1.05,
L4 / L2 is 0.95 to 1.05.
The method according to claim 1,
Wherein the first and second external electrodes are formed by electroless plating.
The method according to claim 1,
Wherein a plurality of said third and fourth internal electrodes are formed.
The method according to claim 1,
Wherein the first external electrode extends only on an upper surface of the ceramic body,
Wherein the second external electrode is extended only to the lower surface of the ceramic body.
KR1020140177190A 2014-12-10 2014-12-10 Laminated ceramic electronic component KR102048102B1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110027321A (en) * 2009-09-10 2011-03-16 삼성전기주식회사 Multilayer chip capacitor and circuit board device
KR20110101910A (en) 2010-03-10 2011-09-16 대우조선해양 주식회사 Device for diminishing flow resistance and swashing wave in a moon pool
KR20140032294A (en) * 2012-09-06 2014-03-14 삼성전기주식회사 Conductive paste for external electrode, multi-layered ceramic electronic parts fabricated by using the same and fabricating method thereof
KR20140060393A (en) * 2012-11-09 2014-05-20 삼성전기주식회사 Multi-layered ceramic capacitor, mounting structure of circuit having thereon multi-layered ceramic capacitor and packing unit for multi-layered ceramic capacitor
KR20140112884A (en) * 2013-03-14 2014-09-24 삼성전기주식회사 Embedded multilayer capacitor and print circuit board having embedded multilayer capacitor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110027321A (en) * 2009-09-10 2011-03-16 삼성전기주식회사 Multilayer chip capacitor and circuit board device
KR20110101910A (en) 2010-03-10 2011-09-16 대우조선해양 주식회사 Device for diminishing flow resistance and swashing wave in a moon pool
KR20140032294A (en) * 2012-09-06 2014-03-14 삼성전기주식회사 Conductive paste for external electrode, multi-layered ceramic electronic parts fabricated by using the same and fabricating method thereof
KR20140060393A (en) * 2012-11-09 2014-05-20 삼성전기주식회사 Multi-layered ceramic capacitor, mounting structure of circuit having thereon multi-layered ceramic capacitor and packing unit for multi-layered ceramic capacitor
KR20140112884A (en) * 2013-03-14 2014-09-24 삼성전기주식회사 Embedded multilayer capacitor and print circuit board having embedded multilayer capacitor

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