KR101598289B1 - Multi-layered ceramic capacitor and board for mounting the same - Google Patents

Multi-layered ceramic capacitor and board for mounting the same Download PDF

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Publication number
KR101598289B1
KR101598289B1 KR1020140100597A KR20140100597A KR101598289B1 KR 101598289 B1 KR101598289 B1 KR 101598289B1 KR 1020140100597 A KR1020140100597 A KR 1020140100597A KR 20140100597 A KR20140100597 A KR 20140100597A KR 101598289 B1 KR101598289 B1 KR 101598289B1
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South Korea
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ceramic body
mounting surface
lead portions
capacitor
external electrodes
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KR1020140100597A
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Korean (ko)
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KR20150050326A (en
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박민철
안영규
이교광
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삼성전기주식회사
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Priority to KR1020130131105A priority patent/KR20140038915A/en
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Priority claimed from US14/522,533 external-priority patent/US20150114704A1/en
Publication of KR20150050326A publication Critical patent/KR20150050326A/en
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Abstract

The present invention is characterized in that three external electrodes are arranged on a mounting surface of a ceramic body so as to be spaced apart from each other and the length of the ceramic body is defined as L and the width of the active layer including a plurality of internal electrodes arranged in the width direction is defined as A A / L < / = 1.14.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a multilayer ceramic capacitor,

The present invention relates to a multilayer ceramic capacitor and a mounting substrate thereof.

Background Art [0002] With the recent miniaturization and high capacity of electronic products, electronic components used in electronic products are also required to be smaller and have higher capacity.

In the case of the multilayer ceramic capacitor, if the equivalent series inductance (hereinafter referred to as " ESL ") is increased, the performance of the electronic product may deteriorate. As the applied electronic component is miniaturized and the capacity is increased, the ESL of the multilayer ceramic capacitor is increased The influence on the performance degradation becomes relatively large.

In particular, the use of decoupling capacitors has been increasing as the performance of ICs has increased, so there is a need for a so-called " MLCC " which is a vertically stacked three terminal MLCC capable of reducing the distance between external terminals, thereby reducing the current flow path and thereby reducing the inductance of the capacitor. LICC (Low Inductance Chip Capacitor) "

Korean Patent Publication No. 2008-0073193 U.S. Patent No. 6,950,300

It is an object of the present invention to provide a multilayer ceramic capacitor and its mounting substrate capable of maximizing low ESL characteristics.

According to one aspect of the present invention, three external electrodes are arranged on a mounting surface of a ceramic body so as to be spaced apart from each other, and the length of the ceramic body is L and the width of the active layer including a plurality of internal electrodes , A multilayer ceramic capacitor satisfying a range of 0.64? A / L? 1.14 is provided.

According to one embodiment of the present invention, a multilayer ceramic capacitor having a vertical stacked three-terminal structure is miniaturized, but the width of the current path is maintained by downsizing the ceramic body only in the longitudinal direction, It is possible to maximize the low ESL characteristics of the multilayer ceramic capacitor by preventing the increase of the ESL of the ceramic capacitor.

1 is a perspective view schematically showing a multilayer ceramic capacitor according to an embodiment of the present invention.
2 is a perspective view showing the ceramic body of the multilayer ceramic capacitor of FIG. 1 in an inverted state.
3 is an exploded perspective view of the multilayer ceramic capacitor of FIG. 1, in which external electrodes are omitted.
4 is a cross-sectional view showing the multilayer ceramic capacitor of FIG.
5 is a perspective view schematically showing a multilayer ceramic capacitor according to another embodiment of the present invention.
FIG. 6 is an exploded perspective view of the multilayer ceramic capacitor of FIG. 5, in which external electrodes are omitted.
7 is a cross-sectional view showing the multilayer ceramic capacitor of FIG.
8 is a perspective view schematically showing a multilayer ceramic capacitor according to still another embodiment of the present invention.
FIG. 9 is a perspective view showing a ceramic body of the multilayer ceramic capacitor of FIG. 8. FIG.
10 is an exploded perspective view of the multilayer ceramic capacitor of FIG. 8, in which external electrodes are omitted.
11 is a cross-sectional view showing the multilayer ceramic capacitor of Fig.
12 is a perspective view showing a state in which the multilayer ceramic capacitor of FIG. 8 is mounted on a substrate.
13 is a cross-sectional view showing a state in which the multilayer ceramic capacitor of FIG. 8 is mounted on a substrate.
FIG. 14 is a graph comparing ESL characteristics according to the size of the multilayer ceramic capacitor.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below.

Further, the embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art.

The shape and size of elements in the drawings may be exaggerated for clarity.

In the drawings, like reference numerals are used to designate like elements that are functionally equivalent to the same reference numerals in the drawings.

In order to clearly illustrate the embodiments of the present invention, when the directions of the hexahedron are defined, L, W and T shown in Fig. 1 indicate the longitudinal direction, the width direction and the thickness direction, respectively. Here, the width direction can be used in the same concept as the lamination direction in which the dielectric layers are laminated.

Multilayer Ceramic Capacitors

FIG. 1 is a perspective view schematically showing a multilayer ceramic capacitor according to an embodiment of the present invention, FIG. 2 is a perspective view showing a ceramic body of the multilayer ceramic capacitor shown in FIG. 1, and FIG. 3 is a cross- FIG. 4 is a cross-sectional view showing the multilayer ceramic capacitor of FIG. 1. FIG.

1 to 4, a multilayer ceramic capacitor 100 according to the present embodiment includes a ceramic body 110 in which a plurality of dielectric layers 111 are stacked in a width direction, a plurality of first and second internal electrodes 121, and 122, and first to third external electrodes 133, 134, and 136, respectively.

That is, the multilayer ceramic capacitor 100 of the present embodiment can be regarded as a three-terminal capacitor having three external terminals in total.

In the present embodiment, when the length of the ceramic body 110 is defined as L and the width of the active layer is defined as A, the range of 0.64? A / L? 1.14 can be satisfied.

The ceramic body 110 has a first surface S1 and a second surface S2 facing each other in the thickness direction and a first surface S1 and a second surface S2, The third surface S3 and the fourth surface S4, and the fifth and sixth surfaces S5 and S6 facing each other in the width direction.

Hereinafter, the mounting surface of the multilayer ceramic capacitor 100 will be described as the first main surface S1 of the ceramic body 110 in the present embodiment.

The ceramic body 110 is formed by laminating a plurality of dielectric layers 111 in the width direction and then firing, and the shape is not particularly limited, but may be a hexahedron shape as shown in the figure.

In the present embodiment, when the length of the ceramic body 110 is L and the width of the ceramic body 110 is W, the range of 0.7? W / L? 1.2 can be satisfied.

14 is a graph showing ESL characteristics according to chip sizes.

In the case of Comparative Example 1, the chip has a length x width of 1.6 x 0.8 (mm). In Comparative Example 2, the chip has a length x width of 1.0 x 0.5 (mm) mm and a length × width of 1.0 × 0.8 (mm).

Referring to FIG. 14, the ESL of Comparative Example 1 was 35 pH and the ESL of Comparative Example 2 was 45 pH higher than Comparative Example 1. However, in Comparative Example 1, only the length was decreased, and W / L was 0.8 It can be seen that the ESL was reduced at 31 pH as compared with Comparative Examples 1 and 2.

When the W / L is less than 0.7, it is difficult to realize a low ESL. When the W / L exceeds 1.2, that is, when the width of the ceramic body 110 is excessively larger than the length of the ceramic body 110, There is a problem that a cutting failure may occur severely in a capacitor manufacturing process. The W / L may preferably be set to 1.0 or less so as not to cause a cutting failure in the manufacturing process.

In addition, the length of the ceramic body 110 may be 0.8 mm or more. When the length of the ceramic body 110 is less than 0.8 mm, the length of the lead portions of the first and second internal electrodes, which will be described later, decreases in the L-direction and ESR (Equivalent Series Resistance) can be increased.

Such an increase in ESR may cause heat generation of the chip and deteriorate efficiency.

The plurality of dielectric layers 111 forming the ceramic body 110 are in a sintered state and the boundaries between the adjacent dielectric layers 111 are such that it is difficult to confirm without using a scanning electron microscope (SEM) Can be integrated.

The ceramic body 110 includes an active layer having a plurality of internal electrodes as a portion contributing to capacity formation of the capacitor and cover layers 112 and 113 formed on both sides of the active layer as margin portions in the width direction .

The active layer may be formed by repeatedly laminating a plurality of first and second internal electrodes 121 and 122 in the width direction with the dielectric layer 111 interposed therebetween.

In the present embodiment, when the length of the ceramic body 110 is defined as L and the width of the active layer is defined as A, the range of 0.64? A / L? 1.14 can be satisfied. The A / L may more preferably be 0.94 or less so as not to cause cutting failure in the multilayer ceramic capacitor manufacturing process.

As in the present embodiment, when the length of the ceramic body 110 and the width of the active layer are numerically limited, the width of the dielectric layer 111 can be utilized as full as the active layer, that is, the capacitor can be used, It is possible to secure a maximum capacity of a certain level.

In the present embodiment, on the other hand, the thicknesses of the cover layers 112 and 113 must be kept to a minimum in order to realize various capacities of the capacitors while keeping the ESL low.

In the vertical capacitor according to the present embodiment, when the width of the active layer is reduced, the width of the current path is reduced and the ESL can be increased.

In this embodiment, the width of the active layer with respect to the length of the ceramic body 110 can be ensured to a certain level or more, thereby realizing a low ESL of a certain level or less.

At this time, the thickness of the dielectric layer 111 can be arbitrarily changed according to the capacity design of the multilayer ceramic capacitor 100. The thickness of one layer may be 0.01 to 1.00 m after firing. However, It is not.

The dielectric layer 111 may include a ceramic powder having a high dielectric constant, for example, a barium titanate (BaTiO 3 ) -based or a strontium titanate (SrTiO 3 ) -based powder, and as long as a sufficient electrostatic capacity can be obtained, But is not limited thereto.

If necessary, a ceramic additive, an organic solvent, a plasticizer, a binder, a dispersant, and the like may be further added to the dielectric layer 111 together with the ceramic powder.

In addition, the average particle diameter of the ceramic powder used for forming the dielectric layer 111 is not particularly limited and may be adjusted for achieving the object of the present invention, but may be adjusted to, for example, 400 nm or less.

The cover layers 112 and 113 may have the same material and configuration as the dielectric layer 111 except that they do not include internal electrodes.

The cover layers 112 and 113 may be formed by laminating a single dielectric layer or two or more dielectric layers on both sides of the active layer in the width direction. Basically, the first and second internal electrodes Thereby preventing damage to the first and second electrodes 121 and 122.

The first and second internal electrodes 121 and 122 are electrodes having different polarities and are formed inside the ceramic body 110 and arranged so as to face each other with the dielectric layer 111 interposed therebetween. At this time, the first and second internal electrodes 121 and 122 may be electrically insulated from each other by a dielectric layer 111 disposed in the middle.

The first and second internal electrodes 121 and 122 may be spaced apart from the first and second side surfaces S3 and S4 of the ceramic body 110 in the longitudinal direction.

The first and second internal electrodes 121 and 122 include a capacitor portion that overlaps the neighboring internal electrode and contributes to formation of a capacitor and a lead portion that extends a portion of the capacitor portion and is drawn out to the outside of the ceramic body 110 .

At this time, although the lead portion is not particularly limited, for example, the length of the lead portion may be shorter than the length of the ceramic body 110 of the internal electrode forming the capacitor.

The thickness of the first and second internal electrodes 121 and 122 may be determined depending on the application. For example, the thickness of the first and second internal electrodes 121 and 122 may be determined to fall within a range of 0.2 to 1.0 탆 in consideration of the size of the ceramic body 110, The invention is not limited thereto.

The material for forming the first and second internal electrodes 121 and 122 is not particularly limited and may be selected from a noble metal material such as palladium (Pd), a palladium-silver (Pd-Ag) alloy, And copper (Cu) may be used as the conductive paste.

The conductive paste may be printed by a screen printing method or a gravure printing method, but the present invention is not limited thereto.

The first and second lead portions 121b and 121b 'are disposed to be spaced apart from each other along the longitudinal direction of the ceramic body 110. The first and second lead portions 121b and 121b' And is formed so as to be exposed through the first surface S1 which is a surface.

The third lead portion 122b is disposed between the first and second lead portions 121b and 121b 'so that the third lead portion 122b is exposed through the first surface S1 of the ceramic body 110 from the second internal electrode 122 .

The first and second external electrodes 133 and 134 are electrodes having the same polarity and are disposed on the first surface S1 of the ceramic body 110 so as to be spaced apart from each other along the longitudinal direction of the ceramic body 110, And are electrically connected to the first and second lead portions 121b and 121b 'exposed through the first surface S1 of the ceramic body 110, respectively.

The first and second external electrodes 133 and 134 extend from the first surface S1 of the ceramic body 110 to a portion of the fifth and sixth surfaces S5 and S6 in the width direction of the ceramic body 110 Can be formed to be elongated.

The third external electrode 136 is an electrode having a polarity different from that of the first and second external electrodes 133 and 134, and can be utilized as a ground terminal in the present embodiment.

The third outer electrode 136 is disposed between the first and second outer electrodes 133 and 134 and contacts the third lead portion 122b exposed through the first surface S1 of the ceramic body 110 And are electrically connected.

The third external electrode 136 may extend from the first surface S1 of the ceramic body 110 to a portion of the fifth and sixth surfaces S5 and S6 in the width direction of the ceramic body 110 have.

In general laminated ceramic electronic parts, external electrodes may be disposed on the cross section of the ceramic body facing each other in the longitudinal direction.

In this case, when AC is applied to the external electrode, the current path is long, so that the current loop can be formed larger, and the size of the induced magnetic field is increased, and the inductance can be increased.

In order to solve the above problem, according to one embodiment of the present invention, in order to reduce the current path, the first surface S1 of the ceramic body 110 is provided between the first and second outer electrodes 133 and 134 A third external electrode 136 is disposed.

Each of the first to third external electrodes 133, 134, and 136 has a triple-layer structure. The first to third conductive layers 133a, 134a, and 136a are in contact with the corresponding lead portions of the corresponding internal electrodes, First to third nickel (Ni) plating layers 133b, 134b, 136b formed to cover the first to third conductive layers 133a, 134a, 136a, and first to third nickel plating layers 133b, 134b (Sn) plated layers 133c, 134c, and 136c formed to cover the first, second and third tin (Sn) layers 136a and 136b.

The first to third conductive layers 133a, 134a and 136a may be formed of a conductive material having the same material as that of the first and second internal electrodes 121 and 122. However, the present invention is not limited thereto. For example, the metal paste may be formed of metal powder such as copper (Cu), silver (Ag) and nickel (Ni), and a conductive paste And then firing it.

Experimental Example

The multilayer ceramic capacitor according to the embodiment and the comparative example of the present invention was produced as follows.

A slurry containing a powder such as barium titanate (BaTiO 3 ) is coated on a carrier film and dried to prepare a plurality of ceramic green sheets having a thickness of 1.8 탆.

Next, a first internal electrode having first and second lead portions exposed on first and second surfaces of the ceramic green sheet by applying a conductive paste for a nickel internal electrode on the ceramic green sheet using a screen, A second internal electrode having a third lead portion which is spaced apart from the first and second lead portions and exposed to the first surface of the ceramic green sheet is formed.

Next, the ceramic green sheets are stacked in a range of about 150 to 400 layers, and a ceramic green sheet on which the first and second internal electrodes are not formed is further laminated on both sides to produce a laminate, Was isostatically pressed at 85 DEG C under a pressure of 1000 kgf / cm < 2 >.

Next, the pressed ceramic laminate was cut into individual chips, and the cut chips were maintained at about 230 DEG C for 60 hours in an atmospheric environment to proceed the binder removal.

Next, the ceramic body was fired in a reducing atmosphere at an oxygen partial pressure of 10 -11 to 10 -10 atm lower than the Ni / NiO equilibrium oxygen partial pressure so that the internal electrode was not oxidized at about 1,200 ° C.

The chip size of the multilayer chip capacitor after firing varied from about 1.0 mm in length to 0.5 to 1.3 mm in width. Here, the manufacturing tolerance was set within the range of 占 0.1 mm in length × width (L 占 W).

Next, the first to third external electrodes are formed on the first surface of the ceramic body so as to correspond to the lead portions of the first and second internal electrodes, respectively. Thus, the multilayer ceramic capacitor is completed. An equivalent series inductance (ESL) measurement test was conducted and is shown in Table 1. Each test was performed on 100 sample samples.

number Of ceramic body
Width (W)
Of the active layer
Width (A)
Inner electrode
Number of layers
ESL (pH) Cutting defect rate (%)
One 0.5mm 0.34mm 150 60.1 0 2 0.5mm 0.44mm 150 48.4 0 3 0.5mm 0.44mm 250 49.2 0 4 0.6mm 0.44mm 250 48.7 0 5 0.6mm 0.54mm 250 40.6 0 6 0.6mm 0.54mm 400 40.1 0 7 0.7mm 0.64mm 400 31.1 0 8 0.8mm 0.74 mm 400 27.4 0 9 0.9mm 0.84mm 400 24.1 0 10 1.0 mm 0.94mm 400 21.2 0 11 1.1mm 1.04mm 400 19.6 4% 12 1.2 mm 1.14mm 400 18.5 6% 13 1.3 mm 1.24mm 400 17.4 22%

* Length of ceramic body (L) = 1.0 mm

Referring to Table 1 and FIG. 14, when the width of the ceramic body is equal to the width of the active layer, as in the samples 1, 2, 4, and 5, the ESL decreases as the width of the active layer increases. That is, it can be seen that the width of the active layer must be increased in order to reduce the ESL.

Even if the number of stacked internal electrodes is different in the case where the widths of the active layers are the same as those in the samples (2, 3) and (5, 6), that is, Is not large.

It can also be seen that, even in the case of the samples 3 and 4, even when the width of the ceramic body is large, the ESL difference is not large when the widths of the active layers are the same.

Therefore, the most important factor affecting the ESL is the width of the active layer. In order to realize a low ESL while maximizing the capacity of the capacitor, the width of the ceramic body should be maximally used as the active layer.

In the samples 7 to 12 satisfying the range of 0.64? A / L? 1.14 when the length of the ceramic body was defined as L and the length of the active layer was defined as A, while the ESL was kept at 32 pH or less, Was less than 10%.

In addition, in sample 13 in which the A / L exceeded 1.14, the cutting defect was severe at 22%.

In addition, in Samples 1 to 11 in which the A / L was 0.94 or less, no cutting failure occurred at all.

Variation example

FIG. 5 is a perspective view schematically showing a multilayer ceramic capacitor according to another embodiment of the present invention, FIG. 6 is an exploded perspective view showing the multilayer ceramic capacitor of FIG. 5 with external electrodes omitted, FIG. 7 is a cross- Fig.

Here, since the structure of the ceramic body 110 is the same as that of the first embodiment described above, a detailed description thereof will be omitted in order to avoid duplication, and the first and second internal electrodes 121 and 122 And the insulating layer 150 will be described in detail.

5 to 7, an insulating layer 150 may be disposed on a second surface S2 of the multilayer ceramic capacitor 100 'of the present embodiment, which is opposed to the mounting surface of the ceramic body 110. FIG.

The first internal electrode 121 is exposed through the second surface S2 of the ceramic body 110 and contacts the insulating layer 150 formed on the second surface S2 of the ceramic body 110. [ 5 lead portions 121a and 121a '.

The second internal electrode 122 is disposed between the third and fourth lead portions 121a and 121a 'and is exposed through the second surface S2 of the ceramic body 110 to be in contact with the insulating layer 150 6 lead portions 122a.

8 is a perspective view schematically showing a multilayer ceramic capacitor according to another embodiment of the present invention, FIG. 9 is a perspective view showing a ceramic body of the multilayer ceramic capacitor of FIG. 8, FIG. 10 is a cross- FIG. 11 is a cross-sectional view showing the multilayer ceramic capacitor of FIG. 8. FIG.

Here, since the structure of the ceramic body 110 is the same as that of the embodiment described above, a detailed description thereof will be omitted in order to avoid duplication, and the fourth to sixth external electrodes 131 and 132 having a structure different from the above- And 135 and the first and second internal electrodes 121 and 122 will be described in detail.

8 to 11, the multilayer ceramic capacitor 100 "of the present embodiment has a structure in which the fourth to sixth external electrodes 131, 132, and 135 are formed on the second surface S2 of the ceramic body 110 And are disposed to face the first to third external electrodes 133, 134 and 136.

At this time, the fourth to sixth external electrodes 131, 132, and 135 may extend to a portion of the fifth and sixth surfaces S5 and S6 of the ceramic body 110 in the width direction, if necessary.

The fourth to sixth external electrodes 131, 132, and 135 have a triple layer structure, and the fourth to sixth conductive layers 131a, 132a, and 135a, which are in contact with and connected to the lead portions of the corresponding internal electrodes, Fourth to sixth nickel (Ni) plating layers 131b, 132b and 135b formed to cover the fourth to sixth conductive layers 131a, 132a and 135a and fourth to sixth nickel plating layers 131b and 132b (Sn) plating layers 131c, 132c, and 135c formed to cover the first to sixth tin (Sn) layers 135a and 135b.

The first internal electrode 121 is exposed through the second surface S2 of the ceramic body 110 to form fourth and fifth external electrodes 131 and 132 formed on the second surface S2 of the ceramic body 110, And the fourth and fifth lead portions 121a and 121a ', respectively.

The second internal electrode 122 is disposed between the third and fourth lead portions 121a and 121a 'and is exposed through the second surface S2 of the ceramic body 110 to be connected to the sixth external electrode 135 And a second lead portion 122a.

As described above, when the internal and external structures of the multilayer ceramic capacitor 100 "are formed in a vertically symmetrical structure, the directionality of the capacitor can be eliminated.

Therefore, since any one of the first and second surfaces S1 and S2 of the multilayer ceramic capacitor 100 "can be provided as the mounting surface, the direction of the mounting surface is considered when the multilayer ceramic capacitor 100 " There is an advantage to not have.

The mounting substrate of the multilayer ceramic capacitor

FIG. 12 is a perspective view showing a state in which the multilayer ceramic capacitor of FIG. 8 is mounted on a substrate, and FIG. 13 is a sectional view showing a multilayer ceramic capacitor of FIG. 8 mounted on a substrate.

12 and 13, the mounting substrate 200 of the multilayer ceramic capacitor according to the present embodiment includes a substrate 210 mounted so that the multilayer ceramic capacitor is horizontally mounted, a substrate 210 formed on the upper surface of the substrate 210, And third electrode pads 221, 222, and 223, respectively.

At this time, the multilayer ceramic capacitor is formed by the solder 230 in a state where the first to third external electrodes 133, 134 and 136 are in contact with the first to third electrode pads 221, 222 and 223, (Not shown).

13, reference numeral 224 denotes a ground terminal, and reference numeral 225 denotes a power supply terminal.

8, but the present invention is not limited thereto. For example, the multilayer ceramic capacitor shown in FIG. 1 and FIG. 5 may have a structure similar to the multilayer ceramic capacitor shown in FIGS. So that the mounting board can be constructed.

The present invention is not limited to the above-described embodiments and the accompanying drawings, but is intended to be limited only by the appended claims.

It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. something to do.

100, 100 ', 100 "; Multilayer Ceramic Capacitors
110; Ceramic body
111; Dielectric layer
112, 113; Cover layer
121, 122; The first and second internal electrodes
121b, 121b '; The first and second lead portions
122b; The third lead portion
121a, 121a '; The fourth and fifth lead portions
122a; The sixth lead portion
133; The first outer electrode
134; The second outer electrode
136; The third outer electrode
131; The fourth external electrode
132; The fifth outer electrode
135; The sixth outer electrode
200; Mounting substrate
210; Board
221, 222, 223; The first to third electrode pads
230; Solder

Claims (13)

  1. A ceramic body including a plurality of dielectric layers stacked in a width direction and including an active layer including a plurality of first and second internal electrodes arranged alternately with the dielectric layer interposed therebetween;
    First and second lead portions extending from the first internal electrode to be exposed through a mounting surface of the ceramic body, the first and second lead portions being spaced apart from each other along the longitudinal direction of the ceramic body;
    A third lead portion extending from the second internal electrode to be exposed through a mounting surface of the ceramic body and positioned between the first and second lead portions when viewed in the longitudinal direction;
    First and second external electrodes disposed on the mounting surface of the ceramic body so as to be spaced apart from each other along the longitudinal direction of the ceramic body and respectively connected to the first and second lead portions; And
    A third external electrode disposed between the first and second external electrodes on a mounting surface of the ceramic body and connected to the third lead portion; / RTI >
    A multilayer ceramic capacitor satisfying a relation of 0.64 ≤ A / L ≤ 1.14 where L is a length of the ceramic body and A is a width of the active layer.
  2. The method according to claim 1,
    Wherein said A / L is 0.94 or less.
  3. The method according to claim 1,
    Wherein L is a length of the ceramic body, and W is a width of the ceramic body, the multilayer ceramic capacitor satisfies a relation of 0.7? W / L? 1.2.
  4. The method of claim 3,
    Wherein the W / L is 1.0 or less.
  5. The method according to claim 1,
    Wherein the length of the ceramic body is greater than 0.8 mm.
  6. The method according to claim 1,
    Wherein the first and second internal electrodes are spaced apart from both longitudinal sides of the ceramic body.
  7. The method according to claim 1,
    And a cover layer disposed on both sides in the width direction of the active layer.
  8. The method according to claim 1,
    Wherein the first to third external electrodes are formed to extend from a mounting surface of the ceramic body to a portion of both sides in a width direction of the ceramic body.
  9. The method according to claim 1,
    Fourth and fifth lead portions extending from the first internal electrode to be exposed through a surface opposite to the mounting surface of the ceramic body, the fourth and fifth lead portions being spaced apart from each other along the longitudinal direction of the ceramic body;
    A sixth lead portion extending from the second internal electrode to be exposed through a surface facing the mounting surface of the ceramic body and positioned between the fourth and fifth lead portions when viewed in the longitudinal direction; And
    An insulating layer disposed on a surface facing the mounting surface of the ceramic body; And a capacitor.
  10. 10. The method of claim 9,
    And the fourth to sixth external electrodes are formed to extend to a portion of both sides of the ceramic body in the width direction on a surface facing the mounting surface of the ceramic body.
  11. The method according to claim 1,
    Fourth and fifth lead portions extending from the first internal electrode to be exposed through a surface opposite to the mounting surface of the ceramic body, the fourth and fifth lead portions being spaced apart from each other along the longitudinal direction of the ceramic body;
    A sixth lead portion extending from the second internal electrode to be exposed through a surface facing the mounting surface of the ceramic body and positioned between the fourth and fifth lead portions when viewed in the longitudinal direction;
    Fourth and fifth external electrodes disposed on the surface of the ceramic body opposite to the ceramic body in the longitudinal direction of the ceramic body and connected to the fourth and fifth lead portions, respectively; And
    A sixth external electrode disposed between the fourth and fifth external electrodes on a surface facing the mounting surface of the ceramic body and connected to the sixth lead portion; And a capacitor.
  12. 12. The method of claim 11,
    And the fourth to sixth external electrodes are formed to extend to a portion of both sides of the ceramic body in the width direction on a surface facing the mounting surface of the ceramic body.
  13. A substrate having first to third electrode pads on an upper surface thereof; And
    The multilayer ceramic capacitor of any one of claims 1 to 12, wherein first to third external electrodes are disposed on the first to third electrode pads, respectively. And a capacitor connected to the capacitor.
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KR1020130131105 2013-10-31
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US14/522,533 US20150114704A1 (en) 2013-10-31 2014-10-23 Multilayer ceramic capacitor and board having the same
US15/403,988 US9820383B2 (en) 2013-10-31 2017-01-11 Multilayer ceramic capacitor having three external electrodes and board having the same
US15/787,443 US10136518B2 (en) 2013-10-31 2017-10-18 Multilayer ceramic capacitor having three external electrodes and board having the same

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