KR20160065763A - Method of manufacturing lead frame - Google Patents
Method of manufacturing lead frame Download PDFInfo
- Publication number
- KR20160065763A KR20160065763A KR1020150169367A KR20150169367A KR20160065763A KR 20160065763 A KR20160065763 A KR 20160065763A KR 1020150169367 A KR1020150169367 A KR 1020150169367A KR 20150169367 A KR20150169367 A KR 20150169367A KR 20160065763 A KR20160065763 A KR 20160065763A
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- KR
- South Korea
- Prior art keywords
- etching
- lead frame
- mask
- pattern
- metal plate
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 87
- 239000002184 metal Substances 0.000 claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 37
- 238000007747 plating Methods 0.000 claims description 71
- 239000004065 semiconductor Substances 0.000 claims description 67
- 238000007788 roughening Methods 0.000 claims description 38
- 239000007788 liquid Substances 0.000 claims description 14
- 238000000059 patterning Methods 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 abstract description 3
- 230000000994 depressogenic effect Effects 0.000 abstract 2
- 230000001131 transforming effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 71
- 239000011347 resin Substances 0.000 description 18
- 229920005989 resin Polymers 0.000 description 18
- 239000000243 solution Substances 0.000 description 15
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 238000005507 spraying Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 3
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000005484 gravity Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000001143 conditioned effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- ing And Chemical Polishing (AREA)
Abstract
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a lead frame, and more particularly, to a method of manufacturing a lead frame in which roughening is performed on a surface.
Conventionally, in a lead frame used in a semiconductor package mounted with a semiconductor element and resin-sealed, when the roughening treatment is performed on the lead frame for the purpose of improving adhesion to resin, the entire surface of the metal material, And the lead frame was formed using this material. In this case, the lead frame is formed on the etched surface or the press-processed surface, on which the roughened surface is not formed.
Further, in the case where the roughening treatment is carried out after forming the lead frame shape, a lead frame in which the front and back surfaces are flush with each other is formed.
In any of the methods, since the surface of the lead frame is matched, there is a problem in that a lead frame requiring glossiness may not be able to obtain a required gloss even if the surface is plated. In addition, there is a problem that paste for adhering the mounted semiconductor element may flow out from the PAD portion in the portion where the semiconductor element is mounted (PAD portion).
With respect to such a problem, Patent Document 1 discloses a technique of forming plating first and then using the plating as a mask to coarsen the lead frame with an etching solution.
However, in the structure described in Patent Document 1, there is a problem that the plating surface is harmonized depending on the type of plating required, and the selection of the etching liquid is also required, which is not general-purpose. In addition, since it is necessary to form a plating on a part where harmonization is not required, there is a problem that the cost is increased.
In recent years, however, since the size and thickness of the semiconductor package are required to be small, there is a problem that the resin used for the package and the lead frame are peeled from each other due to the difference in thermal expansion coefficient. For example, in a QFN (Quad Flat Non-Leaded) type package, the side surface and the surface of the lead frame used are in contact with the resin, and the back surface is exposed in the package bottom surface. There is no need for harmony because of the problem of flowing out. Likewise, in a portion where electrical connection is required by semiconductor elements and wire bonding, harmonization is not required due to bonding. As described above, there is a demand for surface balancing at the portions that do not affect bonding or bonding of semiconductor elements, as described above.
However, it is clear that a method of adjusting the side surface by forming a mask covering the front and back surfaces of the lead frame, and a method of flatly returning the surface of the lead frame in which the entire surfaces are matched, , These methods can not be adopted as they are.
It is therefore an object of the present invention to provide a method of manufacturing a lead frame capable of performing surface roughening only at necessary portions without increasing the number of steps and manufacturing cost.
In order to achieve the above object, a method of manufacturing a leadframe according to an embodiment of the present invention is a method of manufacturing a leadframe having a concave portion formed by a half-etching process,
An etching step of etching the metal plate using a mask having a pattern for half etching processing and a pattern for through etching processing to form the recess and the through pattern on the metal plate;
A mask deforming step of deforming the half etching processing pattern into an opening for roughening treatment,
And a harmonization processing step of harmonizing the metal plate using the mask in which the half etching processing pattern is deformed into the harmonizing processing opening.
According to the present invention, it is possible to obtain a lead frame in which harmonization is performed only in a necessary area without adding a new process.
1 is a view showing an example of a semiconductor package using a lead frame manufactured by a lead frame manufacturing method according to an embodiment of the present invention.
Fig. 2 is an enlarged view showing a formation portion of a roughened treatment layer of a semiconductor element mounting portion of a lead frame manufactured by a lead frame manufacturing method according to an embodiment of the present invention. Fig.
3 is a view showing a series of steps of an example of a method of manufacturing a lead frame according to an embodiment of the present invention. 3 (a) is a view showing an example of a plating layer forming step and an etching mask forming step. 3 (b) is a diagram showing an example of an etching process and an etching mask deformation process. Fig. 3 (c) is a view showing an example of the harmonization processing step. FIG. 3 (d) is a view showing an example of a mask removal process.
Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
1 is a view showing an example of a semiconductor package using a lead frame manufactured by a lead frame manufacturing method according to an embodiment of the present invention.
The
The
1 shows an example in which the
Like the
The
The
The
On the other hand, in the case where the
The
The
Fig. 2 is an enlarged view showing a formation portion of the
In the
Next, a method of manufacturing the lead frame having such a structure will be described with reference to Fig. Fig. 3 is a view showing a series of processes as an example of a method of manufacturing a lead frame according to an embodiment of the present invention. The same constituent elements as those described so far are denoted by the same reference numerals as those described above, and a description thereof will be omitted.
3 (a) is a view showing an example of a plating layer forming step and an etching mask forming step. In the plating layer forming step and the etching mask forming step, the
First, the
In forming the
After the
The resist
The
On the other hand, only the through-etching-
3 (b) is a diagram showing an example of an etching process and an etching mask deformation process. In the etching process, a wet etching process is performed, and a through-
The etching solution may be an etching solution capable of etching the
After the etching process is completed, the resist layer 81 (mask portion) in the half
Fig. 3 (c) is a view showing an example of the harmonization processing step. The roughening treatment step supplies the roughening treatment liquid to the surface of the metal plate 10 (hereinafter referred to as "
FIG. 3 (d) is a view showing an example of a mask removal process. In the mask removal step, the
Thus, the
The
Next, an embodiment in which a method of manufacturing a lead frame according to an embodiment of the present invention is performed will be described.
Example
A dry film resist (AQ-2058, manufactured by Asahi Kasei Chemicals Co., Ltd.) was adhered to both surfaces using a copper material having a thickness of 0.2 mm as a metal plate to form a resist layer.
Next, exposure and development are carried out using a glass mask for upper side and rear side, in which a pattern for forming a plating is formed, thereby forming a plating mask in which the surface of the metal sheet is partially exposed, Respectively.
Then, plating was performed to form a plating layer on the exposed portion of the surface of the metal sheet. In this embodiment, Ni plating with a set value of 1.0 占 퐉, Pd plating with a set value of 0.05 占 퐉, and Au plating with a set value of 0.02 占 퐉 were sequentially performed from the metal plate side to form three plated layers.
Next, the plating masks formed on both surfaces of the metal plate were peeled off with a 3% aqueous solution of sodium hydroxide, and further washed with 3% sulfuric acid.
Then, a dry film resist (AQ-4096, manufactured by Asahi Kasei Chemicals Co., Ltd.) was again adhered to both surfaces of the plated metal plate to form a resist layer, and the shape of the lead frame and the pattern for half- Both surfaces were exposed using a glass mask and developed to form an etching mask covering the formed plating. At this time, the portion where the half-etching is performed does not require the same amount of etching solution as the through-etching, and is formed as a mask in the same state as an island for controlling the amount of etching liquid.
Then, a lead frame was formed by spray etching using a ferric chloride solution. The etching was carried out by using a ferric chloride solution having a liquid temperature of 70 占 폚 and a specific gravity of 1.47 and spraying at a set pressure of 0.3 MPa by a swinging nozzle for about 160 seconds. By this etching process, the etching mask became a new harmonization processing mask.
Next, the copper crystals adhering to the etching solution surface were removed by hydrochloric acid cleaning by spraying, and then subjected to a coarsening treatment by spraying with a coarsening treatment liquid (CZ8100, manufactured by Mitsubishi Chemical Corporation). The roughening treatment liquid was conditioned at a liquid temperature of 35 ° C, a specific gravity of 1.145, and a steel concentration of 35 g / l, and was subjected to a roughening treatment for 20 seconds by spraying. The surface roughness of the roughened surface was found to be SRa 0.2-0.4.
Then, the residue of the roughening treatment liquid attached to the roughened surface was removed by hydrochloric acid cleaning by spraying, and then the roughening treatment mask was peeled off by using an aqueous solution of sodium hydroxide. Thereafter, an acid treatment with sulfuric acid was carried out and the surface was dried to complete a lead frame in which the etching solution surface was partially harmonized.
As described above, this embodiment is an example in which the lead frame shape is formed after plating is formed. However, in the case of forming the lead frame first, the plating mask forming step, the plating step, and the plating mask removing step are not used It is possible to start by starting the etching mask formation process. It is also possible to form a plating on the entire surface of the formed lead frame, and to form a plating on a necessary portion by using a plating mask.
Although the preferred embodiments and examples of the present invention have been described in detail, it is to be understood that the present invention is not limited to the above-described embodiments and examples, and various changes and modifications may be made by those skilled in the art without departing from the scope of the present invention. Branching and substitution can be applied.
10: metal plate 11: semiconductor element mounting portion
12:
11b, 12b: back
13: Through-pattern 14:
15: Lead frame 20: Harmonized layer
30: Plating layer 40: Semiconductor element
50: bonding wire 60: resin
70:
81: resist layer 82: opening
83: pattern for through-etching process 84: pattern for half-etching process
Claims (12)
An etching step of etching the metal plate using a mask having a pattern for half etching processing and a pattern for through etching processing to form the recess and the through pattern on the metal plate;
A mask deforming step of deforming the half etching working pattern into an opening for roughening treatment;
Wherein the metal plate is subjected to a harmonizing process for harmonizing the metal plate using the mask in which the pattern for half etching is deformed into the opening for harmonization processing
≪ / RTI >
Wherein the etching of the metal sheet in the etching step is performed simultaneously from both sides of the metal sheet.
Wherein the concave portion is formed on at least one of the semiconductor element mounting portion and the terminal portion.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JPJP-P-2014-242864 | 2014-12-01 | ||
| JP2014242864A JP6362111B2 (en) | 2014-12-01 | 2014-12-01 | Lead frame manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20160065763A true KR20160065763A (en) | 2016-06-09 |
| KR101773260B1 KR101773260B1 (en) | 2017-08-31 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020150169367A KR101773260B1 (en) | 2014-12-01 | 2015-11-30 | Method of manufacturing lead frame |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP6362111B2 (en) |
| KR (1) | KR101773260B1 (en) |
| CN (1) | CN105655259B (en) |
| TW (1) | TWI600131B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6259139B1 (en) * | 2017-03-24 | 2018-01-10 | シチズンファインデバイス株式会社 | Plate member, member, rectangular piece, member manufacturing method, and fluid ejection orifice plate manufacturing method |
| JP6724851B2 (en) | 2017-04-14 | 2020-07-15 | 株式会社デンソー | Base material, mold package using the same, base material manufacturing method, and mold package manufacturing method |
| JP7353794B2 (en) * | 2019-05-13 | 2023-10-02 | ローム株式会社 | Semiconductor device, its manufacturing method, and module |
| TW202129077A (en) * | 2019-10-11 | 2021-08-01 | 日商聯合精密科技股份有限公司 | Metal machined component, component-mounted module equipped with same, and method for manufacturing same |
| CN113534612B (en) * | 2020-04-17 | 2023-02-17 | 中铝洛阳铜加工有限公司 | Rapid method for detecting flatness of high-precision lead frame material for etching |
| CN112151489B (en) * | 2020-09-01 | 2023-06-06 | 通富微电科技(南通)有限公司 | Lead frame, method for forming lead frame, and lead frame package |
| JPWO2022113661A1 (en) * | 2020-11-30 | 2022-06-02 | ||
| JP7494107B2 (en) | 2020-12-28 | 2024-06-03 | 新光電気工業株式会社 | Lead frame, manufacturing method thereof and semiconductor device |
| JP7413626B1 (en) | 2023-05-02 | 2024-01-16 | 長華科技股▲ふん▼有限公司 | Lead frame and its manufacturing method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008187045A (en) | 2007-01-30 | 2008-08-14 | Matsushita Electric Ind Co Ltd | Lead frame for semiconductor device, manufacturing method therefor, and the semiconductor device |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0231844B2 (en) * | 1986-08-18 | 1990-07-17 | Toppan Printing Co Ltd | HANDOTAISOCHORIIDOFUREEMUNOSEIZOHOHO |
| JP3077918B2 (en) * | 1991-07-04 | 2000-08-21 | 共同印刷株式会社 | Etching method |
| JPH11126859A (en) * | 1997-10-23 | 1999-05-11 | Toppan Printing Co Ltd | Manufacture of lead frame |
| JP2000195984A (en) * | 1998-12-24 | 2000-07-14 | Shinko Electric Ind Co Ltd | Semiconductor device, its manufacture carrier substrate therefor and its manufacture |
| JP3879410B2 (en) * | 2001-02-06 | 2007-02-14 | 凸版印刷株式会社 | Lead frame manufacturing method |
| JP3963655B2 (en) * | 2001-03-22 | 2007-08-22 | 三洋電機株式会社 | Circuit device manufacturing method |
| EP1602749A1 (en) * | 2003-01-17 | 2005-12-07 | Toppan Printing Co., Ltd. | Metal photo-etching product and production method therefor |
| JP4857594B2 (en) * | 2005-04-26 | 2012-01-18 | 大日本印刷株式会社 | Circuit member and method of manufacturing circuit member |
| JP5087787B2 (en) * | 2008-02-12 | 2012-12-05 | 住友金属鉱山株式会社 | Method for manufacturing partially plated lead frame |
| JP2009302209A (en) * | 2008-06-11 | 2009-12-24 | Nec Electronics Corp | Lead frame, semiconductor device, manufacturing method of lead frame, and manufacturing method of semiconductor device |
| JP2010010634A (en) * | 2008-06-30 | 2010-01-14 | Shinko Electric Ind Co Ltd | Lead frame, and method of manufacturing semiconductor device |
| JP5387374B2 (en) * | 2009-12-04 | 2014-01-15 | 住友金属鉱山株式会社 | Lead frame manufacturing method |
| TW201250964A (en) * | 2011-01-27 | 2012-12-16 | Dainippon Printing Co Ltd | Resin-attached lead frame, method for manufacturing same, and lead frame |
| JP5813335B2 (en) * | 2011-02-08 | 2015-11-17 | 新光電気工業株式会社 | Lead frame, semiconductor device, lead frame manufacturing method, and semiconductor device manufacturing method |
| JP6052734B2 (en) * | 2013-03-18 | 2016-12-27 | Ｓｈマテリアル株式会社 | Lead frame for mounting a semiconductor element and manufacturing method thereof |
| JP2014187122A (en) * | 2013-03-22 | 2014-10-02 | Toppan Printing Co Ltd | Led package and method for producing the same |
| JP6347960B2 (en) * | 2014-01-29 | 2018-06-27 | Ａｓｔｉ株式会社 | Microneedle unit and injection device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008187045A (en) | 2007-01-30 | 2008-08-14 | Matsushita Electric Ind Co Ltd | Lead frame for semiconductor device, manufacturing method therefor, and the semiconductor device |
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| Publication number | Publication date |
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| JP2016105432A (en) | 2016-06-09 |
| TW201631725A (en) | 2016-09-01 |
| CN105655259A (en) | 2016-06-08 |
| KR101773260B1 (en) | 2017-08-31 |
| TWI600131B (en) | 2017-09-21 |
| JP6362111B2 (en) | 2018-07-25 |
| CN105655259B (en) | 2019-01-11 |
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