KR20160035193A - Display Device - Google Patents

Abstract

To prevent malfunction, the present invention includes a display panel, a scan driving part, and a compensation circuit part. The display panel displays an image. The scan driving part supplies a scan signal to the display panel. The compensation circuit part monitors the state of the output terminal of the shift register part of the scan driving part, and compensates a voltage supplied to the shift register part in response to the state of the output terminal of the shift register part.

Description

[0001]

The present invention relates to a display device.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, the use of display devices such as an organic light emitting display (OLED), a liquid crystal display (LCD), and a plasma display panel (PDP) is increasing.

Some of the above-described display devices, for example, a liquid crystal display device and an organic light emitting display device, include a display panel including a plurality of sub-pixels arranged in a matrix form and a driver for driving the display panel. The driving unit includes a scan driver for supplying a scan signal (or a gate signal) to the display panel, and a data driver for supplying a data signal to the display panel.

When a scan signal, a data signal, or the like is supplied to the subpixels arranged in a matrix form, the selected subpixel emits light so that an image can be displayed.

A scan driver for outputting a scan signal is implemented as a built-in type formed in a display panel in the form of a gate-in-panel (GIP) formed with a thin film transistor process. The built-in scan driver has various problems due to deterioration of the transistors included in the output stage during long-time driving, and improvement thereof is required.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems of the related art, and it is an object of the present invention to provide a display device capable of improving and preventing problems such as low output or low output of a scan driver,

The present invention provides a display panel, a scan driver, and a compensation circuit. The display panel displays the image. The scan driver supplies a scan signal to the display panel. The compensation circuit part monitors the state of the output terminal of the shift register part of the scan driving part and compensates the voltage supplied to the shift register part according to the state of the output terminal of the shift register part.

The compensation circuit section can stabilize the output level of the gate high voltage output from the shift register section.

The compensation circuit section can vary the voltage level of the clock signal in accordance with the state of the pull-up transistor located at the output terminal of the shift register section.

The compensation circuit section can vary the voltage level of the Q node of the shift register section in accordance with the state of the pull-up transistor located at the output terminal of the shift register section.

The compensation circuit may include a monitor for monitoring the state of the pull-up transistor and a voltage compensator for generating a voltage adjustment signal for varying the voltage level of the clock signal based on the output value from the monitor.

The voltage correction unit can generate the voltage adjustment signal if the result value output from the monitor unit is different from the reference value provided therein.

The voltage correction unit may generate the voltage adjustment signal so that the correction amount (or the variable amount) changes according to the difference between the result value and the reference value.

The monitor unit can be monitored through a pull-up transistor that substantially drives the display panel, or through a monitoring pull-up transistor that is not driving the display panel.

The present invention has the effect of improving and preventing the problem of deterioration of lifetime and reliability of a device as well as a malfunction such as a low or low output of an output signal due to deterioration of a transistor included in an output terminal of the scan driver during long time driving.

1 is a schematic block diagram of a display device;
FIG. 2 is a diagram illustrating a configuration example of a subpixel shown in FIG. 1; FIG.
3 is an exemplary view showing an output terminal of the shift register unit;
4 is a waveform diagram for explaining a problem of the shift register unit during long-time driving;
5 is a waveform for explaining an effect according to the first embodiment of the present invention.
6 is a view showing a compensation circuit according to the first embodiment of the present invention;
7 is an exemplary diagram of voltage variation of a clock signal;
8 shows a compensation circuit according to a second embodiment of the present invention;
9 and 10 are views for explaining the position and driving condition of the pull-up transistor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

≪ Embodiment 1 >

1 is a schematic block diagram of a display device, FIG. 2 is a diagram illustrating a configuration of a subpixel shown in FIG. 1, FIG. 3 is an example of an output terminal of a shift register section, and FIG. FIG. 5 is a waveform diagram for explaining an effect according to the first embodiment of the present invention. FIG.

1, a display device includes a display panel 100, a timing controller 110, a data driver 120, and scan drivers 130 and 140, as shown in FIG.

The display panel 100 includes sub-pixels connected to the data lines DL and the scan lines GL which cross each other. The display panel 100 includes a display region 100A in which subpixels are formed and a non-display region 100B in which various signal lines, pads, and the like are formed outside the display region 100A. The display panel 100 may be implemented by a liquid crystal display (LCD), an organic light emitting display (OLED), an electrophoretic display (EPD), or the like.

As shown in FIG. 2, one subpixel SP is supplied with a scan signal supplied through a switching transistor SW and a switching transistor SW connected to a scan line GL1 and a data line DL1, And a pixel circuit PC that operates in response to the data signal DATA. The switching transistor SW is formed in the form of a thin film transistor. The subpixel SP is implemented by a liquid crystal display panel including a liquid crystal element or an organic light emitting display panel including an organic light emitting element according to the configuration of the pixel circuit PC.

When the display panel 100 is composed of a liquid crystal display panel, it may be a twisted nematic (TN) mode, a VA (Vertical Alignment) mode, an IPS (In Plane Switching) mode, a FFS (Fringe Field Switching) mode, or an ECB (Electrically Controlled Birefringence) Mode. When the display panel 100 is formed of an organic light emitting display panel, it may be implemented as a top emission, a bottom emission, or a dual emission.

The timing controller 110 receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal through an LVDS or TMDS interface receiving circuit connected to an image board. The timing controller 110 generates timing control signals for controlling the operation timings of the data driver 120 and the scan drivers 130 and 140 based on the input timing signal.

The data driver 120 includes a plurality of source drive ICs (Integrated Circuits). The source drive ICs are supplied with the data signal DATA and the source timing control signal DDC from the timing controller 110. The source driver ICs convert the data signal DATA from a digital signal into an analog signal in response to the source timing control signal DDC and supply it through the data lines DL of the display panel 100. [ The source drive ICs are connected to the data lines DL of the display panel 100 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The scan driver 130 and the scan driver 140 include a level shifter 130 and a shift register 140. The scan driver 130 and the scan driver 140 are formed of a gate in panel (GIP) method in which the level shifter 130 and the shift register 140 are separately formed.

The level shifter 130 is formed on an external substrate connected to the display panel 100 in the form of an IC. The level shifter 130 generates a clock signal CLK, a start signal VST, and a power supply based on a signal supplied from the timing controller 110.

The level shifter 130 shifts the level of the generated clock signal CLK, the start signal VST, and the power supply, and supplies the shifted level to the shift register unit 140. The level shifter unit 130 may be included in a power supply unit for generating and outputting power, and may be collectively referred to as a power supply unit.

The shift register unit 140 is formed in the non-display area 100B of the display panel 100 in the form of a thin film transistor by the GIP method. The shift register unit 140 includes stages for shifting and outputting a scan signal in response to a clock signal CLK, a start signal VST, and a power source supplied from the level shifter unit 130. The stages included in the shift register unit 140 sequentially output the scan signals through the output terminals.

The built-in scan driver, in which the level shifter 130 and the shift register 140 are separately formed, is implemented with an oxide or an amorphous silicon thin film transistor or the like in the shift register unit 140. The threshold voltage or the like of the thin film transistor constituting the shift register unit 140 is changed due to deterioration during long-time driving.

As shown in FIGS. 3 to 5, the output terminal of the shift register unit 140 includes a pull-up transistor T6 and a pull-down transistor T7.

In the pull-up transistor T6, a gate electrode is connected to the Q node Q, a first electrode is connected to a clock signal line CLK for transmitting a clock signal, and a second electrode is connected to the scan line GLn. The pull-up transistor T6 is turned on in response to the potential of the Q node Q and outputs the clock signal supplied from the level shifter portion as a scan signal of a gate high voltage.

The pull-down transistor T7 has a gate electrode connected to the QB node QB, a first electrode connected to a low potential voltage line VGL for transmitting a low potential voltage, and a second electrode connected to the scan line GLn. The pull-down transistor T7 is turned on in response to the potential of the QB node QB and outputs the low potential voltage supplied from the level shifter portion as a scan signal of the gate low voltage.

The first electrode and the second electrode of the pull-up transistor T6 and pull-down transistor T7 can be defined as a source electrode, a drain electrode, or a drain electrode and a source electrode, respectively, according to the type of thin film transistor (N type or P type) See also

Meanwhile, the shift register unit 140 outputs a gate-high voltage scan signal and a gate-low voltage scan signal during one frame period. The shift register unit 140 outputs a scan signal having a gate-low voltage for a period longer than the time for outputting the gate-high voltage scan signal for one frame period. However, if driving continues for a long time, a change (movement) occurs in the threshold voltage Vth of the pull-up transistor T6 which outputs the scan signal of the gate high voltage.

The logic high (CLK High) of the clock signal and the logic low (CLK Low) level of the clock signal output from the level shifter unit do not change even if the shift register unit 140 continues driving for a long time. However, when the pull-up transistor T6 located at the output terminal of the shift register unit 140 is deteriorated, the output level of the gate high voltage VGH decreases with time as shown by the slope of Dg shown in FIG. This means that the threshold voltage Vth of the pull-up transistor T6 has shifted.

The first embodiment of the present invention detects and recognizes the deteriorated state of the pull-up transistor T6 in order to solve the deterioration problem of the pull-up transistor T6 located at the output terminal of the shift register unit 140. [ Then, the output level of the lowered gate high voltage VGH is compensated as the slope of Dg in Fig. 5 changes to the slope of the CP. The first embodiment of the present invention compensates the voltage supplied to the Q node in response to the deterioration of the pull-up transistor T6 located at the output terminal of the shift register unit 140. [

For example, according to the first embodiment of the present invention, when the state of the pull-up transistor T6 is sensed by using the compensation circuit and the voltage level of the clock signal is varied when it is determined that the pull-up transistor T6 is deteriorated, (VGH). In addition, the voltage supplied to the Q node is compensated in response to the deterioration of the pull-up transistor T6.

The compensation circuit portion can compensate in such a manner that the logic high level of the clock signal is varied in response to the state of the pull-up transistor T6. The output level of the gate high voltage VGH by the compensation operation of the compensation circuit portion can be stabilized even if the driving time of the pull-up transistor T6 is sustained (or deterioration continues).

The description of the compensation scheme according to the first embodiment of the present invention will be described below.

FIG. 6 is a view showing a compensation circuit according to the first embodiment of the present invention, and FIG. 7 is an example of voltage variation of a clock signal.

As shown in FIG. 6, the compensation circuit according to the first embodiment of the present invention includes a compensation circuit unit including a monitor unit 150 and a voltage correction unit 160.

A pull-up transistor T6 implemented by the GIP method is formed in the display panel Panel. A monitor unit 150 and a voltage correcting unit 160 are formed on a printed circuit board (PCB) (or a flexible circuit board) electrically connected to a display panel.

The monitor unit 150 is connected to the output terminal of the shift register unit formed on the display panel through the monitor line ML. Specifically, the monitor unit 150 monitors the second electrode of the pull-up transistor T6 through the monitor line ML. The monitor unit 150 may include an OPAMP, a comparator, and a passive element.

The monitor unit 150 detects the output state of the pull-up transistor T6 through the monitor line ML. The monitor unit 150 compares the detection voltage detected through the monitor line ML with a reference voltage transmitted through the reference voltage line Ref and generates and outputs a result value RLT. The result value RLT output through the monitor unit 150 may be output in an analog form or converted into a digital form and output. The reference voltage is set to a voltage corresponding to the initial value before the pull-up transistor T6 is deteriorated.

The voltage correction unit 160 generates and outputs a voltage adjustment signal (voltage adjustment) capable of correcting the clock signal based on the result value RLT supplied from the monitor unit 150. [ The voltage correcting unit 160 may include a circuit for converting an analog signal into a digital signal, a logic circuit, or the like.

The voltage correction unit 160 analyzes the result value RLT supplied from the monitor unit 150 and generates a voltage adjustment signal (voltage adjustment) if the result value RLT is similar to or corresponds to the reference value provided therein.

On the other hand, the voltage correction unit 160 analyzes the result value RLT supplied from the monitor unit 150 and generates a voltage adjustment signal (voltage adjustment) if the result value RLT is different from the reference value provided therein. At this time, the voltage correction unit 160 may generate a voltage adjustment signal (voltage adjustment) so that the correction amount (or the variable amount) may be different according to the difference between the result value RLT and the reference value.

The voltage correction unit 160 supplies the generated voltage adjustment signal (voltage adjustment) to the level shifter unit. The voltage correction unit 160 may be included in the timing control unit or in the level shifter unit or may be implemented as a separate circuit.

As shown in FIG. 7, the level shifter 130 varies the clock signal CLK in response to the voltage adjustment signal (voltage adjustment) output from the voltage correction unit. The clock signal CLK maintains the first level L1 (normal level) corresponding to the voltage adjustment signal (voltage adjustment) or the second to fourth levels L2 to L4 (compensation level) of the positive direction or the negative direction To the second to fourth levels (-L2 to -L4) (compensation level)

The reason why the clock signal CLK is varied in the positive direction or in the negative direction is to change the level of the signal in various forms corresponding to the driving characteristics of the transistor constituting the shift register portion (since the transistors are of the N type and the P type) to be.

In this manner, the level shifter unit 130 can vary the voltage level of the clock signal in response to the voltage adjustment signal (voltage adjustment). As a result, even if the pull-up transistor is deteriorated, the voltage level of the clock signal is varied corresponding to deterioration, so that the scan driver can constantly compensate and maintain the output level of the gate high voltage.

≪ Embodiment 2 >

8 is a view illustrating a compensation circuit according to a second embodiment of the present invention.

8, the compensation circuit according to the second embodiment of the present invention includes a monitor unit 150, a first auxiliary circuit 153, a second auxiliary circuit 155, and a voltage correction unit 160 And a timing control unit 110. [

A pull-up transistor T6 implemented by the GIP method is formed in the display panel Panel. The monitor 150, the first sub-circuit 153, the second sub-circuit 155, and the voltage corrector 160 (or the flexible circuit board), which are electrically connected to the display panel, ) Is formed in the timing control unit 110.

The monitor unit 150 is connected to the output terminal of the shift register unit formed on the display panel through the monitor line ML. Specifically, the monitor unit 150 monitors the second electrode of the pull-up transistor T6 through the monitor line ML. The monitor unit 150 may include an OPAMP, a comparator, and a passive element.

The monitor unit 150 detects the output state of the pull-up transistor T6 through the monitor line ML. The monitor unit 150 compares the detection voltage detected through the monitor line ML with the reference voltage transmitted through the reference voltage line Ref, and generates and outputs the resultant value RLT. The result value RLT output through the monitor unit 150 may be converted into a digital form and output.

The first auxiliary circuit 153 is implemented as a current sink source and the second auxiliary circuit 155 is implemented as a passive element such as a resistor and a capacitor. The first and second auxiliary circuits 153 and 155 are used to provide reliability of the circuit when the monitor unit 150 monitors the output terminal of the shift register unit formed on the display panel via the monitor line ML In addition to the circuit shown in Fig.

The timing control unit 110 including the voltage correction unit 160 generates and outputs a voltage adjustment signal (voltage adjustment) capable of correcting the clock signal based on the result value RLT supplied from the monitor unit 150 . The voltage correcting unit 160 may include a circuit for converting an analog signal into a digital signal, a logic circuit, or the like.

The timing control unit 110 including the voltage correction unit 160 analyzes the result value RLT supplied from the monitor unit 150 and outputs a voltage adjustment signal RLT when the result value RLT is similar to or correspond to a reference value provided therein Voltage adjustment) is not generated.

Meanwhile, the timing controller 110 including the voltage corrector 160 analyzes the result value RLT supplied from the monitor unit 150 and outputs a voltage adjustment signal (voltage) if the result value RLT is different from a reference value provided therein Adjustment). At this time, the timing control unit 110 including the voltage correction unit 160 generates a voltage adjustment signal (voltage adjustment) so that the correction amount (or the variable amount) may be different according to the difference between the result value RLT and the reference value .

The timing control unit 110 including the voltage correction unit 160 supplies the generated voltage adjustment signal (voltage adjustment) to the level shifter unit. The voltage correcting unit 160 may be included in the level shifter unit not in the timing controller 110, or may be implemented as a separate circuit.

As shown in FIG. 7, the level shifter 130 varies the clock signal CLK in response to the voltage adjustment signal (voltage adjustment) output from the voltage correction unit. The clock signal CLK maintains the first level L1 in correspondence with the voltage adjustment signal (voltage adjustment) or the second to fourth levels L2 to L4 in the positive direction or the second to fourth levels -L2 to -L4.

The reason why the clock signal CLK is varied in the positive direction or the negative direction is to vary the level of the signal in various forms corresponding to the driving characteristics of the transistors constituting the shift register portion.

The level shifter 130 can vary the voltage level of the clock signal in response to the voltage adjustment signal (voltage adjustment). As a result, even if the pull-up transistor is deteriorated, the voltage level of the clock signal is varied corresponding to deterioration, so that the scan driver can constantly compensate and maintain the output level of the gate high voltage.

The level shifter 130 can also compensate for the voltage to be supplied to the Q node in response to the voltage adjustment signal (voltage adjustment) in the same manner as described above.

Hereinafter, the position and driving condition of the pull-up transistor will be described.

9 and 10 are views for explaining the position and driving condition of the pull-up transistor.

As shown in FIG. 9, a position monitored by the compensation circuit section through the monitor line ML is selected as a pull-up transistor present at the output terminal of one of the stages of the shift register section 140. That is, the monitoring object of the compensation circuit portion is selected as a pull-up transistor which substantially drives the display panel 100. [

In this case, the pull-up transistor continues to operate. Therefore, the compensation circuit part can perform the monitoring and compensation operation through the monitor line ML connected to the pull-up transistor selected as the monitoring object without supplying a separate signal. However, if monitoring is performed during a period in which the display panel 100 displays an image, a voltage drop or the like may be caused at the output terminal of the shift register unit 140. [

Therefore, the compensation circuit part can detect the output state of the pull-up transistor T6 through the monitor line ML after turning on the pull-up transistor T6 and flowing the current or voltage during the blank interval or the non-display interval. At this time, a signal for turning on the pull-up transistor T6 may be selected as a clock signal. After detecting the output state of the pull-up transistor T6, the Q node connected to the gate electrode of the pull-up transistor T6 is discharged.

Since the structure described above performs monitoring with the pull-up transistor driving the display panel 100, a section in which monitoring can be performed is limited.

As shown in Fig. 10, a position monitored by the compensation circuit section through the monitor line ML is selected as a pull-up transistor present at the output terminal of the dummy stage 140d among the stages of the shift register section 140. [ That is, the monitoring object of the compensation circuit portion is selected as a dummy pull-up transistor (or a monitoring pull-up transistor) that does not substantially drive the display panel 100.

In such a case, the pull-up transistor can not be continuously operated, so it must be stressed arbitrarily. For example, a circuit is implemented to output a clock signal while driving the Q node of the pull-up transistor. That is, the circuit is implemented so that the dummy stage 140d is subjected to stresses similar to or the same as those of the stages of the shift register unit 140. [

Therefore, the compensation circuit part can supply a separate signal or the like to perform the monitoring and compensation operation through the monitor line (ML) connected to the pull-up transistor selected as the monitoring target. Unlike FIG. 9, even if monitoring is performed during a period in which the display panel 100 displays an image, a problem such as a voltage drop does not occur at the output terminal of the shift register unit 140.

Therefore, the compensation circuit portion can detect the output state of the pull-up transistor T6 through the monitor line ML during all the intervals including the display period, the blank interval, or the non-display interval.

Since the structure described above performs the monitoring with the pull-up transistor that does not drive the display panel 100, it is possible to dispense with the limitation on the section in which monitoring can be performed.

In the present invention, monitoring objects are exemplified by monitoring through a pull-up transistor that substantially drives the display panel or by monitoring a pull-up transistor that is not driving the display panel as shown in Figs. 9 and 10, You can use both of these examples. The reason for this is that the state of the pull-up transistor must be compensated in real time, and the state of the pull-up transistor must be compensated when the display panel is initially driven or when the display panel is turned off.

As described above, the present invention has the effect of improving and preventing the problem that the lifetime and the reliability of the device are deteriorated due to the malfunction such as the low or low output of the output signal due to the deterioration of the transistor included in the output terminal of the scan driver during the long time driving.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

100: display panel 110: timing controller
120: Data driver 130: Level shifter
140: Shift register unit T6: Pull-up transistor
T7: pull-down transistor 150: monitor section
160:

Claims (8)

Display panel;
A scan driver for supplying a scan signal to the display panel; And
And a compensation circuit unit for monitoring a state of an output terminal of the shift register unit of the scan driver and compensating for a voltage supplied to the shift register unit in accordance with the state of the output terminal of the shift register unit. The method according to claim 1,
The compensation circuit section
And stabilizes the output level of the gate high voltage output from the shift register unit. The method according to claim 1,
The compensation circuit section
Wherein the voltage level of the clock signal is varied in accordance with the state of the pull-up transistor located at the output terminal of the shift register unit. The method according to claim 1,
The compensation circuit section
Wherein the voltage level of the Q node of the shift register unit is varied corresponding to the state of the pull-up transistor located at the output terminal of the shift register unit. The method of claim 3,
The compensation circuit section
A monitor unit for monitoring a deterioration state of the pull-up transistor,
And a voltage correcting unit for generating a voltage adjusting signal for varying a voltage level of the clock signal based on a result value output from the monitor unit. 6. The method of claim 5,
The voltage correction unit
And generates the voltage adjustment signal if a result value output from the monitor unit is different from a reference value provided therein. The method according to claim 6,
The voltage correction unit
And generates the voltage adjustment signal so that the correction amount (or a variable amount) varies according to the difference between the result value and the reference value. 6. The method of claim 5,
The monitor unit
The display panel may be monitored through a pull-up transistor that is substantially driven,
And monitors the display panel through a monitoring pull-up transistor that is not driving the display panel.

Images