KR20220094669A - Display Device Including Data Driving Part And Gate Driving Part - Google Patents

Abstract

The present invention provides a display device comprising: a timing control unit for generating image data, a data control signal, and a gate control signal; a data driving unit for generating a data voltage by using the image data and the data control signal, selecting a first power supply voltage higher than a gate high voltage during a rising period, which is the beginning of a high period, selecting the gate high voltage during the high period other than the rising period, selecting a second power supply voltage lower than a gate low voltage during a dropping period, which is the beginning of a low period, selecting the gate low voltage during the low period other than the dropping period, to generate a target voltage, and outputting a resultant voltage according to the target voltage; a gate driving unit for generating a gate voltage by using the gate control signal and the resultant voltage; and a display panel for displaying an image by using the gate voltage and the data voltage.

Description

Display Device Including Data Driving Part And Gate Driving Part

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device including a data driver that generates a voltage resulting from an improved slew rate and supplies it to a gate driver.

In line with the information age, the display field has also developed rapidly, and in response to this, a liquid crystal display device (LCD) as a flat panel display device (FPD) with the advantages of thinness, light weight, and low power consumption. ), an organic light emitting diode display device (OLED), a field emission display device (FED), and the like are being developed.

Such a display device displays an image using the data signal and the gate signal of the data driver and the gate driver. In the case of a display device of a portable terminal, a gate-in-panel (GIP) type gate driver is displayed. It is formed on the panel, and the data driver generates a gate driving voltage and supplies it to the gate-in-panel type gate driver.

However, as the resolution and operating frequency increase, the number of sub-pixels increases, and accordingly, one horizontal period (H) is shortened, and there is a problem in that the sampling time for compensating for deterioration of each sub-pixel is insufficient.

In addition, when the sampling time is insufficient, defects such as unevenness occur, thereby deteriorating the optical characteristics of the display device.

The present invention has been proposed to solve this problem, and by using a voltage lower than the gate low voltage at the beginning of the change of the low period and using a voltage higher than the gate high voltage at the beginning of the change of the high period to generate the resulting voltage, the gate An object of the present invention is to provide a display device in which a slew rate of a driving voltage is improved, a sufficient sampling time is secured, and deterioration of optical characteristics is prevented.

In order to solve the above problems, the present invention provides a timing control unit for generating image data, a data control signal and a gate control signal, and a data voltage using the image data and the data control signal to generate a data voltage, which is the initial rise of the high period. selecting a first power voltage higher than the gate high voltage during the period, selecting a gate high voltage during a high period other than the rising period, selecting a second power supply voltage lower than the gate low voltage during a falling period, which is the initial stage of the low period, A data driver that selects a gate low voltage during a low period other than the falling period to generate a target voltage and outputs a result voltage according to the target voltage, a gate driver that generates a gate voltage using the gate control signal and the resultant voltage; A display device including a display panel for displaying an image using a gate voltage and a data voltage is provided.

And, the data driver includes a first mux for selecting one of the first power voltage and the gate high voltage according to the rising signal, and a second mux for selecting one of the second power voltage and the gate low voltage according to the falling signal; It may include a level shifter that selects outputs of the first and second muxes according to the high-low signal to generate a target voltage and outputs the resultant voltage.

Also, the first mux selects the first power voltage during the rising section, selects the gate high voltage during the high section other than the rising section, the second mux selects the second power voltage during the falling section, and during the falling section The gate low voltage can be selected during other low periods.

In addition, the level shifter may select the output of the first mux during the high period and select the output of the second mux during the low period to generate the target voltage.

In addition, the data driver includes a power supply for supplying the first power voltage and the second power voltage, a high voltage generator for generating a gate high voltage by using the first power voltage, and a gate low voltage by using the second power voltage. It may further include a low voltage generator for generating a voltage, a control signal generator for generating a rising signal, a falling signal, and a high-low signal, and a buffer for stabilizing and outputting the resultant voltage of the level shifter.

The rising signal may have a high level voltage during the rising period, the falling signal may have a high level voltage during the falling period, and the high-low signal may have a high level voltage during the high period and a low level voltage during the low period. .

Also, the gate driver may be of a gate-in-panel type disposed on a substrate of the display panel.

In addition, the timing controller and the data driver may be configured as one integrated circuit.

In the present invention, the slew rate of the gate driving voltage is improved and sufficient by using a voltage lower than the gate low voltage at the beginning of the change of the low period and generating the resulting voltage using a voltage higher than the gate high voltage at the beginning of the change of the high period. The sampling time is secured and the optical characteristic deterioration is prevented.

1 is a view showing a display device according to an embodiment of the present invention.
2 is a diagram illustrating a data driving unit, a gate driving unit, and a power supply unit of a display device according to an embodiment of the present invention;
3 is a waveform diagram illustrating a plurality of signals and a plurality of voltages of a data driver of a display device according to an embodiment of the present invention;
4A and 4B are diagrams illustrating resultant voltages in a rising section and a falling section according to first and second power supply voltages of a display device according to an embodiment of the present invention, respectively;

Hereinafter, a display device according to the present invention will be described with reference to the accompanying drawings.

1 is a view showing a display device according to an embodiment of the present invention. The display device may be an organic light emitting diode display device (OLED display device).

1 , the display device 110 according to the embodiment of the present invention includes a timing controller 120 , a data driver 130 , a gate driver 140 , and a display panel 150 .

The timing controller 120 controls image data and data using a plurality of timing signals, such as an image signal transmitted from an external system such as a graphic card or a TV system, a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, and a clock. A signal and a gate control signal are generated, and the generated image data and data control signal are transmitted to the data driver 130 , and the generated gate control signal is transmitted to the gate driver 140 through the data driver 130 .

The data driver 130 generates a data voltage (data signal) by using the data control signal and image data transmitted from the timing controller 120 , and applies the generated data voltage to the data line DL of the display panel 150 . accredit to

The timing controller 120 and the data driver 130 may be configured as one integrated circuit (IC).

The gate driver 140 generates a gate voltage (gate signal) by using a gate control signal transmitted from the timing controller 120 through the data driver 130 , and applies the generated gate voltage to the gate of the display panel 150 . applied to the wiring GL.

Here, the gate driver 140 includes a gate-in-panel that is formed together on the substrate of the display panel 150 on which the gate line GL, the data line DL, and the sub-pixel SP are formed. GIP) type.

The display panel 150 displays an image using a gate voltage and a data voltage. For this purpose, a plurality of sub-pixels SP, a plurality of gate lines GL, and a plurality of data lines DL are disposed in the display area. includes

A plurality of sub-pixels (SP) includes red, green, and blue sub-pixels, and the gate wiring (GL) and data line (DL) intersect each other to define red, green, and blue sub-pixels. Each of the sub-pixels is connected to the gate line GL and the data line DL, and the red, green, and blue sub-pixels may constitute one pixel.

When the display device 110 is an organic light emitting diode display, each of the plurality of sub-pixels SP includes a plurality of thin film transistors such as a switching thin film transistor, a driving thin film transistor, and a sensing thin film transistor, a storage capacitor, and a light emitting diode. can

Here, the data driver 130 generates a gate driving voltage and supplies it to the gate driver 140 , which will be described with reference to the drawings.

FIG. 2 is a diagram illustrating a data driver and a gate driver of a display device according to an embodiment of the present invention, which will be described with reference to FIG. 1 together.

As shown in FIG. 2 , the data driver 130 of the display device 110 according to the embodiment of the present invention includes a power supply unit 160 , a high voltage generator 162 , a low voltage generator 164 , It includes a gate driving voltage generator including a first mux 166 , a second mux 168 , a control signal generator 170 , a level shifter 172 , and a buffer 174 .

In another embodiment, the gate driving voltage generator may be disposed in a separate power supply unit such as a power management integrated circuit (PMIC).

Specifically, the power supply unit 160 generates first and second power voltages V1 and V2 to generate a high voltage generator 162 , a low voltage generator 164 , a first mux 166 , and a second mux. 168, the first and second power voltages V1 and V2 may have positive and negative voltage values, respectively.

The high voltage generator 162 generates a gate high voltage VGH by using the first power voltage V1 of the power supply unit 160 and supplies it to the first mux 166, the gate high voltage VGH. may be a voltage value lower than the first power voltage V1.

The low voltage generator 164 generates a gate low voltage VGL by using the second power voltage V2 of the power supply 160 and supplies it to the second mux 168, the gate low voltage VGL. may be a higher voltage value than the second power voltage V2.

The first mux 166 selects one of the first power voltage V1 and the gate high voltage VGH according to the rising signal SR of the control signal generator 170 to form a level shifter 172 and a buffer ( 174) is output.

The second mux 168 selects one of the second power voltage V2 and the gate low voltage VGL according to the falling signal SF of the control signal generator 170 to form a level shifter 172 and a buffer ( 174) is output.

The control signal generator 170 generates a high-low signal SHL, a rising signal SR, and a falling signal SF, and determines a high section (TPH in FIG. 3 ) and a low section (TPL in FIG. 3 ). The high-low signal SHL of TPF), the falling signal SF is supplied to the second mux 168 .

The level shifter 172 selects the output voltages of the first and second muxes 166 and 168 according to the high-low signal SHL of the control signal generator 170 to generate a target voltage Vtg, and The resulting voltage Vrs according to the voltage Vtg is output to the buffer 174 .

The buffer 174 stabilizes the resulting voltage Vrs of the level shifter 172 and outputs it to the gate driving unit 140 as a gate driving voltage.

The gate driver 140 generates a gate voltage by using a gate driving voltage that is a result voltage Vrs of the level shifter 172 and a gate control signal transmitted from the timing controller 120 .

3 is a waveform diagram illustrating a plurality of signals and a plurality of voltages of a data driver of a display device according to an embodiment of the present invention, which will be described with reference to FIGS. 1 and 2 together.

As shown in FIG. 3 , in the display device 110 according to the embodiment of the present invention, the high-low signal SHL of the control signal generator 170 of the data driver 130 is generated during the high period TPH. It has a high level voltage and has a low level voltage during the low period TPL.

The rising signal SR of the control signal generator 170 has a high level voltage during the rising period TPR, which is an initial stage of the high period TPH, and a low level voltage in the remaining period.

The falling signal SF of the control signal generator 170 has a high level voltage during the falling period TPF, which is an initial stage of the low period TPL, and a low level voltage in the remaining period.

The level shifter 172 generates a target voltage Vtg as the output voltage of the first mux 166 during the high period TPH according to the high-low signal SHL of the control signal generator 170 and generates the target voltage Vtg during the low period ( TPL), a target voltage Vtg is generated as an output voltage of the second mux 168 .

The first mux 166 selects and outputs the first power voltage V1 of the power supply unit 160 during the rising period TPR according to the rising signal SR of the control signal generator 170 , and outputs the rest. During the section (the remaining section of the high section TPH and the low section TPL), the gate high voltage VGH of the high voltage generator 162 is selected and output.

The second mux 168 selects and outputs the second power voltage V2 of the power supply unit 160 during the falling period TPF according to the falling signal SF of the control signal generator 170 , and outputs the rest. During the section (the remaining section of the low section TPL and the high section TPH), the gate low voltage VGL of the low voltage generator 164 is selected and output.

Accordingly, the target voltage Vtg generated by the level shifter 172 becomes the first power voltage V1 during the rising period TPR, which is the initial stage of the high period TPH, and is high except for the rising period TPR. It becomes the gate high voltage VGH during the remaining period of the period TPH, becomes the second power voltage V2 during the falling period TPF which is the initial stage of the low period TPL, and becomes the second power voltage V2 during the low period other than the falling period TPF. It becomes the gate low voltage VGL during the remaining period of TPL.

The target voltage Vtg of the level shifter 172 is output as a result voltage Vrs, and the result voltage Vrs is generated from the gate low voltage VGL during the rising period TPR, which is the initial stage of the high period TPH. It increases to the gate high voltage VGH, and is maintained as the gate high voltage VGH for the remainder of the high period TPH other than the rising period TPR, and during the falling period TPF, which is the initial stage of the low period TPL. It decreases from the gate high voltage VGH to the gate low voltage VGL, and is maintained as the gate low voltage VGL during the remainder of the low period TPL other than the falling period TPF.

Here, the resulting voltage Vrs may have a different slew rate depending on the width (time) of the rising section TPR and the falling section TPF. The slew rate is defined as the ratio of the voltage variation to the time variation. can do.

For example, when the width of the ascending section TPR and the descending section TPF is 0, it corresponds to an infinite slew rate, and as the widths of the ascending section TPR and the falling section TPF increase, the slew rate decreases. do.

In the display device 110 according to the embodiment of the present invention, the target voltage Vtg becomes the first power voltage V1 higher than the gate high voltage VGH in the rising period TPR, and becomes the first power voltage V1 in the falling period TPF. Since the second power voltage V2 is lower than the gate low voltage VGL, the target voltage Vtg in the rising section TPR and the falling section TPF is the gate high voltage VGH and the gate low voltage VGL, respectively. Compared to this case, the slew rate of the resultant voltage Vrs increases and the widths of the rising section TPR and the falling section TPF decrease.

Accordingly, a sampling time for compensating for deterioration of the sub-pixel SP of the display device 110 can be sufficiently secured, and defects such as unevenness can be prevented, thereby minimizing deterioration of optical characteristics.

4A and 4B are diagrams illustrating resultant voltages in a rising section and a falling section according to the first and second power voltages of the display device according to an embodiment of the present invention, respectively, which will be described with reference to FIGS. 1 to 3 . do.

As shown in FIG. 4A , the level shifter 172 does not include a separate first power voltage V1 in the entire high section TPH, and includes only the gate high voltage VGH of about 6.0V ( When outputting the result voltage Vrs using Vtg), the rising section TPR at the beginning of the high section TPH has a width of about 0.7 μs, while the level shifter 172 gates high during the rising section TPR. When the result voltage Vrs is output using the target voltage Vtg including the first power voltage V1 higher than the voltage VGH, the width of the rising period TPR decreases, and the first power voltage V1 ) increases, the width of the rising section TPR further decreases, so that the level shifter 172 uses the target voltage Vtg including the first power voltage V1 of about 8.5V during the rising section TPR. When outputting the resulting voltage Vrs, the rising period TPR may have a width of about 0.3 μs.

That is, during the initial rising period TPR of the high period TPH, the resultant voltage Vrs that is the gate driving voltage is generated using the first power voltage V1 higher than the gate high voltage VGH, thereby generating the rising period TPR. ), it is possible to increase the slew rate in the rising period TPR of the resultant voltage Vrs.

As shown in FIG. 4B , the level shifter 172 does not include a separate second power supply voltage V2 throughout the low period TPL and includes only the gate low voltage VGL of about -6.0V. When outputting the result voltage Vrs using (Vtg), the falling section TPF at the beginning of the low section TPL has a width of about 0.5 μs, while the level shifter 172 is gated during the falling section TPF. When the resultant voltage Vrs is output using the target voltage Vtg including the second power voltage V2 lower than the low voltage VGL, the width of the falling section TPF decreases, As V2) decreases, the width of the falling section TPF further decreases, so that the level shifter 172 increases the target voltage Vtg including the second power voltage V2 of about -8.5V during the falling section TPF. In the case of outputting the result voltage Vrs, the falling section TPF may have a width of about 0.1 μs.

That is, during the initial falling period TPF of the low period TPL, the resultant voltage Vrs that is the gate driving voltage is generated using the second power voltage V2 lower than the gate low voltage VGL, thereby generating the falling period TPF. ), it is possible to increase the slew rate in the falling period TPF of the resultant voltage Vrs.

As described above, in the display device 110 according to the embodiment of the present invention, the first voltage V1 is higher than the gate high voltage VGH in the rising period TPR and the gate low voltage VGL in the falling period TPF. ) by outputting the result voltage Vrs using the target voltage Vtg having the second voltage V2 lower than is reduced, and as a result, a sampling time for compensating for deterioration of the sub-pixel SP of the display device 110 can be sufficiently secured, and defects such as stains can be prevented, thereby minimizing deterioration of optical properties.

Although the above has been described with reference to the preferred embodiment of the present invention, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention described in the claims below You will understand that it can be done.

110: display device 120: timing control unit
130: data driving unit 140: gate driving unit
150: display panel 160: power supply
162: high voltage generator 164: low voltage generator
166, 168: first and second mux 170: control signal generator
172: level shifter 174: buffer

Claims (8)

a timing controller for generating image data, a data control signal, and a gate control signal;
A data voltage is generated using the image data and the data control signal, a first power voltage higher than the gate-high voltage is selected during a rising period that is an initial stage of a high period, and the gate-high voltage is selected during the high period other than the rising period. a voltage is selected, a second power voltage lower than the gate low voltage is selected during a falling section that is an initial stage of a low section, and a target voltage is generated by selecting the gate low voltage during the low section other than the falling section, and the target voltage is generated. a data driver outputting a result voltage according to the voltage;
a gate driver for generating a gate voltage by using the gate control signal and the resultant voltage;
A display panel displaying an image using the gate voltage and the data voltage
A display device comprising a.
The method of claim 1,
The data driver,
a first mux for selecting one of the first power voltage and the gate high voltage according to a rising signal;
a second mux for selecting one of the second power voltage and the gate low voltage according to a falling signal;
A level shifter that selects outputs of the first and second muxes according to a high-low signal to generate the target voltage and outputs the resultant voltage
A display device comprising a.
3. The method of claim 2,
the first mux selects the first power voltage during the rising period and selects the gate high voltage during the high period other than the rising period;
The second mux selects the second power supply voltage during the falling period and selects the gate low voltage during the low period other than the falling period.
3. The method of claim 2,
The level shifter is configured to select an output of the first mux during the high period and select an output of the second mux during the low period to generate the target voltage.
3. The method of claim 2,
The data driver,
a power supply for supplying the first power voltage and the second power voltage;
a high voltage generator generating the gate high voltage using the first power voltage;
a low voltage generator generating the gate low voltage using the second power voltage;
a control signal generator configured to generate the rising signal, the falling signal, and the high-low signal;
A buffer for stabilizing and outputting the resultant voltage of the level shifter
A display device further comprising a.
3. The method of claim 2,
The rising signal has a high level voltage during the rising period,
The falling signal has a high level voltage during the falling period,
The high-low signal has a high level voltage during the high period and a low level voltage during the low period.
The method of claim 1,
The gate driver is a gate-in-panel type display device disposed on a substrate of the display panel.
The method of claim 1,
The timing controller and the data driver are configured as a single integrated circuit.

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