KR20160031065A - Display panel preventing shortage of line and fabricating method thereof - Google Patents

Abstract

The present invention relates to a display panel preventing a line from being short-circuited and a manufacturing method thereof. According to one aspect of the present invention, a display panel is provided to supply reference voltage or operation voltage to a thin film transistor through a connection line made of the same material of a light-shielding layer. According to the other aspect of the present invention, operation voltage is applied to the thin film transistor through an operation voltage connection line made of the same material as the light-shielding layer, and the display panel is also provided to apply reference voltage to the thin film transistor through a reference voltage connection line made of the same material as the light-shielding layer. The display panel comprises: the light-shielding layer placed on the substrate; the connection line made of the same material as the light-shielding layer; the buffer layer placed on the connection line and the light-shielding layer; the film transistor placed on the buffer layer; and a voltage supply line electrically connected to the connection line through a connection hole.

Description

TECHNICAL FIELD [0001] The present invention relates to a display panel and a method of manufacturing the same,

The present invention relates to a display panel for preventing a short circuit of a wiring and a method of manufacturing the same.

2. Description of the Related Art [0002] As an information-oriented society develops, there have been various demands for a display device for displaying images. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various display devices such as an organic light emitting display (OLED) device are being used. Such various display apparatuses include display panels corresponding thereto.

Thin film transistors are formed in each pixel region of the display panel, and a specific pixel region in the display panel is controlled through the current flow of the thin film transistor. The thin film transistor is composed of a gate and a source / drain electrode, and a wiring (line) constituting a circuit in the same process is formed together with the material forming the gate and the source / drain electrode in the process. When a wiring is formed using a gate or a source / drain electrode, if the step between the gate and the source / drain electrode is not large, a short circuit may occur due to an external impact or a foreign substance in the process. However, when the step between the wirings is increased to prevent a short circuit between the wirings, there is a problem that the thickness of the entire panel becomes thick. Therefore, a structure for preventing a short circuit without increasing the thickness of the entire panel is needed.

SUMMARY OF THE INVENTION In view of the foregoing, an object of the present invention is to provide a display device including wiring formed of a material such as a light-shielding layer at a height at which a light-shielding layer is formed in order to increase a level difference, and a method of manufacturing the same.

In order to achieve the above object, in one aspect, the present invention provides a display panel for providing a reference voltage or a driving voltage to a thin film transistor through a connection wiring formed of the same material as the light-shielding layer.

In another aspect of the present invention, a driving voltage is applied to a thin film transistor through a driving voltage connecting line formed of the same material as the light blocking layer, and a reference voltage is applied to the thin film transistor through a reference voltage connecting line formed of the same material as the light blocking layer A display panel is provided.

According to still another aspect of the present invention, there is provided a method of manufacturing a light emitting device, comprising: forming a connection wiring with the same material as the light shielding layer and the light shielding layer; and forming a contact hole in the connection wiring to electrically connect the connection wiring with the driving voltage supply wiring or the reference voltage supply wiring . ≪ / RTI >

As described above, according to the present invention, a driving voltage is applied using a light-shielding layer used in a coplanar structure, or a connection wiring for applying a reference voltage is formed, so that a distance between the data wiring and the data wiring can be increased.

According to the present invention, it is possible to reduce the possibility of a short circuit between the data line and the connection line due to an increase in the distance between the data line and the connection line, thereby improving the stability of the product or the yield of product production on the process.

According to the present invention, since the connection wiring is located in the same layer as the light shielding layer, there is an effect of widening the separation distance between the wirings without increasing the thickness of the display panel.

According to the present invention, since the connection wiring is formed in the same step as the light shielding layer, there is an effect of widening the separation distance between the wirings without increasing the production process of the display panel.

1 is a view schematically showing a display device according to embodiments.
2A is a cross-sectional view showing a coplanar structure to which the present invention is applied.
FIG. 2B is a plan view showing a part of the display device, and FIG. 2C is a view showing a cross section of the regions II 'and II-II' of FIG. 2B.
Fig. 3 is an example in which a short circuit occurs in the interlayer insulating layer between the data wiring and the reference voltage connecting wiring in the structure of Fig.
FIG. 4A is a plan view of a reference voltage connecting wiring according to an embodiment of the present invention formed using a light shielding layer, and FIG. 4B is a sectional view of FIG. 4A.
FIGS. 5A to 5E are views illustrating a process of forming a light-shielding layer according to an embodiment of the present invention and forming a driving voltage connection wiring and a reference voltage connection wiring using a light-shielding layer material.
6 is a cross-sectional view of II 'and II-II' of FIG. 5E according to an embodiment of the present invention.
7 is a flowchart illustrating a process of forming a display panel according to an embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

1 is a view schematically showing a display device according to embodiments.

Referring to FIG. 1, a display device 100 according to an embodiment includes a plurality of first lines VL1 to VLm formed in a first direction (e.g., a vertical direction) A display panel 110 on which a plurality of second lines HL1 to HLn are formed, a first driver 120 for supplying a first signal to a plurality of first lines VL1 to VLm, A second driver 130 for supplying a second signal to the first and second lines HL1 to HLn and a timing controller 140 for controlling the first and second drivers 120 and 130.

The display panel 110 is provided with a plurality of first lines VL1 to VLm formed in a first direction (e.g., a vertical direction) and a plurality of second lines HL1 to HLn formed in a second direction (e.g., A plurality of pixels (P) are defined according to the intersection of the pixels.

Each of the first driving unit 120 and the second driving unit 130 may include at least one driver IC for outputting a signal for displaying an image.

A plurality of first lines VL1 to VLm formed in the first direction on the display panel 110 are formed in a vertical direction (first direction) to transmit a data voltage (first signal) And the first driver 120 may be a data driver for supplying the data voltage to the data line.

A plurality of second lines HL1 to HLn formed in the second direction on the display panel 110 are formed in a horizontal direction (second direction) to form a gate signal (first signal) And the second driver 130 may be a gate driver for supplying a scan signal to the gate line.

In addition, a pad portion is formed on the display panel 110 to connect the first driver 120 and the second driver 130. When the first driver 120 supplies a first signal to the plurality of first lines VL1 through VLm, the pad unit transmits the first signal to the display panel 110 and the second driver 130 similarly applies a plurality of second lines HL1 to HLn), and transmits the second signal to the display panel (110).

At least one thin film transistor is formed in each pixel region. The thin film transistor is composed of a source / drain electrode, a semiconductor layer (active layer), and a gate. Of these, when an oxide semiconductor is used as an active layer, it is referred to as an oxide thin film transistor (oxide TFT). The oxide-based material using the active layer may be IGZO, but the present invention is not limited thereto. The oxide thin film transistor can be applied to a display device including a liquid crystal display device and an organic electroluminescence display. Examples of the oxide semiconductor include zinc oxide (ZnO) semiconductor, indium zinc oxide (IZO) semiconductor, indium aluminum zinc oxide (IAZO) semiconductor, indium gallium zinc oxide, (IZZO) semiconductor, or indium tin zinc oxide (ITZO) semiconductor. However, the present invention is not limited thereto.

On the other hand, in the oxide thin film transistor, when the source / drain electrode is etched in the coplanar structure in which the gate and the source / drain electrode are located above the active layer, the channel layer of the oxide semiconductor is not damaged, can do.

2A is a cross-sectional view showing a coplanar structure to which the present invention is applied. A light shield layer 202 and a buffer layer 204 are formed on a substrate 200 and an oxide semiconductor layer 210 is formed and a gate insulator 215 and a gate 220a are formed do. An interlayer dielectric (ILD) layer 225 is formed thereon and partially etched to expose the oxide semiconductor layer 210, and the source / drain electrodes 230 are contacted through the exposed contact holes. And a passivation layer 260 is formed. When the display panel is formed, the gate 220a and the source / drain electrode 230 are formed and a wiring is formed at the same time.

FIG. 2B is a plan view showing a part of the display device, and FIG. 2C is a view showing a cross section of the regions I-I 'and II-II' of FIG. 2B.

In FIG. 2B, drive voltage supply lines (EVDD or VDD, 285a and 285b) for supplying drive voltages to both sides are located, and a reference voltage supply line 288 for supplying a reference voltage (Vref) . The reference voltage connection wiring 220b for applying the reference voltage supply wiring 288 to the other transistor is formed of a gate layer which is the same material as the gate 220a of FIG. 2A, and a reference voltage connection wiring 220b A reference voltage is applied to the sensing transistors 270a and 270d. The sensing transistors 270a, 270b, 270c, and 270d are transistors for applying a constant voltage Vref necessary for display driving and sensing driving. The switching transistors 275a, 275b, 275c and 275d are connected between the data lines 280a, 280b, 280c and 280d for supplying the data voltage Vdata and the driving transistor (not shown in the figure). The data lines 280a, 280b, 280c, and 280d are formed in the same process as source / drain formation with the same material as the source / drain electrodes. The reference voltage connecting wiring 220b which is connected to the reference voltage supply wiring 288 and applies the reference voltage to the sensing transistors 270a and 270d is formed in the same process with the same material as the gate 220a. As a result, the distance between the data lines 280a, 280b, 280c, and 280d and the reference voltage connecting line 220b is determined by the thickness of the interlayer dielectric (ILD) 225,

Fig. 3 is an example in which a short circuit occurs in the interlayer insulating layer between the data wiring and the reference voltage connecting wiring in the structure of Fig. The interlayer insulating layer 225 between the reference voltage connecting interconnection 220b and the data interconnection 280a is damaged due to an external impact or a foreign matter in the process is introduced and the reference voltage connecting interconnection 220b and the data interconnection 280a ) May be connected to each other as shown in 298, resulting in a short circuit. A short circuit reduces the yield of the display panel. Since only the interlayer insulating layer 225 is located in the overlapping region of the gate layer used as the VDD and Vref connection wirings and the source / drain layer as the data wiring, there is a high possibility that a short circuit will occur.

Hereinafter, embodiments of the present invention utilize the light shielding layer as a VDD and Vref connection wiring to increase a distance between overlapping wirings to prevent a short circuit. That is, the light shielding layer for light shielding of the thin film transistor is utilized not only as a light shielding function but also as a connection wiring for applying VDD and Vref in a pixel. When the light-shielding layer is used as a connection wiring, an interlayer insulating layer as well as a buffer layer is formed between the connection wiring and the data wiring, thereby increasing the distance between the wirings, thereby reducing the possibility of short circuit, .

FIG. 4A is a plan view of a reference voltage connecting wiring according to an embodiment of the present invention formed using a light shielding layer, and FIG. 4B is a sectional view of FIG. 4A.

In FIG. 4A, a reference voltage is applied to the sensing transistors 270a and 270d through the reference voltage connection wiring 402 formed using the light shielding layer. On the other hand, the switching transistors 275a, 275b, 275c, and 275d connect the data lines 280a, 280b, 280c, and 280d that supply the data voltage Vdata to the driving transistor (not shown). The data lines 280a, 280b, 280c, and 280d are formed in the same process as source / drain formation with the same material as the source / drain electrodes.

An interlayer insulating layer 225 and a buffer layer 204 are formed between the data lines 280a, 280b, 280c, and 280d and the reference voltage connecting line 402 as shown in FIG. 4B, The short circuit between the data lines 280a, 280b, 280c, and 280d and the reference voltage connection line 402 can be effectively prevented.

Referring to FIGS. 4A and 4B, in order to prevent a short circuit between the data line and the reference voltage connection line or between the data line and the driving voltage connection line according to an embodiment of the present invention, a light-shielding layer and a reference formed of the same material as the light- The voltage connecting wiring 402 or the driving voltage connecting wiring is located on the substrate. The light-shielding layer and the reference voltage connection wiring 402 or the drive voltage connection wiring are formed in the same layer. A buffer layer is formed thereon (204). An oxide semiconductor layer, a gate, and a source / drain electrode are formed on the buffer layer to form a plurality of thin film transistors. A reference voltage connection wiring 402 or a driving voltage connection wiring of the same material as that of the light-shielding layer formed previously is used as a connection wiring for providing a reference voltage or a driving voltage to the gate, the oxide semiconductor layer, or the source / drain electrode of these thin film transistors . A driving voltage supply wiring and a reference voltage supply wiring 288 for supplying a driving voltage and a reference voltage with the same material as the source / drain electrodes are formed in the same layer as the source / drain electrodes. The reference voltage connection wiring 402 or the drive voltage connection wiring is connected to the reference voltage supply wiring 288 and the drive voltage supply wiring through the contact hole formed in the buffer layer and the interlayer insulating layer, respectively. Further, since the buffer layer and the interlayer insulating layer are formed between the reference voltage connecting wiring and the driving voltage connecting wiring and the data wiring, the possibility of short-circuiting is lowered, thereby increasing the stability of the product and the process yield. The connection between the reference voltage supply wiring 288 and the reference voltage connection wiring 402 and the resulting increase in the distance between the reference voltage connection wiring and the data wiring is shown in FIGS. 4A and 4B.

The driving voltage connecting wiring is also formed in the same layer as the reference voltage connecting wiring. Therefore, the driving voltage connecting wiring is also formed between the data wiring 280a, 280b, 280c, and 280d and the driving voltage connecting wiring, And the buffer layer 204 are formed and increased beyond the distance indicated by 295 in FIG. 2C. As a result, a short circuit between the data lines 280a, 280b, 280c, and 280d and the driving voltage connecting line can be effectively prevented.

FIGS. 5A to 5E are views illustrating a process of forming a light-shielding layer according to an embodiment of the present invention and forming a driving voltage connection wiring and a reference voltage connection wiring using a light-shielding layer material.

Referring to FIG. 5A, there is shown a case where four subpixels are formed in one pixel. The present invention is not limited to the four sub-pixel configurations and is applicable to all thin film transistor structures in which the light-shielding layer is formed.

Light-shielding layers 502a, 502b, 502c, and 502d for each sub-pixel are formed on the substrate. The light shielding layer is distributed in the region where the thin film transistor is formed. A reference voltage connecting wiring 502g and a driving voltage connecting wiring 502e and 502f for applying a reference voltage to the same material as the material forming the light shielding layer are formed. The reference voltage connecting line 502g is electrically connected to the reference voltage supply line formed of the same material as the source / drain electrode in the process of FIG. 5E, described later, through the contact hole to apply the reference voltage Vref to the transistor do. In addition, the driving voltage connecting lines 502e and 502f are electrically connected to the driving voltage supply line formed of the same material as the source / drain electrodes in the process of FIG. 5E described later to apply the reference voltage EVDD to the transistor .

After the light-shielding layer, the driving voltage connection wiring, and the reference voltage connection wiring are formed on the same layer, a buffer layer (not shown) is formed thereon, and thin film transistors are formed. In the case of applying the coplanar structure shown in FIG. 2A as a thin film transistor, after an oxide semiconductor layer is formed, a gate insulating film and a gate are formed thereon, an oxide semiconductor layer is etched to conduct a part, A contact hole is formed in the interlayer insulating layer, and the source / drain electrode is electrically connected to the oxide semiconductor layer which is made conductive through the contact hole. Of course, the present invention is not limited thereto, and can be applied to various semiconductor and thin film transistor structures.

5B is a view showing an oxide semiconductor layer formed. 510a, 510b, 510c and 510d constitute an oxide semiconductor layer of the driving transistor. And 570a, 570b, 570c, and 570d constitute oxide semiconductor layers of the sensing transistors 270a, 270b, 270c, and 270d. 575a, 575b, 575c and 575d constitute the oxide semiconductor layers of the switching transistors 275a, 275b, 275c and 275d.

Referring to FIG. 5C, a gate insulating film (not shown in the figure) and a gate are formed on the oxide semiconductor layer. Gate electrodes 520a, 520b, 520c and 520d of the driving transistor are formed, and wirings 520e for transferring the scan signals in the same process are formed using the same material as the gate.

Referring to FIG. 5D, an interlayer insulating layer is formed on the resultant structure of FIG. 5C, and contact holes are formed to form contact holes of an oxide semiconductor layer, a driving voltage connection wiring, and a reference voltage connection wiring.

The contact holes 511a, 511b, 511c and 511d of the oxide semiconductor layers 510a, 510b, 510c and 510d of the driving transistor are contact holes to which driving voltages are applied, and the other contact holes 512a, 512b, 512c and 512d, Are connected to the oxide semiconductor layers 570a, 570b, 570c, and 570d of the sensing transistors 270a, 270b, 270c, and 270d. The gates 520a, 520b, 520c and 520d of the driving transistor are connected to the switching transistors 275a, 275b, 275c and 275d through the contact holes 513a, 513b, 513c and 513d, respectively.

The contact holes 571a, 571b, 571c and 571d formed on the oxide semiconductor layers 570a, 570b, 570c and 570d of the sensing transistors 270a, 270b, 270c and 270d are connected to the oxide semiconductor layers 510a, 510b, 510c and 510d and the other contact holes 572a, 572b, 572c and 572d are connected to the reference voltage connection line 502g.

On the other hand, the contact holes 576a, 576b, 576c and 576d formed on the oxide semiconductor layers 575a, 575b, 575c and 575d of the switching transistors 275a, 275b, 275c and 275d are connected to the source / And the other contact holes 577a, 577b, 577c and 577d are connected to the data lines 580a, 580b, 580c and 580d to be described later.

5C shows a process of forming three kinds of transistors such as a sensing transistor, a switching transistor, and a driving transistor. The switching transistor is electrically connected to the driving transistor. The sensing transistor is electrically connected to the source or drain electrode of the driving transistor. The source or drain electrode of the sensing transistor is connected to the reference voltage connection wiring or to the reference voltage supply wiring since the reference voltage is applied. However, when a plurality of transistors are closely formed, it is difficult to form a supply wiring for supplying power between these transistors, and for this reason, a connection wiring is required. However, since there is a possibility that a short circuit occurs in a region where the connection wiring is vertically overlapped with the data wiring, in the present invention, the connection wiring is formed as far as possible from the data wiring, At the same time.

The source or drain electrode of the driving transistor is connected to the driving voltage connection wiring or to the driving voltage supply wiring because the driving voltage is applied thereto. When a plurality of thin film transistors are formed such that four sub-pixels constitute one pixel and a drive voltage supply wiring can not be formed therebetween, a connection wiring electrically connected to the drive voltage supply wiring and applying a drive voltage is formed And a driving voltage connecting line formed in the same layer as the light blocking layer according to an embodiment of the present invention may apply a driving voltage to the driving transistors formed apart from the driving voltage supplying line. Likewise, the source or drain electrode of the sensing transistor is connected to the reference voltage connection wiring or to the reference voltage supply wiring since the reference voltage is applied. When a plurality of thin film transistors are formed such that four sub-pixels constitute one pixel and a reference voltage supply wiring can not be formed therebetween, a connection wiring electrically connected to the reference voltage supply wiring to apply the reference voltage And the reference voltage connection line formed in the same layer as the light-shielding layer according to an embodiment of the present invention may apply a reference voltage to the sensing transistors spaced apart from the reference voltage supply line.

Contact holes 505a, 505b and 505c are also formed on the reference voltage connecting wiring 502g so that 505b is connected to the reference voltage supplying wiring and 505a and 505b are connected to the sensing transistors 270a, 270b, 270c and 270d do. On the other hand, contact holes 505e and 505f are also formed on the driving voltage connecting wirings 502e and 502f to be connected to the driving voltage supplying wirings. Further, the other contact holes 506e and 506f on the driving voltage connecting lines 502e and 502f are connected to driving transistors formed separately from the driving voltage supplying line.

FIG. 5E is a diagram in which source / drain electrodes, drive voltage supply lines, and reference voltage supply lines are formed. The driving voltage supply wiring and the reference voltage supply wiring are formed of the same material as the material forming the source / drain electrodes.

The driving voltage supply lines EVDD 585a and 585b are connected to the contact holes 511a and 511d of the driving transistor and are connected to the driving voltage connecting lines 502e and 502f connected to the driving voltage supply lines EVDD 585a and 585b, The contact holes 511b and 511c of the transistors apply driving voltages to the driving transistors connected through 581b and 581c.

The data lines 580a, 580b, 580c and 580d are connected to the contact holes 577a, 577b, 577c and 577d formed on the oxide semiconductor layers 575a, 575b, 575c and 575d of the switching transistors 275a, 275b, 275c and 275d, To apply a data signal to the switching transistor.

On the other hand, the reference voltage supply wiring Vref 588 is connected to the contact holes 572b and 572c of the sensing transistors 270b and 270c of the adjacent sub-pixels. The reference voltage supply wiring 588 is connected to the reference voltage connection wiring 502g through the contact hole 505b. The contact holes 505a and 505c on the reference voltage connection wiring 502g are connected to the contact holes 572a and 572d of the sensing transistors 270a and 270d of the sub pixel to apply a reference voltage.

The reference voltage connecting line 502g and the driving voltage connecting lines 502e and 502f are located under the buffer layer formed in the process of FIGS. 5A and 5B. The data lines 580a, 580b, 580c, and 580d are located on the interlayer insulating layer formed in the processes of FIGS. 5D and 5E. As a result, a buffer layer and an interlayer insulating layer are formed between the reference voltage connecting wiring 502g and the driving voltage connecting wirings 502e and 502f and the data wirings 580a, 580b, 580c, and 580d, thereby preventing a short circuit.

Since the reference voltage connecting line 502g and the driving voltage connecting lines 502e and 502f are formed in the same layer as the light shielding layers 502a and 502b and 502c and 502d, Thereby increasing the distance between the wirings without increasing the thickness of the entire panel, thereby providing an effect of preventing a short circuit.

FIG. 6 is a cross-sectional view taken along line I-I 'and II-II' of FIG. 5E according to an embodiment of the present invention.

610 is a cross-sectional view of I-I 'in which the data lines 580a and 580b are overlapped with the driving voltage connecting line 505e in FIG. 5E. An interlayer insulating layer and a buffer layer are formed between the data lines 580a and 580b and the driving voltage connecting line 505e, so that no short circuit occurs between the two lines.

Reference numeral 620 denotes a cross section of II-II 'in which the data lines 580a and 580b and the reference voltage connecting line 502g are overlapped in FIG. 5E. Similarly, an interlayer insulating layer and a buffer layer are formed between the data wirings 580a and 580b and the reference voltage connecting wiring 502g, so that short-circuiting does not occur. In the case of applying the present invention described above, the light shielding layer, which is the metal layer at the bottom of the coplanar structure, is used as a connection wiring for transferring VDD and Vref in the pixel, It is composed of insulating layer to reduce the possibility of short circuit.

7 is a flowchart illustrating a process of forming a display panel according to an embodiment of the present invention. A process of forming a thin film transistor of a display panel is presented.

A light shielding layer and a connection wiring are formed on the substrate (S710). 5A includes an embodiment in which the light-shielding layer, the driving voltage connection wiring, and the reference voltage connection wiring are formed. Next, a buffer layer is formed on the light-shielding layer and the connection wiring (S720). The thickness of the buffer layer or the material of the buffer layer may be variously selected in consideration of the material of the light-shielding layer or the material of the oxide semiconductor. Next, an oxide semiconductor layer, a gate insulating layer, a gate layer, and an interlayer insulating layer are sequentially formed on the buffer layer (S730). This was illustrated in FIGS. 5B and 5C.

Thereafter, the interlayer insulating layer and the buffer layer are etched to form a first contact hole exposing the connection wiring (S740). Examples of contact holes that expose the connection wiring previously include 505a, 505b, 505c505e, 505f, 506e, and 506f. The supply wirings for supplying the connection wirings and the voltages are connected through the contact holes, and the connection wirings and the thin film transistors are connected through the other contact holes. Thereafter, the interlayer insulating layer is etched to form a second contact hole exposing the oxide semiconductor layer and the gate layer (S750). The process of forming the contact holes may be performed in various manners. After the buffer layer of S720 is formed, the contact holes on the connection wiring are firstly etched, the interlayer insulating layer is formed, and then the contact holes on the connection wiring are secondarily etched have. Next, a voltage supply wiring electrically connected to the connection wiring is formed through the first contact hole on the connection wiring. A source / drain electrode electrically connected to the oxide semiconductor layer or the gate layer is formed through the second contact hole (S760). A voltage supply wiring is formed of the same material as the source / drain electrodes, and a data wiring is also formed in step S760.

7, since the interlayer insulating layer and the buffer layer exist between the data line and the connection line, the thin film transistor of the display panel which is embossed by the process of FIG. 7 can maintain a larger gap than the conventional thin film transistor and lower the possibility of short circuit, thereby enhancing the stability of the product. 7, since the thin-film transistor of the display panel is formed of the same material as the light-shielding layer and is formed of the same material as the light-shielding layer, the thickness of the display panel is not increased, You can expand the distance.

The embodiments disclosed herein can be applied to the field of using all the thin film transistors to which an oxide semiconductor is applied and also can be applied to a coplanar structure of a top gate in one embodiment, But is not limited thereto. Therefore, in the thin film transistor formed with the light shielding layer, the driving voltage connection wiring and the reference voltage connection wiring which are connected to the driving power supply wiring or the reference voltage supply wiring at the time of forming the light shielding layer are formed of the same material as the light shielding layer, Or Vref, and also raises the level difference with the data wiring to reduce the possibility of short circuit and improves process yield or product safety.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: display device 110: display panel
120: first driving part 130: second driving part
140: timing controller 200: substrate
502a, 502b, 502c, 502d: light shielding layers 502e, 502f: driving voltage connecting wiring
502g: Reference voltage connection wiring 580a, 580b, 580c, 580d: Data wiring
585a, 585b: driving voltage supply wiring 588: reference voltage supply wiring

Claims (10)

A light shielding layer disposed on the substrate;
A connection wiring formed on the substrate and formed of the same material as the light shielding layer;
A buffer layer located on the connection wiring and the light shielding layer;
A plurality of thin film transistors positioned on the buffer layer and including an oxide semiconductor layer, a gate, and a source / drain electrode; And
And a voltage supply line formed of the same material as the source / drain electrode and electrically connected to the connection line through the contact hole.
The method according to claim 1,
And a buffer layer and an interlayer insulating layer are formed between the connection wirings and the data wirings formed of the same material as the source / drain electrodes.
The method according to claim 1,
Wherein the connection wiring is a drive voltage connection wiring, and the voltage supply wiring is a drive voltage supply wiring.
The method according to claim 1,
Wherein the connection wiring is a reference voltage connection wiring, and the voltage supply wiring is a reference voltage supply wiring.
A light shielding layer disposed on the substrate;
A driving voltage connection line including a first contact hole formed on the substrate and formed of the same material as the light shielding layer and electrically connected to a driving voltage supply line and a second contact hole electrically connected to the first thin film transistor;
A reference voltage connection line including a third contact hole formed on the substrate and formed of the same material as the light shielding layer and electrically connected to the reference voltage supply line and a fourth contact hole electrically connected to the second thin film transistor;
A buffer layer located on the light-shielding layer, the driving voltage connection wiring, and the reference voltage connection wiring;
A plurality of thin film transistors positioned on the buffer layer and including an oxide semiconductor layer, a gate, and a source / drain electrode;
A driving voltage supply line formed of the same material as the source / drain electrode and electrically connected to the driving voltage connection line through the first contact hole; And
And a reference voltage supply line formed of the same material as the source / drain electrode and electrically connected to the reference voltage connection line through the third contact hole.
6. The method of claim 5,
And a buffer layer and an interlayer insulating layer are formed between the driving voltage connecting wiring and the reference voltage connecting wiring and the data wiring formed of the same material as the source / drain electrode.
6. The method of claim 5,
Wherein the first thin film transistor is the driving transistor and the second thin film transistor is the sensing transistor.
Forming a light-shielding layer and a connection wiring on the substrate;
Forming a buffer layer on the light-shielding layer and the connection wiring;
Sequentially forming an oxide semiconductor layer, a gate insulating layer, a gate layer, and an interlayer insulating layer on the buffer layer;
Etching the interlayer insulating layer and the buffer layer to form a first contact hole exposing a connection wiring;
Etching the interlayer insulating layer to form a second contact hole exposing the oxide semiconductor layer and the gate layer;
Forming a source / drain electrode electrically connected to the oxide semiconductor layer or the gate layer through the voltage supply wiring electrically connected to the connection wiring through the first contact hole and the second contact hole; A method of manufacturing a display panel.
9. The method of claim 8,
Wherein the connection wiring is a drive voltage connection wiring, and the voltage supply wiring is a drive voltage supply wiring.
9. The method of claim 8,
Wherein the connection wiring is a reference voltage connection wiring, and the voltage supply wiring is a reference voltage supply wiring.

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