KR20210086151A - Display panel, method for manufacturing the same and display devie comprising the same - Google Patents

Abstract

The present specification relates to a display panel, a manufacturing method thereof, and a display device including the same. According to an embodiment of the present specification, the display panel includes a thin film transistor formed on a substrate. The thin film transistor comprises: an active layer formed on a substrate and including a channel unit, a first conductive unit extending to one side of the channel unit, and a second conductive unit extending to the other side of the channel unit; a semiconductor layer formed on the substrate to overlap the channel unit; and a gate electrode formed on the substrate so as not to overlap the first and second conductive units. Therefore, the display panel can simplify processes.

Description

A display panel, a manufacturing method thereof, and a display device including the same {DISPLAY PANEL, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVIE COMPRISING THE SAME}

The present specification relates to a display panel, a method of manufacturing the same, and a display device including the same.

A transistor is widely used as a switching element or a driving element in the field of electronic devices. In particular, since a thin film transistor (TFT) may be manufactured on a glass substrate or a plastic substrate, switching of a display device such as a liquid crystal display device or an organic light emitting device It is widely used as an element.

The thin film transistor may be formed in various structures according to the type of material constituting the active layer, an arrangement structure of electrodes (gate electrode, source electrode, drain electrode), a channel formation method, and the like.

For example, a thin film transistor having an oxide BCE structure has an inverted-staggered structure in which an oxide semiconductor is used as an active layer, a gate electrode is disposed below, and source/drain electrodes are disposed above.

In particular, a thin film transistor having a back channel etched (BCE) structure has a simple structure and is simple because an etching process for forming source/drain electrodes is performed without forming an etch stopper (ES) on the semiconductor layer. Since the number of mask processes can be reduced during the manufacturing process, there is an advantage in terms of productivity.

Although the thin film transistor having such an oxide BCE structure is advantageous for realizing high pixels per inch (PPI), a region in which the active layer and the source/drain electrodes overlap is essentially created.

The overlapping region of the active layer and the source/drain electrode is affected by the parasitic capacitor generated between the gate electrode and the source/drain electrode, causing a difference in pixel charging characteristics, resulting in a luminance non-uniformity defect, resulting in deterioration of image quality. Not only does it cause problems, but it is also inefficient in terms of power consumption.

The content of the background art described above is technical information that the inventor of the present specification possessed to derive an example of the present specification or acquired in the process of deriving an example of the present specification, and must be disclosed to the general public prior to the filing of the present specification It cannot be said to be a known technology.

The present specification is to solve the problems of the prior art as described above, and a display panel including an oxide semiconductor layer having a conductor portion made conductive by light irradiation using a gate terminal as a mask, a manufacturing method therefor, and a display including the same It is a technical task to provide a device.

The present specification provides a display panel implemented to prevent overlapping of a gate electrode and a source/drain electrode to suppress generation of a parasitic capacitor between a gate electrode and a source/drain electrode, a manufacturing method thereof, and a display device including the same make it a technical task.

An object of the present specification is to provide a display panel capable of simplifying a process by omitting a process of forming source/drain electrodes constituting a thin film transistor, a manufacturing method thereof, and a display device including the same.

The problems to be solved according to the example of the present specification are not limited to the above-mentioned problems, and other problems not mentioned are from the description below to those of ordinary skill in the art to which the technical idea of the present specification belongs. can be clearly understood.

A display panel according to an embodiment of the present specification for achieving the above technical problem includes a thin film transistor formed on a substrate, the thin film transistor being formed on the substrate and extending to a channel portion and one side of the channel portion An active layer including a first conductive portion and a second conductive portion extending to the other side of the channel portion, a semiconductor layer formed on a substrate to overlap the channel portion, and a semiconductor layer formed on the substrate to not overlap the first and second conductive portions including a gate electrode.

A method of manufacturing a display panel according to an exemplary embodiment of the present specification includes forming a pattern on a substrate, forming a first insulating layer on the substrate to cover the gate electrode, and sequentially forming an active layer on the first insulating layer. and forming a semiconductor layer, wherein the active layer includes a channel portion and first and second conductive portions formed to face each other with the channel portion interposed therebetween, wherein the gate electrode does not overlap the first and second conductive portions do.

Specific details according to various examples of the present specification other than the means for solving the above-mentioned problems are included in the description and drawings below.

According to the means for solving the above problems, by irradiating light to the oxide semiconductor layer using the gate terminal as a mask to form a channel portion and source/drain electrodes, the channel portion and the source/drain electrodes overlap and the gate electrode and the source/drain electrode are formed. It has the effect of preventing overlap.

Accordingly, it is possible to prevent a difference in pixel charging characteristics from being influenced by a parasitic capacitor generated between the gate electrode and the source/drain electrode. In addition, as the problem of the difference in pixel charging characteristics is resolved, the problem of luminance non-uniformity and image quality deterioration can be solved.

In addition, since the process of forming the source/drain electrodes constituting the thin film transistor is omitted, the process may be simplified.

Since the contents of the problems to be solved, the problem solving means, and the effects mentioned above do not specify the essential characteristics of the claims, the scope of the claims is not limited by the matters described in the contents of the specification.

The accompanying drawings are provided to help understanding of the present embodiment, and provide embodiments together with detailed description. However, the technical features of the present embodiment are not limited to specific drawings, and features disclosed in each drawing may be combined with each other to constitute a new embodiment.
1 is a schematic diagram illustrating a configuration of an example of a display device including a display panel according to an embodiment of the present specification.
FIG. 2 is a diagram illustrating an example of an equivalent circuit for any one pixel P of FIG. 1 .
FIG. 3 is a diagram illustrating another example of an equivalent circuit for any one pixel P of FIG. 1 .
4 is a plan view of one pixel of a display panel according to an exemplary embodiment of the present specification.
FIG. 5A is a cross-sectional view illustrating a cross-section taken along the cut line II′ in FIG. 4 .
FIG. 5B is a cross-sectional view showing a cross-section taken along the cut line II-II' in FIG. 4 .
6 is a cross-sectional view of one pixel of a display panel according to another exemplary embodiment of the present specification.
7A to 7L are diagrams for explaining a method of manufacturing a display panel according to an exemplary embodiment of the present specification.
8 is a cross-sectional view illustrating an example of a thin film transistor having a bottom gate structure applied to a display panel according to an embodiment of the present specification.

Advantages and features of the present specification and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present specification to be complete, and in the technical field to which the technical spirit of the present specification belongs It is provided to inform those of ordinary skill in the scope of the technical idea, and the technical idea of the present specification is only defined by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining an example of the present specification are exemplary, the present specification is not limited to the matters shown in the drawings. Like elements may be referred to by the same reference numerals throughout the specification. In addition, in describing an example of the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless the expression 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

For example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., the expression 'directly' or 'directly' is used. One or more other parts may be positioned between the two parts unless otherwise specified.

Spatially relative terms "below, beneath", "lower", "above", "upper", etc. are one element or component as shown in the drawings. and can be used to easily describe the correlation with other devices or components. The spatially relative terms should be understood as terms including different orientations of the device during use or operation in addition to the orientation shown in the drawings. For example, if an element shown in the figures is turned over, an element described as "beneath" or "beneath" another element may be placed "above" the other element. Accordingly, the exemplary term “below” may include both directions below and above. Likewise, the exemplary terms “above” or “on” may include both directions above and below.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless the expression "

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present specification.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of "at least one of the first, second, and third items" means 2 of the first, second, and third items as well as each of the first, second, or third items. It may mean a combination of all items that can be presented from more than one.

Each feature of the various embodiments of the present specification may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently with respect to each other or may be implemented together in a related relationship. may be

In adding reference numerals to the components of each drawing describing the embodiments of the present specification, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings.

In the embodiments of the present specification, the source electrode and the drain electrode are merely distinguished for convenience of description, and the source electrode and the drain electrode may be interchanged. The source electrode may be the drain electrode, and the drain electrode may be the source electrode. Also, the source electrode of one embodiment may be a drain electrode in another embodiment, and the drain electrode of one embodiment may be a source electrode in another embodiment.

In some embodiments of the present specification, a source region and a source electrode are distinguished, and a drain region and a drain electrode are distinguished for convenience of description, but embodiments of the present specification are not limited thereto. The source region may be a source electrode, and the drain region may be a drain electrode. Also, the source region may be the drain electrode, and the drain region may be the source electrode.

Hereinafter, a display panel, a method of manufacturing the same, and a display device including the same according to an embodiment of the present specification will be described with reference to the accompanying drawings and examples.

1 is a schematic diagram illustrating a configuration of an example of a display device including a display panel according to an embodiment of the present specification.

Referring to FIG. 1 , a display device 100 according to an exemplary embodiment may include a display panel 110 , a gate driver 120 , a data driver 130 , and a controller 140 .

In the display panel 110 , gate lines GL and data lines DL are disposed, and a pixel P is disposed in an area where the gate lines GL and data lines DL intersect.

The gate driver 120 is controlled by the controller 140 , and a gate pulse (GP) capable of turning on a switching element to the gate lines GL for one frame. are supplied sequentially. Here, one frame refers to a period in which one image is output through the display panel 110 .

In addition, the gate driver 120 gates a gate off signal (Goff) capable of turning off the switching device during the remaining period in which the gate pulse GP is not supplied during one frame. It is supplied to the lines GL. Hereinafter, the gate pulse GP and the gate-off signal Goff are collectively referred to as a scan signal SS.

According to an embodiment of the present invention, the gate driver 120 may be mounted on the display panel 110 . As described above, a structure in which the gate driver 120 is directly mounted on the display panel 110 is referred to as a gate in panel (GIP) structure. Also, the gate driver 120 may be mounted on only one side of the display panel 110 or may be mounted on both sides of the display panel 110 .

The data driver 130 converts the image data RGB input from the controller 140 into an analog data voltage. In addition, the data driver 130 supplies the data voltage Vdata corresponding to one horizontal line to the data lines DL for each horizontal period in which the gate pulse GP is supplied to the gate line GL. Let the pixel P express the brightness according to the image data.

The controller 140 controls the gate driver 120 and the data driver 130 .

The controller 140 uses various timing signals (eg, a vertical synchronization signal, a horizontal synchronization signal, a clock signal, etc.) supplied from an external system (not shown), and a gate control signal (gate) for controlling the gate driver 120 . A control signal (GCS) and a data control signal (DCS) for controlling the data driver 130 are output. In addition, the controller 140 supplies the image data RGB to the data driver 130 by sampling the input image data input from the external system and rearranging it.

The gate control signal GCS includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), a start signal (Vst), and a gate clock. (GCLK) and the like. Also, the gate control signal GCS may include control signals for controlling the shift register.

The data control signal DCS includes a source start pulse (SSP), a source shift clock signal (SSC), a source output enable signal (source output enable, SOE), and a polarity control signal (polarity, POL). ), etc.

FIG. 2 is a diagram illustrating an example of an equivalent circuit for any one pixel P of FIG. 1 .

FIG. 2 is a case in which the display panel 110 is a liquid crystal display panel. In the pixel P included in the display panel 110 according to the exemplary embodiment of the present specification, at least one thin film used as a switching device for driving liquid crystals. A transistor (TFT) may be included.

Referring to FIG. 2 , one gate line GL and one data line DL may be disposed to cross each other in the pixel P. According to an embodiment, two or more gate lines GL may be disposed between the pixels P, or one data line DL may be disposed in each of the two or more pixels P.

A thin film transistor TFT that is controlled by a scan signal applied to the gate line GL and transmits a data voltage supplied through the data line DL to the pixel electrode PXL may be disposed in the pixel P . In addition, a common electrode COM to which a common voltage is applied may be disposed in the pixel P, and a capacitor C may be formed between the common electrode COM and the pixel electrode PXL.

The thin film transistor TFT is turned on when a turn-on level scan signal (ie, gate pulse GP) is applied through the gate line GL, and the data voltage ( Vdata) is applied to the pixel electrode PXL.

FIG. 3 is a diagram illustrating another example of an equivalent circuit for any one pixel P of FIG. 1 .

3 is a case in which the display panel 110 is an organic light emitting display panel. Each pixel P included in the display panel 110 according to an embodiment of the present invention includes an organic light emitting diode (OLED) emitting light and A pixel driver PDC for driving the organic light emitting diode OLED may be provided.

Signal lines DL, EL, GL, PLA, PLB, SL, and SPL supplying driving signals to the pixel driver PDC may be formed in the pixel P.

The pixel driver PDC outputs to the organic light emitting diode OLED according to the data voltage Vdata transmitted through the switching transistor Tsw1 and the switching transistor Tsw1 connected to the gate line GL and the data line DL. It may include a driving transistor Tdr for controlling the amount of current, and a sensing transistor Tsw2 for sensing characteristics of the driving transistor Tdr.

A gate pulse and a gate row signal are supplied to the gate line GL, and the gate pulse and the gate row signal are collectively referred to as a gate signal VG. A scan pulse and a scan row signal are supplied to the scan pulse line SPL connected to the gate of the sensing transistor Tsw2, and the scan pulse and scan row signal are collectively referred to as a scan control signal SS.

Hereinafter, the technical idea of the present specification will be described with reference to the liquid crystal display panel with reference to FIGS. 4 to 6, but this description is only an example for explaining the technical idea of the present specification, and the technical idea described below is organic light emitting diode The same may be applied to the display panel. Also, hereinafter, the thin film transistor TR is exemplified to have a bottom gate structure, but the thin film transistor TR may be formed to have a top gate structure.

4 is a plan view of one pixel of a display panel according to an exemplary embodiment of the present specification, FIG. 5A is a cross-sectional view taken along the cut line I-I' in FIG. 4 , and FIG. 5B is a cross-sectional view taken along the cut line II in FIG. 4 . It is a cross-sectional view taken along -II', and FIG. 6 is a cross-sectional view of one pixel of a display panel according to another exemplary embodiment of the present specification.

Hereinafter, a pixel of a display panel according to an exemplary embodiment of the present specification will be described with reference to FIGS. 4 to 6 , with reference to FIG. 6 if necessary.

In this specification, region I-I' may be expressed as a transistor region, and region II-II' may be expressed as a pixel region.

4 to 6 , the display panel 400 according to the embodiment of the present specification includes a substrate 410 , a gate electrode 420 formed on the substrate 410 , a first insulating layer 430 , and an active layer ( 440 , a semiconductor layer 450 , a second insulating layer 460 , a first electrode 470 , a second electrode 480 , a third insulating layer 490 , and a third electrode 500 . In addition, the gate electrode 420 , the active layer 440 , and the semiconductor layer 450 may constitute one thin film transistor TR.

In addition, the display panel according to the exemplary embodiment of the present specification may include first to third contact holes CH1 , CH2 , and CH3 , and first and second connection electrodes BR1 and BR2 .

Glass or plastic may be used as the substrate 410 . As the plastic, a transparent plastic having a flexible property, for example, polyimide may be used. When polyimide is used as the substrate 410 , when a high-temperature deposition process is performed on the substrate 410 , a heat-resistant polyimide that can withstand high temperatures may be used.

The gate electrode 420 is patterned and formed on the substrate 410 , and may be a portion extending from the gate line GL or a part of the gate line GL. In this embodiment, the gate electrode 420 is Although exemplified as being formed as a single layer, it may be formed as a multilayer structure including at least two or more conductive layers having different physical properties.

The gate electrode 420 is an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, molybdenum ( Mo) or a molybdenum-based metal such as a molybdenum alloy, may include at least one of chromium (Cr), tantalum (Ta), neodium (Nd), and titanium (Ti).

In the present embodiment, the gate electrode 420 is used as a mask during the rear exposure process for forming the pattern of the semiconductor layer 450 , and the region overlapping the gate electrode 420 of the active layer 440 is exposed during the exposure process. A region that is not exposed to light during the exposure process and does not overlap the gate electrode 420 of the active layer 440 is exposed to light during the exposure process to become a conductor.

As shown in FIG. 5A , the first dummy metal layer DM1 formed in the process of forming the gate electrode 420 may be formed on the same layer as the gate electrode 420 and spaced apart from the gate electrode 420 . 6 , the first dummy metal layer DM1 may be omitted.

The first dummy metal layer DM1 may be used as a signal line required for driving the display panel. However, in FIG. 5A , the first dummy metal layer DM1 is exemplified as being connected to the second conductive part 445 . However, when the first dummy metal layer DM1 is used as a signal line, the second conductive part (445) may not be connected.

The first insulating layer 430 ( 'gate insulating layer') is formed entirely on the substrate 410 to cover the gate electrode 420 , and is disposed between the gate electrode 420 and the active layer 440 , to the gate electrode 420 . ) and the active layer 440 are insulated.

The first insulating layer 430 may include at least one of silicon oxide, silicon nitride, and metal-based oxide. However, the material constituting the gate insulating layer 430 is not limited to this embodiment and may include other insulating materials.

Although the first insulating layer 430 is illustrated as being formed as a single layer in this embodiment, it may be formed in a multi-layered structure including at least two insulating layers having different physical properties.

As shown in FIG. 5A , a dummy hole DH is formed in a region overlapping the first dummy metal layer DM1 of the first insulating layer 430 to expose the first dummy metal layer DM1, and the dummy hole ( The second conductor portion 445 may extend up to DH) to be connected to the first dummy metal layer DM1 , but as shown in FIG. 6 , the dummy hole DH may not be formed.

The active layer 440 is formed on the gate insulating layer 430 , and includes a channel portion 441 that overlaps the gate electrode 420 , and conductive portions 443 and 445 that do not overlap the gate electrode 420 . and a first conductive portion 443 is formed on one side of the channel portion 441 with the channel portion 441 interposed therebetween, and a second conductive portion 445 is formed on the other side of the channel portion 441 .

Accordingly, the channel portion 441 , the first conductive portion 443 , and the second conductive portion 445 are formed on the same layer.

As the active layer 440 , a transparent conductive oxide (TCO) such as ITO or IZO capable of transmitting light may be used, and thus, the semiconductor layer 450 formed on the active layer 440 . ) may be transmitted through the active layer 440 .

In addition, since the active layer 440 should not be etched by the etchant used to form the semiconductor layer 450 , it should be formed of a material that is not visible by the etchant used to form the semiconductor layer 450 . do. That is, the etch selectivity of the material forming the active layer 440 and the material forming the semiconductor layer 450 should be different.

For example, when acetic acid or citric acid is used as the etchant used to form the semiconductor layer 450 , the active layer 440 may be formed of ITO, but the material of the active layer, the material of the semiconductor layer, and the etchant The type may be appropriately selected according to the characteristics.

A part of the conductive parts 443 and 445 becomes a source region, and the other part becomes a drain region. In this embodiment, the first conductive part 443 is a source region, and the second conductive part ( 445 is illustrated as the drain region.

However, this distinction is for convenience of description, and the source region and the drain region may be interchanged. Depending on the voltage, the first conductive portion 443 may serve as a drain region and the second conductive portion 445 may serve as a source region. Also, the first conductive portion 443 may be a source electrode or a drain electrode, and the second conductive lower portion 445 may be a drain electrode or a source electrode.

As shown in FIG. 5A , the second conductor portion 445 may extend to the first dummy metal layer DM1 and may be connected to the first dummy metal layer DM1 through the dummy hole DH.

In the self-aligning structure in which the region other than the channel portion 441 of the active layer 440 is made conductive by using the patterned gate electrode 420 as a mask, the gate electrode 420 is active Used as a mask to conduct some areas of layer 440 .

Accordingly, the channel portion 441 is patterned to correspond to the gate electrode 420 , and a region of the active layer 440 overlapping with the gate electrode 420 becomes the channel portion 441 , so that on the gate electrode 420 , Only the channel portion 441 is formed.

In addition, since the gate electrode 420 does not overlap the source/drain regions 443 and 445 , the generation of parasitic capacitors between the gate electrode 420 and the source/drain regions 443 and 445 is suppressed, and thus Accordingly, it is possible to prevent a difference in pixel charging characteristics from being caused by the parasitic capacitor, and to solve problems of luminance non-uniformity and image quality degradation.

The semiconductor layer 450 is formed to overlap the channel portion 441 on the active layer 440 , and may include an oxide semiconductor material. For example, the semiconductor layer 450 may include at least one of an oxide semiconductor material such as IGZO (InGaZnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, or the like. However, it may include other oxide semiconductor materials known in the art.

According to an embodiment of the present specification as shown in FIG. 5A , since the semiconductor layer 450 is formed through an exposure process using the gate electrode 420 as a mask, the first dummy metal layer DM1 is formed. If present, the first dummy metal layer DM1 also serves as a mask. Accordingly, a region overlapping the first dummy metal layer DM1 of the material layer ('semiconductor layer forming material layer') applied to form the semiconductor layer 450 is also left as it is, so that the same layer as the semiconductor layer 450 is left as it is. A dummy semiconductor layer DS overlapping the first dummy metal layer DM1 is formed.

Of course, as shown in FIG. 6 , when the first dummy metal layer DM1 is not formed, the dummy semiconductor layer DS is also not formed.

The second insulating layer 460 is formed entirely on the substrate 410 to cover the exposed region of the active layer 440 and the semiconductor layer 450 , is made of an insulating material to protect the thin film transistor TR, and the thin film transistor ( TR) and flatten the upper part.

The second insulating film 460 may be formed of an inorganic material, an organic material, or a laminate of an organic material layer and an inorganic material layer, and may be formed as a single layer, but may be formed as two layers or more as in the present embodiment.

When the second insulating layer 460 is formed as a single layer, it functions as a protective layer and a planarization layer, and as in the present embodiment, the second insulating layer 460 forms the first layer, the first sub insulating layer 461 and the first When the second sub insulating layer 463 is disposed on the sub insulating layer 461 and forms a second layer, the first sub insulating layer 461 may be a protective layer, and the second sub insulating layer 463 may be a planarization layer.

The first electrode 470 is formed on the second insulating layer 460 and may be used as a common electrode to which a common voltage is applied or a pixel electrode to which a data voltage is applied. In this embodiment, it is exemplified as being used as a common electrode. do.

As shown in FIG. 5A , the second dummy metal layer DM2 formed in the process of forming the first electrode 470 is formed on the same layer as the first electrode 470 and spaced apart from the first electrode 140 by a predetermined distance. However, as shown in FIG. 6 , the second dummy metal layer DM2 may be omitted.

The second electrode 480 may be formed on the second dummy metal layer DM2 as shown in FIG. 5A , but may also be formed on the same layer as the first electrode 470 as shown in FIG. 6 . . The second electrode 480 may be used as a data line to which a data voltage is applied, and is formed to be spaced apart from the first electrode 470 by a predetermined distance.

When the second dummy metal layer DM2 is formed, the second dummy metal layer DM2 may be used as a data line, and the second electrode 480 may be omitted. The second electrode 480 is preferably formed of a low-resistance material, and the second dummy metal layer DM2 and the second electrode 480 may be formed in one mask process.

The third insulating film 490 is entirely formed on the second insulating film 460, covers the first electrode 470 and the second electrode 480, and may be formed of an inorganic material, an organic material, or a laminate of an organic material layer and an inorganic material layer. and can be used as a protective film.

The third electrode 500 is formed on the third insulating layer 490 and may be used as a common electrode to which a common voltage is applied or a pixel electrode to which a data voltage is applied. In this embodiment, it is exemplified as being used as a pixel electrode. do.

In addition, a first contact hole CH1 connected to the first conductive part 443 is formed through the second insulating layer 460 and the third insulating layer 470 , and a second contact hole CH1 connected to the second electrode 480 is formed. A contact hole CH2 is formed to pass through the third insulating layer 490 , and a third contact hole CH3 connected to the second conductive part 445 connects the second insulating layer 460 and the third insulating layer 470 . formed through

In order to apply the data voltage supplied to the second electrode 480 to the third electrode 500 , the first connection electrode BR1 connecting the second electrode 480 and the first conductive part 443 is connected to the first and a second connection electrode BR2 formed along the second contact holes CH1 and CH2 and connecting the third electrode 500 and the second conductor 445 is formed along the third contact hole CH3. do.

As shown in FIG. 5A , the third contact hole CH3 may pass through the second and third insulating layers 470 to be connected to the dummy semiconductor layer DS, and as shown in FIG. 6 , the third contact hole CH3 may be connected to the dummy semiconductor layer DS. The hole CH3 may be directly connected to the second conductor 445 .

As described above, since the channel portion 441 and the first and second conductive portions 443 and 445 are formed through the exposure process using the gate electrode 420 as a mask, the gate electrode 420 and the first and the second conductor parts 443 and 445 do not overlap. Therefore, a parasitic capacitor does not occur between the gate electrode 420 and the first conductive part 443 and between the gate electrode 420 and the second conductive part 445 , and the pixel charging characteristic by the parasitic capacitor is prevented from being changed. Accordingly, it is possible to solve problems of luminance non-uniformity and image quality degradation.

The non-overlapping structure between the gate electrode 420 and the first and second conductors 443 and 445 may be applied to the liquid crystal display panel exemplified above, as well as to the organic light emitting display panel.

Accordingly, the non-overlapping structure between the gate electrode 420 and the first and second conductor portions 443 and 445 may be applied to a thin film transistor (TFT) provided in a pixel of the liquid crystal display panel shown in FIG. It may be applied to the switching transistor Tsw1, the driving transistor Tdr, and the sensing transistor Tsw2 provided in the pixel of the organic light emitting display panel illustrated in FIG. 3 .

Of course, the pixel structure of the liquid crystal display panel and the pixel structure of the organic light emitting display panel are not limited to FIGS. 2 and 3 , and the non-overlapping structure between the gate electrode 420 and the first and second conductors 443 and 445 . A transistor having a may be further provided in the display panel.

In the above description, the thin film transistor TR is formed in a bottom gate structure as an example, but the non-overlapping structure between the gate electrode 420 and the first and second conductor parts 443 and 445 of the present specification. The thin film transistor TR may be equally applied to the thin film transistor TR having a top gate structure.

The structure of the display panel included in the display device according to the embodiment of the present specification has been described above with reference to FIGS. 1 to 6 . Hereinafter, a method of manufacturing a display panel according to an exemplary embodiment of the present specification will be described with reference to FIGS. 7A to 7L .

The display panel manufacturing method described below is described by taking as an example that applied to the case of manufacturing the liquid crystal display panel shown in FIGS. 4 and 5 , but the gate electrode 420 and the first and second conductors described above The non-overlapping structure between the portions 443 and 445 may be applied to a pixel having a structure different from that of the pixel in FIG. 2 , and may also be applied to a case of manufacturing an organic light emitting display panel.

In addition, the method for manufacturing a display panel described below is described by taking as an example that it is applied to manufacturing a display panel including a thin film transistor TR having a bottom gate structure, but the gate electrode 420 of the present specification The non-overlapping structure between the first and second conductors 443 and 445 may be equally applied to the case of manufacturing a display panel including the thin film transistor TR having a top gate structure.

7A to 7L are views for explaining a method of manufacturing a display panel according to an embodiment of the present specification, wherein (a) is a cross-sectional view, (b) is a plan view corresponding to the cross-sectional view, and for convenience of explanation For this purpose, some components may not be shown in the plan view, the plan view for the cross-sectional view may be omitted, and the description will be focused on the I-I' region, but, if necessary, the II-II' area will be described.

Hereinafter, a method of manufacturing a display panel according to an embodiment of the present specification will be described with reference to 7a to 7l, but a method of manufacturing a display panel according to another embodiment of the present specification may be described in more detail.

First, as shown in FIG. 7A , a gate electrode 420 is patterned on a substrate 410 . In this case, the first dummy metal layer DM1 may be formed on the same layer as the gate electrode 420 and spaced apart from the gate electrode 420 by a predetermined distance. In some embodiments, the first dummy metal layer DM1 is not formed. It may not be.

Thereafter, as shown in FIG. 7B , a first insulating layer 430 is formed on the substrate 410 to cover the gate electrode 420 and the first dummy metal layer DM1 , and the first dummy metal layer DM1 . ), a dummy hole DH is formed in a portion of the region overlapping the . , so that a portion of the first dummy metal layer DM1 is exposed.

When the first dummy metal layer DM1 is not formed in the process of FIG. 7A , the dummy hole DH is not formed, and even though the first dummy metal layer DM1 is formed in the process of FIG. 7A , the dummy hole is not formed. (DH) may not be formed.

Thereafter, as shown in FIGS. 7C to 7H , an active layer 440 is formed on the first insulating layer 430 , and a semiconductor layer 450 is formed on the active layer 440 .

Specifically, as shown in FIG. 7C, in order to form the active layer 440 and the semiconductor layer 450, an active material is applied on the first insulating film 430 to form an active material layer 440a, A semiconductor material is applied on the active material layer 440a to form a semiconductor material layer 450a.

In a subsequent process ( FIG. 7G ), the semiconductor material layer 450a is etched to form the semiconductor layer 450 . The semiconductor material layer 450a should be etched but the active material layer 440a should not be etched.

Accordingly, the active material and the semiconductor material must be appropriately selected according to the etchant. For example, when acetic acid or citric acid is used as the etchant, ITO may be used as the active material, and IGZO may be used as the semiconductor material. However, the type of the etchant, the type of the active material, and the type of the semiconductor material are not limited to the embodiments of the present specification.

The active material layer 440a and the semiconductor material layer 450a are formed to cover the gate electrode 420 , and include a region overlapping the gate electrode 420 and a region not overlapping the gate electrode 420 .

In FIG. 7C , the active material layer 440a extends to the dummy hole DH and is connected to the first dummy metal layer DM1 , and the semiconductor material layer 450a also extends to the dummy hole DH and the active material layer 440a is extended to the dummy hole DH. ) through the first dummy metal layer DM1.

However, even when the first dummy metal layer DM1 is formed, the active material layer 440a and the semiconductor material layer 450a may not extend to the first dummy metal layer DM1 . That is, the active material layer 440a and the semiconductor material layer 450a may not be connected to the first dummy metal layer DM1 .

Thereafter, as shown in FIG. 7D , a photoresist PR is formed on the semiconductor material layer 450a and may be used as a mask for forming the dummy semiconductor layer DS together with the semiconductor layer 450 . , may be used as a mask for forming only the semiconductor layer 450 .

Thereafter, as shown in FIGS. 7E and 7F , a region overlapping the gate electrode 420 of the active material layer 440a becomes a channel portion 441 by an exposure process using the gate electrode 420 as a mask. , a region of the active material layer 440a that does not overlap the gate electrode 420 is made conductive to become conductive portions 443 and 445 . Since the channel portion 441 is not exposed to light, it has substantially the same characteristics as the active material layer 44a.

Thereafter, as shown in FIG. 7G , patterned photoresists PR1 and PR2 are formed through a mask process, and the photoresists PR1 and PR2 are etched by an etching process using the photoresists PR1 and PR2 as a mask. Areas that do not overlap with the photoresists PR1 and PR2 are not corroded, and regions located under the photoresists PR1 and PR2 of the semiconductor material layer 450a remain. , the remaining regions form the semiconductor layer 450 and the dummy semiconductor layer DS.

When only the semiconductor layer 450 is formed, only the first photoresist PR1 is formed. When the semiconductor layer 450 and the dummy semiconductor layer DS are formed, the first and second photoresists PR1 and PR2 are formed. is formed

The first photoresist PR1 is formed to overlap only the gate electrode 420 so that the channel portion 441 and the semiconductor layer 450 of the active layer 440 formed in a subsequent process are aligned with the gate electrode 420 , , the second photoresist PR2 may be formed to overlap only the first dummy metal layer DM1 such that the dummy semiconductor layer DS is aligned with the first dummy metal layer DM1 .

After the semiconductor layer 450 and the dummy semiconductor layer DS are formed, the photoresists PR1 and PR2 are removed to form a display panel as shown in FIG. 7H .

Thereafter, as shown in FIG. 7I , a second insulating layer 460 is formed on the substrate 410 to cover the exposed region of the active layer 440 and the semiconductor layer 450 , and a dummy semiconductor layer DS is formed. In this case, the second insulating layer 460 is formed to also cover the dummy semiconductor layer DS.

The second insulating film 460 may be formed of an inorganic material, an organic material, or a laminate of an organic material layer and an inorganic material layer, and may be formed as a single layer, but in the present embodiment, the second insulating film 460 includes the first sub insulating film 461 and It is exemplified that the second sub insulating film 463 has a two-layer structure.

A first contact hole CH1 and a third contact hole CH3 are formed in the second insulating layer 460 . The first contact hole CH1 is formed in a region overlapping the first conductive portion 443 , The third contact hole CH3 is formed in a region overlapping the second conductive portion 445 . When the dummy semiconductor layer DS is formed as in the present embodiment, the third contact hole CH3 is formed in a region overlapping the dummy semiconductor layer DS.

A mask process is performed to form the first and third contact holes CH1 and CH3, and the first and third contact holes CH1 and CH3 may have different depths formed according to the mask process conditions of FIG. 7I . have.

In this embodiment, the first contact hole CH1 passes through the first sub insulating layer 461 , but is not formed in the second sub insulating layer 463 , and the third contact hole CH3 passes through the first sub insulating layer 461 . Although it is exemplified that a portion of the second sub insulating layer 463 is formed through the , the structure of the first and third contact holes CH1 and CH3 after the mask process in FIG. 7I is limited to this embodiment. no.

Thereafter, the first electrode 770 of FIG. 5B is formed on the second insulating layer 460 in the pixel region II-II′, and the first electrode 470 and the first electrode 470 in the transistor region I-I′ are formed on the second insulating layer 460 . The spaced apart second electrodes 480 are formed (7j). In this embodiment, the second electrode 480 is exemplified on the second dummy metal layer DM2 formed on the same layer as the first electrode 470 , but the second dummy metal layer DM2 is not formed. In this state, the second electrode 480 may be formed on the same layer as the first electrode 470 .

Thereafter, as shown in FIG. 7K , a third insulating layer 490 is formed on the second insulating layer 460 to cover the first and second electrodes 470 and 480 , and an inorganic material, an organic material, or an organic material layer and an inorganic material It may consist of a laminate of layers.

In the process of forming the third insulating layer 490 , a third insulating layer 490 may also be formed in the first and third through holes CH1 and CH3 , and are formed in the first and third through holes CH1 and CH3 . The third insulating layer 490 to be used is removed. In the process of removing the third insulating layer 490 formed in the first and third through holes CH1 and CH3, the first and third through holes CH1 and CH3 may be formed deeper, and the first conductor The flower part 443 is exposed through the first through hole CH1 , and the dummy semiconductor DS is exposed through the third through hole CH3 .

A second contact hole CH2 is formed in a region of the third insulating layer 490 overlapping the second electrode 480 , and the second electrode 480 is exposed through the second contact hole CH2 .

Thereafter, as shown in FIG. 7L , a third electrode 500 is formed on the third insulating layer 490 and a first connection electrode ( BR1) is formed along the first and second contact holes CH1 and CH2, and the second connection electrode BR2 connecting the third electrode 500 and the second conductive part 445 is connected to the third contact hole ( CH3) is formed.

In the above, an example in which the non-overlapping structure between the gate electrode 420 and the first and second conductor portions 443 and 445 of the present specification is applied to a case in which a liquid crystal display panel including a thin film transistor having a bottom gate structure is manufactured has been described. . The non-overlapping structure between the gate electrode 420 and the first and second conductor parts 443 and 445 of the present specification can be applied to implement a thin film transistor having a top gate structure, and the thin film transistor having a top gate structure is Liquid crystal display panel It can be applied to an organic light emitting display panel.

8 is a cross-sectional view illustrating an example of a thin film transistor having a bottom gate structure applied to a display panel according to an embodiment of the present specification.

The thin film transistor having the bottom gate structure of FIG. 8 includes a substrate 810 , a semiconductor layer 820 formed on the substrate 810 , an active layer 830 , a first insulating layer 840 , a gate electrode 850 , and a second An insulating layer 860 may be included. In addition, the semiconductor layer 820 , the active layer 830 , and the gate electrode 850 may constitute one thin film transistor TR. A buffer layer may be further formed on the substrate 810 .

Glass or plastic may be used as the substrate 810 . As the plastic, a transparent plastic having a flexible property, for example, polyimide may be used. When polyimide is used as the substrate 410 , when a high-temperature deposition process is performed on the substrate 810 , a heat-resistant polyimide capable of withstanding a high temperature may be used.

The semiconductor layer 820 is patterned and formed on the substrate 810 , and may include an oxide semiconductor material. For example, the semiconductor layer 820 may include at least one of an oxide semiconductor material such as IGZO (InGaZnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, or the like. However, it may include other oxide semiconductor materials known in the art.

The active layer 830 is formed on the substrate 810 to cover the semiconductor layer 820 , and includes a channel portion 831 that is a region overlapping the semiconductor layer 820 , and a conductive portion that does not overlap the semiconductor layer 820 . (833, 835), the first conductive portion 833 is formed on one side of the channel portion 831 with the channel portion 831 interposed therebetween, and the second conductive portion (831) is formed on the other side of the channel portion 831. 835) is formed.

Accordingly, the channel portion 831 , the first conductive portion 833 , and the second conductive portion 835 are formed on the same layer using the same material, and the first conductive portion 833 extends from one side of the channel portion 831 . and the second conductive portion 835 extends from the other side of the channel portion 831 .

The first and second conductive parts 833 and 835 may be formed by conducting an active material layer by an exposure process using the gate electrode 850 as a mask.

An ITO-based oxide semiconductor material may be used as the active layer 830 , but the material of the active layer 830 is not limited thereto, and may include other oxide semiconductor materials known in the art.

One of the conductive portions 833 and 835 becomes a source region, and the other becomes a drain region.

The first insulating layer 840 is formed on the substrate 810 to cover the active layer 830 , protects the active layer 830 , and may be expressed as a gate insulating layer.

The first insulating layer 840 may include at least one of silicon oxide and silicon nitride. However, the material of the second insulating layer 840 is not limited to the embodiment of the present specification, and may include other insulating materials and may have a single layer structure or a multilayer structure.

In the present embodiment, the gate electrode 850 may be formed to cover the entire upper portion of the active layer 830 , but is not limited thereto, and may be formed on a portion of the upper surface of the active layer 830 . For example, the gate electrode 850 may be formed only on the channel portion 831 of the active layer 830 .

The gate electrode 850 is formed on the first insulating layer 840 .

The gate electrode 850 is an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, molybdenum ( Mo) or a molybdenum-based metal such as a molybdenum alloy, may include at least one of chromium (Cr), tantalum (Ta), neodium (Nd), and titanium (Ti). The gate electrode 850 may have a multilayer structure including at least two conductive films having different physical properties.

The gate electrode 850 at least partially overlaps the active layer 830 , overlaps the channel portion 831 of the active layer 830 , and also overlaps the semiconductor layer 820 .

Accordingly, the semiconductor layer 820 , the channel portion 831 , and the gate electrode 850 are aligned in a line, and the gate electrode 850 does not overlap the first and second conductive portions 833 and 835 .

As such, since the gate electrode 850 does not overlap the first and second conductive parts 833 and 835 , a parasitic capacitor between the gate electrode 850 and the first and second conductive parts 833 and 835 . is suppressed, and thus, it is possible to prevent a difference in pixel charging characteristics from being caused by the parasitic capacitor, and to solve problems of luminance non-uniformity and image quality degradation.

A second insulating layer 860 is formed on the first insulating layer 840 to cover the gate electrode 860 , and may be expressed as an interlayer insulating layer.

The second insulating layer 860 is made of an insulating material, and may be made of an organic material, an inorganic material, or a laminate of an organic material layer and an inorganic material layer.

As in the present embodiment, the first and second conductive parts 833 and 835 are conductively formed by an exposure process using the gate electrode 850 as a mask, and the gate electrode 850 of the active layer 830 is formed. Only regions that do not overlap with Accordingly, the gate electrode 850 and the first and second conductors 833 and 835 do not overlap each other.

A display panel, a method for manufacturing the same, and a display device including the same according to the present specification may be described as follows.

A display panel according to an example of the present specification includes a thin film transistor formed on a substrate, and the thin film transistor is formed on the substrate, and includes a channel portion, a first conductor portion extending to one side of the channel portion, and the other side of the channel portion. an active layer including a second conductive portion; and a semiconductor layer formed on a substrate to overlap the channel portion, and a gate electrode formed to not overlap the first and second conductive portions on the substrate.

According to an example of the present specification, the active layer is formed on the gate electrode, and the semiconductor layer is formed on the active layer.

According to an example of the present specification, the active layer is formed on the semiconductor layer, and the gate electrode is formed on the active layer.

According to an example of the present specification, the semiconductor layer does not overlap the first conductive portion and the second conductive portion.

According to an example of the present specification, the active layer is formed of a transparent conductive oxide having a different etch selectivity from a material forming the semiconductor layer.

According to an example of the present specification, the first insulating film formed between the gate electrode and the active layer, the first and second conductive parts, and the second insulating film formed on the first insulating film to cover the semiconductor layer, the second insulating film on the first electrode formed on the , a second electrode formed on the second insulating film to be spaced apart from the first electrode, a third insulating film formed on the second insulating film to cover the first and second electrodes, and on the third insulating film and a third electrode formed thereon.

According to an example of the present specification, a first contact hole passing through the second and third insulating layers to be connected to the first conductor portion, a second contact hole passing through the third insulating layer to expose the second electrode, and the second and second 3 A third contact hole connected to the second conductive part through the insulating layer, a first connection electrode formed along the first and second contact holes to connect the second electrode and the first conductive part, and a third contact hole and a second connection electrode that is formed along and connects the third electrode and the second conductor.

According to an example of the present specification, a dummy semiconductor layer formed on the second conductor to be spaced apart from the semiconductor layer may be further included, and the second connection electrode may be connected to the dummy semiconductor layer.

According to an example of the present specification, a first dummy metal layer formed on the same layer as the gate electrode and spaced apart from the gate electrode is further included, and the first insulating layer includes a dummy hole formed in a region overlapping the first dummy metal layer. and the second conductive portion may extend to the dummy hole to be connected to the first dummy metal layer.

According to an example of the present specification, the second electrode may be formed on the same layer as the first electrode.

According to an example of the present specification, a second dummy metal layer formed to be spaced apart from the first electrode on the same layer as the first electrode may be further included, and the second electrode may be formed on the second dummy metal layer.

A method of manufacturing a display panel according to an example of the present specification includes the steps of forming a pattern on a substrate, forming a first insulating layer on the substrate to cover the gate electrode, and sequentially active on the first insulating layer. forming a layer and a semiconductor layer, wherein the active layer includes a channel portion and first and second conductive portions formed to face each other with the channel portion interposed therebetween, and the gate electrode has a ratio of the first and second conductive portions to the first and second conductive portions. overlap

According to an example of the present specification, the semiconductor layer does not overlap the first conductive portion and the second conductive portion.

According to an example of the present specification, the forming of the active layer and the semiconductor layer may include forming an active material layer on the first insulating film, forming a semiconductor material layer on the active material layer, and on the semiconductor material layer. Forming a photoresist, performing an exposure process using a gate electrode as a mask on the active material layer to form a channel portion and first and second conductive portions, and a photoresist pattern formed by patterning the photoresist and forming a semiconductor layer through an etching process using a mask.

According to an example of the present specification, the active material layer is formed of a transparent conductive oxide having a different etch selectivity from the semiconductor material layer.

According to an example of the present specification, forming a second insulating film on the first insulating film to cover the active layer and the semiconductor layer, forming the first and second electrodes spaced apart on the second insulating film, the first and forming a third insulating film on the second insulating film to cover the second electrode, and forming a third electrode on the third insulating film.

A display device according to an example of the present specification includes a display panel including gate lines, data lines, and pixels disposed at intersections of the gate lines and the data lines, and a gate driver supplying a scan signal to the gate lines. , and a data driver supplying a data voltage to the data lines, wherein the display panel is a display panel according to an exemplary embodiment of the present specification.

Features, structures, effects, etc. described in various examples of the present specification are included in at least one example of the present specification, and are not necessarily limited to only one example. Furthermore, features, structures, effects, etc. illustrated in at least one example of the present specification can be combined or modified with respect to other examples by those of ordinary skill in the art to which the technical idea of the present specification pertains. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the technical scope or scope of the present specification.

The present specification described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which this specification belongs that various substitutions, modifications, and changes are possible without departing from the technical spirit of the present specification. It will be clear to those who have the knowledge of Therefore, the scope of the present specification is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present specification.

400: display panel 410: substrate
420: gate electrode 430: first insulating film
440: active layer 441: channel part
443: first conductive portion 445: second conductive portion
450: semiconductor layer 460: second insulating film
461: first sub insulating film 463: second sub insulating film
470: first electrode 480: second electrode
490: third insulating film 500: third electrode
BR1: first connection electrode BR2: second connection electrode
CH1: first contact hole CH2: second contact hole
CH3: 3rd contact hole DH: dummy hole
DM1: first dummy metal film DM2: second dummy metal film
DS: dummy semiconductor layer

Claims (17)

A thin film transistor formed on a substrate,
The thin film transistor,
an active layer formed on the substrate and including a channel part, a first conductive part extending to one side of the channel part, and a second conductive part extending to the other side of the channel part;
a semiconductor layer formed on the substrate to overlap the channel portion; and
and a gate electrode formed on the substrate so as not to overlap the first and second conductive portions. The method of claim 1,
The active layer is formed on the gate electrode, and the semiconductor layer is formed on the active layer. The method of claim 1,
The active layer is formed on the semiconductor layer, and the gate electrode is formed on the active layer. The method of claim 1,
and the semiconductor layer does not overlap the first and second conductive portions. 3. The method of claim 2,
The active layer is formed of a transparent conductive oxide having a different etch selectivity from a material forming the semiconductor layer. 3. The method of claim 2,
a first insulating layer formed between the gate electrode and the active layer;
a second insulating film formed on the first insulating film so as to cover the first and second conductive parts and the semiconductor layer;
a first electrode formed on the second insulating layer;
a second electrode formed on the second insulating layer to be spaced apart from the first electrode;
a third insulating layer formed on the second insulating layer to cover the first and second electrodes; and
and a third electrode formed on the third insulating layer. 7. The method of claim 6,
a first contact hole passing through the second and third insulating layers and connected to the first conductive part;
a second contact hole penetrating the third insulating layer and exposing the second electrode;
a third contact hole passing through the second and third insulating layers and connected to the second conductor;
a first connection electrode formed along the first and second contact holes to connect the second electrode and the first conductor portion; and
and a second connection electrode formed along the third contact hole to connect the third electrode and the second conductor portion. 8. The method of claim 7,
and a dummy semiconductor layer formed on the second conductor portion to be spaced apart from the semiconductor layer, wherein the second connection electrode is connected to the dummy semiconductor layer. 8. The method of claim 7,
Further comprising a first dummy metal film formed on the same layer as the gate electrode and spaced apart from the gate electrode,
the first insulating layer includes a dummy hole formed in a region overlapping the first dummy metal layer;
and the second conductive portion extends to the dummy hole and is connected to the first dummy metal layer. 7. The method of claim 6,
The second electrode is formed on the same layer as the first electrode. 7. The method of claim 6,
Further comprising a second dummy metal film formed on the same layer as the first electrode and spaced apart from the first electrode,
and the second electrode is formed on the second dummy metal layer. patterning a gate electrode on a substrate;
forming a first insulating layer on the substrate to cover the gate electrode; and
sequentially forming an active layer and a semiconductor layer on the first insulating film;
The active layer includes a channel portion, and first and second conductive portions formed to face each other with the channel portion interposed therebetween,
The method of claim 1, wherein the gate electrode does not overlap the first and second conductive parts. 13. The method of claim 12,
The method of claim 1, wherein the semiconductor layer does not overlap the first and second conductive parts. The method of claim 12, wherein the forming of the active layer and the semiconductor layer comprises:
forming an active material layer on the first insulating layer;
forming a semiconductor material layer on the active material layer;
forming a photoresist on the semiconductor material layer;
forming the channel portion and the first and second conductive portions by performing an exposure process on the active material layer using the gate electrode as a mask; and
and forming the semiconductor layer through an etching process formed by patterning the photoresist and using the photoresist pattern as a mask. 15. The method of claim 14,
The method of claim 1, wherein the active material layer is formed of a transparent conductive oxide having a different etch selectivity from that of the semiconductor material layer. 13. The method of claim 12,
forming a second insulating layer on the first insulating layer to cover the active layer and the semiconductor layer;
forming first and second electrodes spaced apart from each other on the second insulating layer;
forming a third insulating layer on the second insulating layer to cover the first and second electrodes; and
and forming a third electrode on the third insulating layer. a display panel including gate lines, data lines, and pixels disposed at intersections of the gate lines and the data lines;
a gate driver supplying a scan signal to the gate lines; and
a data driver supplying a data voltage to the data lines;
The display panel is
The display panel of any one of claims 1 to 11, the display device.

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