KR20200016073A - Thin film trnasistor substrate, method for manufacturing the same and display device comprising the same - Google Patents

Abstract

One embodiment of the present invention provides a thin film transistor substrate which comprises: a substrate; a light blocking layer on the substrate; a buffer layer on the light blocking layer; a semiconductor layer on the buffer layer; and a gate electrode spaced apart from the semiconductor layer and at least partially overlapping the semiconductor layer. The semiconductor layer comprises a channel part and a conducting part. A part of the conducting part is a source region, and the other part thereof is a drain region. The light blocking layer overlaps the channel layer of the semiconductor layer and does not overlap the conducting part. According to the present invention, a conducting process of a semiconductor can be simplified.

Description

Thin film transistor substrate, method of manufacturing the same, and display device including the same {THIN FILM TRNASISTOR SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE COMPRISING THE SAME}

The present invention relates to a thin film transistor substrate, a method of manufacturing the same, and a display device including the thin film transistor substrate.

Transistors are widely used as switching devices or driving devices in the field of electronic devices. In particular, since a thin film transistor may be manufactured on a glass substrate or a plastic substrate, the thin film transistor is a switching element of a display device such as a liquid crystal display device or an organic light emitting device. It is widely used.

The thin film transistor includes an amorphous silicon thin film transistor in which amorphous silicon is used as the active layer, a polycrystalline silicon thin film transistor in which polycrystalline silicon is used as the active layer, and an oxide semiconductor are used as the active layer, based on the material constituting the active layer. It may be classified into an oxide semiconductor thin film transistor.

Since amorphous silicon may be deposited in a short time to form an active layer, the amorphous silicon thin film transistor (a-Si TFT) has an advantage of short manufacturing process time and low production cost. On the other hand, since the mobility (mobility) is low, the current driving ability is not good, and the threshold voltage is changed, the amorphous silicon thin film transistor has a disadvantage that the use of the active matrix organic light emitting device (AMOLED) and the like is limited.

A polycrystalline silicon thin film transistor (poly-Si TFT) is formed by depositing amorphous silicon and then crystallizing the amorphous silicon. Since the process of manufacturing amorphous polycrystalline thin film transistor requires amorphous silicon crystallization, the manufacturing cost increases due to the increase in the number of processes, and the polycrystalline silicon thin film transistor is applied to large area devices because the crystallization process is performed at high process temperature. There is a difficulty in becoming. In addition, due to the polycrystalline characteristics, it is difficult to secure uniformity of the polycrystalline silicon thin film transistor.

Since the oxide constituting the active layer can be formed at a relatively low temperature, has high mobility, and has a large resistance change according to the oxygen content, the oxide semiconductor TFT has a desired physical property. It has the advantage that it can be easily obtained. In addition, because of the nature of the oxide, the oxide semiconductor is transparent, it is also advantageous to implement a transparent display.

In order to apply an oxide semiconductor to a thin film transistor, it is necessary to conductor a part of an oxide semiconductor layer made of an oxide semiconductor. Conductorization is carried out in various ways such as plasma treatment, ultraviolet treatment. In order to reduce the manufacturing process cost of an oxide semiconductor thin film transistor, it is necessary to simplify a conductorization process.

1. Korean Patent Publication No. 10-2018-0062278 (published June 8, 2018): a transistor substrate, an organic light emitting display panel using the same and a method of manufacturing the same, and an organic light emitting display device using the same

An embodiment of the present invention is to provide a thin film transistor substrate including an oxide semiconductor layer having a conductive portion conductorized by light irradiation using a light blocking layer as a mask.

Another embodiment of the present invention is to provide a method of manufacturing a thin film transistor substrate for conducting a portion of the oxide semiconductor layer by light irradiation using the light blocking layer as a mask.

Another embodiment of the present invention is to provide a display device including a thin film transistor including an oxide semiconductor layer having a conductive part conductored by light irradiation using a light blocking layer as a mask.

An embodiment of the present invention for achieving the above-described technical problem, a substrate, a light blocking layer on the substrate, a buffer layer on the light blocking layer, a semiconductor layer on the buffer layer and the semiconductor layer spaced at least partially overlapping the semiconductor layer A gate electrode, wherein the semiconductor layer includes a channel portion and a conductorization portion, a portion of the conductorization portion is a source region, another portion is a drain region, and the light blocking layer overlaps the channel portion of the semiconductor layer. The present invention provides a thin film transistor substrate that does not overlap with the conductive part.

The semiconductor layer includes an oxide semiconductor material.

The gate electrode overlaps the channel portion of the semiconductor layer and overlaps at least a portion of the conductorization portion.

The gate electrode overlaps the conductorization portion of the semiconductor layer to form a capacitor.

The semiconductor layer includes a first semiconductor layer on the substrate and a second semiconductor layer on the first semiconductor layer.

Another embodiment of the present invention includes a substrate, a light blocking layer on the substrate, a buffer layer on the light blocking layer, a pixel driver disposed on the buffer layer and including at least one thin film transistor, and a light emitting device connected to the pixel driver. The thin film transistor includes a semiconductor layer on a buffer layer and a gate electrode spaced apart from the semiconductor layer and at least partially overlapping the semiconductor layer, wherein the semiconductor layer includes a channel portion and a conductorization portion, and a part of the conductorization portion is a source region. The other portion is a drain region, and the light blocking layer overlaps the channel portion of the semiconductor layer, and does not overlap the conductorization portion.

The semiconductor layer includes an oxide semiconductor material.

The gate electrode overlaps the channel portion of the semiconductor layer and overlaps at least a portion of the conductorization portion.

The conductive part and the gate electrode overlapped with each other form a capacitor.

The semiconductor layer includes a first semiconductor layer on the substrate and a second semiconductor layer on the first semiconductor layer.

The light emitting device is an organic light emitting diode.

In another embodiment of the present invention, forming a light blocking layer on a substrate, forming a buffer layer on the light blocking layer, a semiconductor having a region overlapping with the light blocking layer on the buffer layer and a non-overlapping region Forming a layer, forming a gate electrode spaced apart from the semiconductor layer at least partially overlapping the semiconductor layer, and irradiating light onto the substrate on the light blocking layer side to overlap the light blocking layer of the semiconductor layer A method of manufacturing a thin film transistor substrate is provided, including the step of conductoring a region not in use.

The semiconductor layer includes an oxide semiconductor material.

The light irradiation may be performed before or after the forming of the gate electrode.

The light is ultraviolet light.

The gate electrode overlaps a region overlapping with the light blocking layer in the semiconductor layer and overlaps at least a portion of a region not overlapping with the light blocking layer.

According to one embodiment of the present invention, since part of the semiconductor layer can be easily conductored by light irradiation using the light blocking layer as a mask, the conductorization process of the semiconductor layer is simplified and the cost of conductorization is reduced.

In a conventional self-aligned structure in which a gate electrode is used as a mask for conductorization of a semiconductor layer, when a capacitor electrode connected to the gate electrode is to be formed, a separate capacitor is formed after the gate electrode is formed. An electrode was formed and the gate electrode and the capacitor electrode were connected using a separate bridge. On the other hand, according to an embodiment of the present invention, since the light shielding layer is used as a mask for conductorization, the gate electrode of the thin film transistor does not need to be used as a mask, and the area of the gate electrode is extended so that a part of the gate electrode is directly It can be one electrode of a capacitor. Thus, in accordance with one embodiment of the present invention, the capacitor formation process can be simplified, and the capacitor formation cost can be reduced.

In addition to the effects mentioned above, other features and advantages of the present invention will be described below, or will be clearly understood by those skilled in the art from such description and description.

1 is a cross-sectional view of a thin film transistor substrate according to an exemplary embodiment of the present invention.
2 is a cross-sectional view of a thin film transistor substrate according to another exemplary embodiment of the present invention.
3 is a cross-sectional view of a thin film transistor substrate according to another exemplary embodiment of the present invention.
4 is a cross-sectional view of a thin film transistor substrate according to another exemplary embodiment of the present invention.
5 is a cross-sectional view of a thin film transistor substrate according to a comparative example.
6 is a schematic diagram of a display device according to another exemplary embodiment of the present invention.
FIG. 7 is a circuit diagram of one pixel of FIG. 6.
8 is a plan view of the pixel of FIG. 7.
FIG. 9 is a cross-sectional view taken along line II ′ of FIG. 8.
FIG. 10 is a cross-sectional view taken along line II-II 'of FIG. 8.
FIG. 11 is a cross-sectional view taken along line III-III ′ of FIG. 8.
12A is a plan view of a pixel of a display device according to a comparative example.
FIG. 12B is a cross-sectional view taken along line IV-IV ′ of FIG. 12A.
13A and 13G are diagrams illustrating a manufacturing process of a thin film transistor substrate according to an exemplary embodiment.
14A and 14B illustrate a process chart of manufacturing a thin film transistor substrate according to another exemplary embodiment.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, only the present embodiments to make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to inform those who have the scope of the invention. The invention is only defined by the scope of the claims.

Shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing embodiments of the present invention are exemplary, and thus the present invention is not limited to the items shown in the drawings. Like elements may be referred to by like reference numerals throughout the specification. In addition, in describing the present invention, when it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

In the case where 'comprises', 'haves', 'consists of' and the like mentioned in the present specification are used, other parts may be added unless the expression 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

In interpreting a component, it is interpreted to include an error range even if there is no separate description.

For example, when the positional relationship between two parts is described as 'on', 'upper', 'lower', 'beside', etc., the expression 'directly' or 'direct' is used. Unless otherwise specified, one or more other parts may be located between the two parts.

The spatially relative terms "below, beneath", "lower", "above", "upper", etc., as shown in the figures, are one element or component. And can be used to easily describe the correlation of the device with other devices or components. Spatially relative terms are to be understood as terms that include different directions of the device in use or operation in addition to the directions shown in the figures. For example, when flipping a device shown in the figure, a device described as "below" or "beneath" of another device may be placed "above" of another device. Thus, the exemplary term "below" can encompass both an orientation of above and below. Likewise, the exemplary terms “up” or “up” may include both up and down directions.

In the case of a description of a temporal relationship, for example, if the temporal after-term relationship is described as 'after', 'following', 'after', 'before', or the like, 'directly' or 'direct' It may also include non-contiguous cases unless the expression is used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be a second component within the technical spirit of the present invention.

The term "at least one" should be understood to include all combinations which can be presented from one or more related items. For example, the meaning of "at least one of the first item, the second item, and the third item" means two items of the first item, the second item, or the third item, as well as two of the first item, the second item, and the third item, respectively. It can mean a combination of all items that can be presented from more than one.

The features of each of the various embodiments of the invention may be combined or combined with one another, in whole or in part, and various interlocking and driving technologies are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in an association. It may be.

In embodiments of the present invention, the source electrode and the drain electrode are only distinguished for convenience of description, and the source electrode and the drain electrode may be interchanged. Specifically, the source electrode of one embodiment may be used as the drain electrode, the drain electrode may be used as the source electrode. Also, the source electrode of one embodiment may be a drain electrode in another embodiment, and the drain electrode of one embodiment may be a source electrode in another embodiment.

In the embodiments of the present invention, for convenience of description, the source region and the source electrode are distinguished and the drain region and the drain electrode are distinguished, but embodiments of the present invention are not limited thereto. The source region may be a source electrode and the drain region may be a drain electrode. In addition, the source region may be a drain electrode, and the drain region may be a source electrode.

 Hereinafter, a thin film transistor, a method of manufacturing the same, and a display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are shown in different drawings.

1 is a cross-sectional view of a thin film transistor substrate 100 according to an embodiment of the present invention.

The thin film transistor substrate 100 according to the exemplary embodiment of the present invention may include a substrate 110, a light blocking layer LS on the substrate 110, a buffer layer 120 on the light blocking layer LS, and a semiconductor layer on the buffer layer 120. The gate electrode 160 is spaced apart from the semiconductor layer 130 and at least partially overlaps the semiconductor layer 130. The semiconductor layer 130 includes a channel portion 131 and conductors 132 and 233, some of the conductors 132 and 133 are source regions 132, and others are drain regions 133. . The light blocking layer LS overlaps the channel portion 131 of the semiconductor layer 130 and does not overlap the conductorization portions 132 and 133.

Hereinafter, the components of the thin film transistor substrate 100 according to the exemplary embodiment of the present invention will be described in detail.

Glass or plastic may be used as the substrate 110. As the plastic, a transparent plastic having flexible properties such as polyimide may be used. When polyimide is used as the substrate 110, considering that a high temperature deposition process is performed on the substrate 110, a heat resistant polyimide that can withstand high temperatures may be used.

The light blocking layer LS is disposed on the substrate 110. According to the exemplary embodiment of the present invention, the light blocking layer LS overlaps the channel portion 131 of the semiconductor layer 130. The light blocking layer LS blocks the light incident to the thin film transistor substrate 100 to protect the semiconductor layer 130, and in particular, protects the channel portion 131.

In addition, the light blocking layer LS acts as a mask during the conductorization process of the semiconductor layer 130 by light irradiation during the manufacturing process of the thin film transistor substrate 100, thereby preventing the light blocking layer LS of the semiconductor layer 130. ) To prevent conductors from overlapping areas. As a result, the region overlapping with the light blocking layer LS of the semiconductor layer 130 is not conductive and becomes the channel portion 131. Therefore, according to the exemplary embodiment of the present invention, the light blocking layer LS does not overlap the conductive parts 132 and 133 of the semiconductor layer 130.

Any material capable of blocking light may be used as the material of the light blocking layer LS without limitation. For example, the light blocking layer LS may be made of metal.

Referring to FIG. 1, a buffer layer 120 is disposed on a substrate 110. The buffer layer 120 includes an insulating material such as silicon oxide and silicon nitride. The buffer layer 120 protects the semiconductor layer 130. In addition, the buffer layer 120 serves to planarize an upper portion of the substrate 110 on which the light blocking layer LS is disposed. The buffer layer 120 is also called a protective layer or an insulating layer.

The semiconductor layer 130 is disposed on the buffer layer 120. According to an embodiment of the present invention, the semiconductor layer 130 includes an oxide semiconductor material. For example, the semiconductor layer 130 may be formed of IZO (InZnO), IGO (InGaO), ITO (InSnO), IGZO (InGaZnO), IGZTO (InGaZnSnO), GZTO (GaZnSnO), and GZO (GaZnO). And at least one of an ITZO (InSnZnO) based oxide semiconductor material. However, one embodiment of the present invention is not limited thereto, and the semiconductor layer 130 may include other oxide semiconductor materials known in the art.

Referring to FIG. 1, the semiconductor layer 130 may include a channel portion 131 overlapping the light blocking layer LS and conductive parts 132 and 133 not overlapping the light blocking layer LS. The semiconductor layer 130 has at least two conductorization parts 132 and 133 spaced apart from each other with the channel part 131 interposed therebetween.

Some of the conductorization units 132 and 133 become the source region 132, and other portions become the drain region 133. The source region 132 and the drain region 133 are spaced apart from each other with the channel portion 131 interposed therebetween. According to an embodiment of the present invention, the source region 132 may be referred to as a source electrode, and the drain region 133 may be referred to as a drain electrode.

The gate insulating layer 140 is disposed on the semiconductor layer 130. The gate insulating layer 140 protects the semiconductor layer 130. The gate insulating layer 140 may include at least one of silicon oxide, silicon nitride, and a metal oxide. However, an embodiment of the present invention is not limited thereto, and the gate insulating layer 140 may include another insulating material. The gate insulating layer 140 may have a single film structure or may have a multilayer film structure.

Referring to FIG. 1, the gate insulating layer 140 may be disposed on the entire surface of the substrate 110 including the entire upper portion of the semiconductor layer 130. However, an embodiment of the present invention is not limited thereto, and the gate insulating layer 140 may be disposed on a portion of the semiconductor layer 130. For example, the gate insulating layer 140 may be disposed only on the channel portion 131 of the semiconductor layer 130.

The gate electrode 160 is disposed on the gate insulating layer 140.

The gate electrode 160 may be formed of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, or molybdenum ( It may include at least one of molybdenum-based metal such as Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta), neodium (Nd) and titanium (Ti). The gate electrode 160 may have a multilayer film structure including at least two conductive films having different physical properties.

The gate electrode 160 at least partially overlaps the semiconductor layer 130. Referring to FIG. 1, the gate electrode 160 overlaps the channel portion 131 of the semiconductor layer 130.

However, an embodiment of the present invention is not limited thereto, and the gate electrode 160 not only overlaps the channel portion 131 of the semiconductor layer 130, but also the conductorization portions 132 and 133 of the semiconductor layer 130. May overlap with at least some of them (see FIG. 4). In this case, a part of the gate electrode 160 overlapping the channel portion 131 of the semiconductor layer 130 serves to turn on / off the thin film transistor TR, and the conductorization portion 132 of the semiconductor layer 130 is formed. A portion of the gate electrode 160 overlapping the 133 forms a capacitor together with the conductors 132 and 133 of the semiconductor layer 130.

An interlayer insulating layer 150 is disposed on the gate electrode 160. The interlayer insulating layer 150 is made of an insulating material. The interlayer insulating layer 150 may be formed of an organic material, an inorganic material, or a laminate of an organic material layer and an inorganic material layer.

The thin film transistor substrate 100 according to the exemplary embodiment of the present invention includes a source electrode 170 connected to the source region 132 and a drain electrode 180 connected to the drain region 133. Referring to FIG. 1, the source electrode 170 and the drain electrode 180 are disposed on the interlayer insulating layer 150.

The source electrode 170 is connected to the channel portion 131 of the semiconductor layer 130 through the source region 132, and the drain electrode 180 is connected to the channel portion of the semiconductor layer 130 through the drain region 133. 131). Referring to FIG. 1, the source electrode 170 and the drain electrode 180 are connected to the source region 132 and the drain region 133 of the semiconductor layer 130 through contact holes formed in the interlayer insulating layer 150, respectively. It is connected to the channel unit 131, respectively.

However, an embodiment of the present invention is not limited thereto, and the source region 132 may be a source electrode and the drain region 133 may be a drain electrode without a separate source electrode 170 and a drain electrode 180. It may be.

 The source electrode 170 and the drain electrode 180 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodium (Nd), and copper ( Cu), and at least one of their alloys. The source electrode 170 and the drain electrode 180 may be made of a single layer made of a metal or an alloy of metal, respectively, or may be made of two or more layers.

In an exemplary embodiment, a portion of the thin film transistor substrate 100 except for the substrate 110 may be referred to as a thin film transistor TR. Therefore, the thin film transistor substrate 100 according to the exemplary embodiment of the present invention may include at least the light blocking layer LS, the semiconductor layer 130, the gate electrode 160, the source electrode 170, and the drain electrode 130. One thin film transistor TR is included.

2 is a cross-sectional view of a thin film transistor substrate 200 according to another exemplary embodiment of the present invention. Hereinafter, in order to avoid duplication, description of the already described components is omitted.

In the thin film transistor substrate 200 of FIG. 2, the semiconductor layer 130 has a multilayer structure as compared with the thin film transistor substrate 100 of FIG. 1. In detail, the semiconductor layer 130 includes a first semiconductor layer 130a on the substrate 110 and a second semiconductor layer 130b on the first semiconductor layer 130a. The first semiconductor layer 130a and the second semiconductor layer 130b may include the same semiconductor material or may include different semiconductor materials. When the first semiconductor layer 130a and the second semiconductor layer 130b include the same metal material, oxygen concentrations may be different from each other.

The first semiconductor layer 130a supports the second semiconductor layer 130b. Therefore, the first semiconductor layer 130a is also referred to as a "support layer". The channel portion 131 is formed in the second semiconductor layer 130b. Therefore, the second semiconductor layer 130b is also referred to as a "channel layer". However, an embodiment of the present invention is not limited thereto, and the channel unit 131 may also be formed in the first semiconductor layer 130a.

The first semiconductor layer 130a and the second semiconductor layer 130b may be formed by deposition. The first semiconductor layer 130a and the second semiconductor layer 130b may be formed by a continuous process.

A structure in which the semiconductor layer 130 includes the first semiconductor layer 130a and the second semiconductor layer 130b is also referred to as a bi-layer structure.

3 is a cross-sectional view of a thin film transistor substrate 300 according to another exemplary embodiment of the present invention.

The thin film transistor substrate 300 of FIG. 3 further includes a connection electrode 185 disposed on the interlayer insulating layer 150 and connected to the gate electrode 160 in comparison with the thin film transistor substrate 100 of FIG. 1. The connection electrode 185 may be connected to other elements or wires disposed on the thin film transistor substrate 300 (see FIGS. 8 and 10). Although not shown, the connection electrode 185 may be connected to other devices on the substrate 110 to allow the gate electrode 160 to be connected to other devices. Alternatively, the connection electrode 185 is connected to a wiring (not shown) formed on the thin film transistor substrate 300 so that the gate electrode 160 is connected to the wiring (not shown).

In addition, although not illustrated, the drain electrode 180 may be connected to the light blocking layer LS as well as the channel portion 131 of the semiconductor layer 130 (see FIGS. 9 and 11). However, an embodiment of the present invention is not limited thereto, and the light blocking layer LS may be connected to the source electrode 170.

4 is a cross-sectional view of a thin film transistor substrate 400 according to another exemplary embodiment of the present invention.

Referring to FIG. 4, the gate electrode 160 extends over the upper portion of the channel portion 131 of the semiconductor layer 130 and the upper portion of the conductorization portions 132 and 133.

In detail, the gate electrode 160 overlaps the channel portion 131 of the semiconductor layer 130, and overlaps at least a portion of the conductorization portions 132 and 133 of the semiconductor layer 130. The gate electrode 160 may overlap the conductors 132 and 133 of the semiconductor layer 130 to form a capacitor Cap.

In this case, a part of the gate electrode 160 overlapping with the channel part 131 serves to turn on / off the thin film transistor TR, and the other part of the gate electrode 160 overlapping with the conductorization parts 132 and 133. A portion of the semiconductor layer 130 may form capacitance together with the conductors 132 and 133 of the semiconductor layer 130.

Referring to FIG. 4, the drain region 133 overlapping with the gate electrode 160 of the conductive parts 132 and 133 of the semiconductor layer 130 becomes the first electrode 511 of the capacitor Cap, and the drain region. A portion of the gate electrode 160 overlapping the 133 becomes the second electrode 512 of the capacitor Cap, and the capacitor Cap is formed by the drain region 133 and a part of the gate electrode 160. .

In the thin film transistor substrate 400 shown in FIG. 4, the source region 132 of the semiconductor layer 130 is a source electrode, and the drain region 133 is a drain electrode.

The connection electrode 185 is disposed on the interlayer insulating layer 150.

The connection electrode 185 is connected to the gate electrode 160 to apply a gate signal or voltage to the gate electrode 160.

The passivation layer 155 is disposed on the connection electrode 185. The passivation layer 155 is made of an insulating material and protects the thin film transistor TR. The passivation layer 155 may be formed of an organic material, an inorganic material, or a laminate of an organic material layer and an inorganic material layer. The upper portion of the thin film transistor TR is flattened by the passivation layer 155. Therefore, the protective film 155 is also called a planarization film.

5 is a cross-sectional view of a thin film transistor substrate 501 according to a comparative example.

In the thin film transistor substrate 501 illustrated in FIG. 5, after the gate electrode 160 is patterned, an area other than the channel portion 131 of the semiconductor layer 130 is formed using the patterned gate electrode 160 as a mask. It has a self-aligned structure for conductoring. In the self-aligned structure, since the gate electrode 160 is used as a mask for conductoring the semiconductor layer 130, the gate electrode 160 is patterned to correspond to the channel portion 131. The region overlapping the gate electrode 160 of the semiconductor layer 130 becomes the channel portion 131.

In the self-aligned structure illustrated in FIG. 5, a separate capacitor electrode 513 is formed to form a capacitor. In addition, the separate capacitor electrode 513 is connected to the gate electrode 160 through a separate bridge 165.

In detail, after the intermediate passivation layer 145 is formed on the gate electrode 160, a separate capacitor electrode 513 overlapping at least partially with the conductorization portions 132 and 133 of the semiconductor layer 130 is the intermediate passivation layer 145. ) And a separate bridge 165 to connect the gate electrode 160 and the separate capacitor electrode 513. Therefore, according to the comparative example, a process of forming a separate capacitor electrode 513 and a process of forming a separate bridge 165 are required to form a capacitor.

On the other hand, according to another embodiment of the present invention shown in FIG. 4, since the light shielding layer LS is used as a mask for conductorization, the gate electrode 160 is used as a mask for the channel portion 131. It doesn't work. Accordingly, the area of the gate electrode 160 may be extended so that a portion of the gate electrode 160 may overlap at least a portion of the conductorization units 132 and 133. As a result, a part (drain region) 133 of the conductorization parts 132 and 133 becomes one electrode 511 (first electrode) of the capacitor Cap, and a part of the gate electrode 160 becomes different from the capacitor Cap. It becomes one electrode 512 (2nd electrode), and the capacitor Cap is formed. As described above, according to another embodiment of the present invention, a process of forming a capacitor is simplified as compared with the comparative example. As a result, the cost of capacitor Cap can be reduced.

Hereinafter, a display device to which the thin film transistor substrates 100, 200, 300, and 400 described above may be applied will be described.

FIG. 6 is a schematic diagram of a display device 600 according to another exemplary embodiment of the present invention, FIG. 7 is a circuit diagram of one pixel 601 of FIG. 6, and FIG. 8 is a pixel diagram of the pixel 601 of FIG. 7. 9 is a cross-sectional view taken along line II ′ of FIG. 8, FIG. 10 is a cross-sectional view taken along line II-II ′ of FIG. 8, and FIG. 11 is a cross-sectional view taken along line III-III ′ of FIG. 8. to be.

According to another exemplary embodiment, the display device 600 includes a light blocking layer LS1, LS2, LS3 and LS4 on a substrate 110 and a substrate 100, and a light blocking layer LS1, LS2, LS3 and LS4 on a substrate 110. The light emitting device is connected to the buffer layer 120, the pixel driver PDC on the buffer layer 120, and the pixel driver PDC. The pixel driver PDC includes at least one thin film transistor TR1, TR2, TR3, and TR4.

The display device 600 according to another exemplary embodiment of the present invention includes an organic light emitting diode OLED as a light emitting device. Accordingly, the display device 600 according to another exemplary embodiment of the present invention is an organic light emitting display device, and includes gate lines GL, data lines DL, gate lines GL, and data lines DL. And an organic light emitting display panel 610 having a plurality of pixels 601 defined by the pixels.

In detail, the display device 600 according to another exemplary embodiment of the present invention sequentially sequentially the gate lines GL provided in the organic light emitting display panel 610 and the organic light emitting display panel 610 to output an image. A gate driver 620 for supplying a gate pulse GP, a data driver 630 and a gate driver 620 for supplying a data voltage to the data lines DL of the organic light emitting display panel 610; The controller 640 controls the data driver 630.

The controller 640 uses a timing signal supplied from an external system, for example, a vertical synchronizing signal, a horizontal synchronizing signal, a clock, and the like to control the gate control signal GCS and the data driver for controlling the gate driver 620. A data control signal DCS for controlling 630 is output. The controller 640 samples the input image data input from the external system and rearranges the input image data, and supplies the rearranged digital image data to the data driver 630.

The data driver 630 converts the image data Data input from the control unit 640 into an analog data voltage, so that one horizontal line of data is provided for each horizontal period in which the gate pulse GP is supplied to the gate line GL. The voltages Vdata are transmitted to the data lines DL.

The gate driver 620 sequentially supplies the gate pulse GP to the gate lines GL of the organic light emitting display panel 610 in response to the gate control signal GCS input from the controller 640. Accordingly, transistors disposed in each pixel 601 to which the gate pulse GP is input may be turned on to output an image to each pixel 601. The gate driver 620 may be formed independently of the organic light emitting display panel 610 to have a configuration electrically connected to the organic light emitting display panel 610 in various ways, and may be a gate mounted in the organic light emitting display panel 610. It may have a configuration of a gate in panel (GIP) method.

At least one of the data driver 630 or the gate driver 620 may be integrally formed with the controller 640.

The organic light emitting display panel 610 is formed by the gate lines GL to which the gate pulse GP is applied, the data lines DL to which the data voltage is applied, and the gate lines GL and the data lines DL. Pixels 601 are defined. Each of the pixels 601 includes at least one thin film transistor TR1, TR2, TR3, and TR4. According to another embodiment of the present invention, an oxide thin film transistor having a coplanar shape is used as the thin film transistors TR1, TR2, TR3, and TR4.

As illustrated in FIG. 7, each of the pixels 601 included in the organic light emitting display panel 610 includes an organic light emitting diode OLED and a pixel driver PDC for driving the organic light emitting diode OLED. ). In each of the pixels 601, signal lines DL, EL, GL [GL _n , GL _{n -1} ], PLA, PLB, SL, and SPL are provided to supply a driving signal to the pixel driver PDC. .

The data voltage Vdata is supplied to the data line DL, the gate pulse GP is supplied to the gate line GL, the first driving power source ELVDD is supplied to the power supply line PLA, and the driving power source is supplied. The second driving power supply EVSS is supplied to the line PLB, the reference voltage Vref is supplied to the sensing line SL, and the sensing pulse SP is supplied to the sensing pulse line SPL. The emission control signal EM is supplied to the line EL. Referring to FIGS. 7 and 8, when the gate line of the n-th pixel 601 is referred to as "GL _n ", the gate line of the neighboring n-th pixel 601 is "GL _{n -1} " and n The gate line “GL _{n −1} ” of the ₋₁ th pixel 601 serves as a sensing pulse line SPL of the n th pixel 601.

For example, as illustrated in FIG. 7, the pixel driver PDC includes a first thin film transistor TR1 (switching transistor) and a first thin film transistor TR1 connected to the gate line GLn and the data line DL. According to the data voltage Vdata transmitted through the switching transistor, the second thin film transistor TR2 (driving transistor) and the second thin film transistor TR2 that control the magnitude of the current output to the organic light emitting diode OLED. And a fourth thin film transistor TR3 (emission transistor) for controlling the light emission time of the light emitting diode) and a fourth thin film transistor TR4 (sensing transistor) for sensing the characteristics of the second thin film transistor TR2.

According to another embodiment of the present invention, the first thin film transistor TR1 is referred to as a "switching transistor", the second thin film transistor TR2 is referred to as a "drive transistor" and the third thin film transistor TR3 is "emitted". Transistor "and four thin film transistors TR4 are also called" sensing transistors. " However, another embodiment of the present invention is not limited thereto. The pixel driver PDC may be formed in various structures other than the structure shown in FIG. 7. The pixel driver PDC may include, for example, three or less thin film transistors, or may include five or more thin film transistors.

The first capacitor C1 is positioned between the gate electrode of the second thin film transistor TR2 and the pixel electrode of the organic light emitting diode OLED. The first capacitor C1 is also referred to as a storage capacitor Cst.

The second capacitor C2 is positioned between the terminal to which the first driving power source ELVDD is supplied among the terminals of the third thin film transistor TR3 and the pixel electrode 710 of the organic light emitting diode OLED.

The first thin film transistor TR1 is turned on by the gate pulse GP supplied to the gate line GLn, and the gate electrode of the second thin film transistor TR2 receives the data voltage Vdata supplied to the data line DL. To send.

The fourth thin film transistor TR4 is connected to the first node n1 and the sensing line SL between the second thin film transistor TR2 and the organic light emitting diode OLED, and is turned on or turned on by the sensing pulse SP. It is turned off and senses the characteristic of the second thin film transistor TR2 which is a driving transistor in the sensing period.

The second node n2 connected to the gate electrode of the second thin film transistor TR2 is connected to the first thin film transistor TR1. The first capacitor C1 is positioned between the second node n2 and the first node n1.

The third thin film transistor TR3 transfers the first driving power source ELVDD to the second thin film transistor TR2 or cuts off the first driving power source ELVDD according to the emission control signal EM. When the third thin film transistor TR3 is turned on, current is supplied to the second thin film transistor TR2 to output light from the organic light emitting diode OLED.

7 to 11, the pixel driver PDC is disposed on the buffer layer 120 and includes at least one thin film transistor TR1, TR2, TR3, and TR4.

 8 and 9, the thin film transistors TR1, TR2, TR3, and TR4 include the semiconductor layers 130 (A1, A2, A3, A4) and the semiconductor layers 130 (A1, A1) on the buffer layer 120. The gate electrodes G1, G2, G3, and G4 may be spaced apart from the semiconductor layers 130 (A1, A2, A3, and A4) and spaced apart from A2, A3, and A4. The semiconductor layer 130 (A1, A2, A3, A4) includes the channel portion 131 and the conductive portions 132 and 133, and some of the conductive portions 132 and 133 are the source region 132 (S1, S2, S3, and S4, and the other part is the drain region 133 (D1, D2, D3, D4). The light blocking layers LS1, LS2, LS3, and LS4 overlap the channel portions 131 of the semiconductor layers 130 (A1, A2, A3, and A4), and do not overlap the conductors 132 and 133.

7 and 8, the n−1th first light blocking layer LS1 may be the fourth light blocking layer LS4 of the nth pixel.

8 to 11, the source region 132 of the semiconductor layer 130 of the thin film transistors TR1, TR2, TR3, and TR4 serves as the source electrodes S1, S2, S3, and S4, and drains the drains. The region 133 may serve as the drain electrodes D1, D2, D3, and D4. In addition, the source electrodes S1, S2, S3, and S4 may be formed separately from the source region 132, and the drain electrodes D1, D2, D3, and D4 may be formed separately from the drain region 133.

According to another embodiment of the present invention, the semiconductor layer 130 (A1, A2, A3, A4) includes an oxide semiconductor material. For example, the semiconductor layers 130 (A1, A2, A3, and A4) may be formed of IZO (InZnO), IGO (InGaO), ITO (InSnO), IGZO (InGaZnO), IGZTO (InGaZnSnO), or GZTO. It may include at least one of a (GaZnSnO) -based, GZO (GaZnO) -based, and ITZO (InSnZnO) -based oxide semiconductor material. However, one embodiment of the present invention is not limited thereto, and the semiconductor layer 130 (A1, A2, A3, A4) may be made of other oxide semiconductor materials known in the art. In addition, any one of the semiconductor layers A1, A2, A3, and A4 may be made of amorphous silicon or polycrystalline silicon.

In addition, the semiconductor layers 130 (A1, A2, A3, and A4) may include a first semiconductor layer 130a on the substrate 110 and a second semiconductor layer 130b on the first semiconductor layer 130a. (See Figure 2). In this case, the first semiconductor layer 130a supports the second semiconductor layer 130b. The channel part 131 may be formed in the second semiconductor layer 130b. However, another embodiment of the present invention is not limited thereto. The channel unit 131 may also be formed in the first semiconductor layer 130a.

The gate insulating layer 140 is disposed on the semiconductor layer 130 (A1, A2, A3, A4). The gate insulating layer 140 may include at least one of silicon oxide, silicon nitride, and a metal oxide. The gate insulating layer 140 may have a single film structure or may have a multilayer film structure.

The gate electrode 160 is disposed on the gate insulating layer 140. The gate electrode 160 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, and molybdenum ( It may include at least one of molybdenum-based metal such as Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta), neodium (Nd) and titanium (Ti). The gate electrode 160 may have a multilayer film structure including at least two conductive films having different physical properties.

8 and 9, the gate electrode G2 of the second thin film transistor TR2 overlaps with the channel portion 131 of the semiconductor layer 130 (A2), and at least one of the conductive portions 132 and 133. It also overlaps with some. The conductors 132 and 133 and the gate electrode G2 overlapping each other form a capacitor. The capacitor thus formed is referred to as a first capacitor C1.

Specifically, the gate electrode G2 of the second thin film transistor TR2 not only overlaps the channel portion 131 of the semiconductor layer 130 (A2), but also the drain region 133 of the conductorization portions 132 and 133. Overlap with. The drain region 133 overlapping the gate electrode G2 becomes the first electrode C11 of the first capacitor C1, and a part of the gate electrode G2 overlapping the drain region 133 is the first capacitor C1. It becomes the second electrode C12 of C1, and the first capacitor C1 is formed by the drain region 133 and a part of the gate electrode G2.

As described above, part of the gate electrode G2 of the second thin film transistor TR2 and part of the conductor parts 132 and 133 of the semiconductor layer 130 (A2) form the first capacitor C1. There is no need for a separate additional process for forming one capacitor C1. As a result, process efficiency can be improved and process costs can be reduced.

Referring to FIG. 8, the second capacitor C2 overlaps the power supply line PLA. The second capacitor C2 includes a first electrode C21 extending from the drain region 133 of the second thin film transistor TR2 and a second electrode C22 connected to the power supply line PLA.

Referring to FIG. 9, an interlayer insulating layer 150 is disposed on an entire surface of the substrate 110 including the gate electrodes G1, G2, G3, and G4 and an upper portion of the emission line EL.

The interlayer insulating layer 150 is made of an insulating material. In detail, the interlayer insulating layer 150 may be formed of an organic material, an inorganic material, or may be formed of a laminate of an organic material layer and an inorganic material layer.

The connection electrode 185 is disposed on the interlayer insulating layer 150. 8 to 10, the connection electrode 185 connects the drain electrode D1 of the first thin film transistor TR1 and the gate electrode G2 of the second thin film transistor TR2. Accordingly, the data voltage Vdata supplied to the data line DL may be transmitted to the gate electrode D2 of the second thin film transistor TR2.

In addition, at least one of the source electrodes S1, S2, S3, and S4 and the drain electrodes D1, D2, D3, and D4 may be disposed on the interlayer insulating layer 150. A separate source electrode may not be formed when the source region 132 serves as a source electrode, and a separate drain electrode may not be formed even when the drain region 133 serves as a drain electrode.

8, 9, and 11, the drain electrode D2 of the second thin film transistor TR2 is formed on the interlayer insulating layer 150. The drain electrode D2 of the second thin film transistor TR2 is connected to the drain region 133 of the semiconductor layer 130 through any one contact hole H2 formed in the interlayer insulating layer 150.

In addition, the drain electrode D2 of the second thin film transistor TR2 is connected to the light blocking layer LS2 through the contact hole connecting portion 125 and another contact hole H3 formed in the interlayer insulating layer 150. 8 and 9, a part of the drain electrode D2 of the second thin film transistor TR2 may be the light blocking layer connection part 125.

The passivation layer 155 is disposed on the connection electrode 185 and the light blocking layer connection part 125. The passivation layer 155 covers and protects the thin film transistors TR1, TR2, TR3, and TR4, and planarizes an upper portion of the thin film transistors TR1, TR2, TR3, and TR4. The passivation layer 155 may be formed of at least one layer made of organic or inorganic material. The protective film 155 is also called a planarization film.

The organic light emitting diode OLED, which is a light emitting device, is disposed on the passivation layer 155. The organic light emitting diode OLED includes a pixel electrode 710, a light emitting layer 720, and a common electrode 730.

The pixel electrode 710 of the organic light emitting diode OLED is connected to the second thin film transistor TR2. The pixel electrode 710 of the organic light emitting diode OLED is connected to the drain electrode D2 of the second thin film transistor TR2 through the contact hole H1 formed in the passivation layer 155.

The organic light emitting diode OLED is surrounded by the bank 750. Each of the pixels 601 may be divided by the bank 750.

12A is a plan view of a pixel of the display device 801 according to a comparative example, and FIG. 12B is a cross-sectional view taken along line IV-IV ′ of FIG. 12A.

The display device 801 illustrated in FIG. 12A includes a first thin film transistor T1 as a switching transistor, a second thin film transistor T2 as a driving transistor, a third thin film transistor T3 as an emission transistor, and a sensing transistor 4. And a thin film transistor T4.

After patterning the gate electrode G2, the second thin film transistor TR2 uses the patterned gate electrode G2 as a mask to self-conduct a region other than the channel portion 131 of the semiconductor layer 130. It has a self-aligning structure. In order to use the gate electrode G2 as a mask during the conductorization of the semiconductor layer 130, the gate electrode G2 is patterned to correspond to the channel portion 131. As a result, the region overlapping with the gate electrode G2 of the semiconductor layer 130 becomes the channel portion 131.

12A and 12B, the drain region 133 of the semiconductor layer A2 of the second thin film transistor TR2 becomes the first electrode C11 of the first capacitor C1 and the gate electrode G2 and the gate electrode G2. The conductor pattern formed separately becomes the second electrode C12 of the first capacitor C1.

According to a comparative example, in order to form the second electrode C12 of the first capacitor C1, after the gate electrode G2 is formed, a conductor pattern overlapping the drain region 133 of the semiconductor layer A2 is separately formed. Is formed. The second electrode C12 of the first capacitor C1 formed as described above is connected to the gate electrode G2 through the bridge 165. Therefore, in the manufacturing process of the display device 801 according to the comparative example, in order to form the first capacitor C1, a process of forming the second electrode C12 and a process of forming the bridge 165 are separately required. Do.

12A and 12B, the drain electrode D1 of the first thin film transistor T1 and the gate of the second thin film transistor T2 are formed through the three contact holes CH1, CH2, and CH3 and the bridge 165. The electrode and the second electrode C12 of the first capacitor C1 are connected to each other.

In contrast, according to another exemplary embodiment of the present invention illustrated in FIG. 8, the light blocking layer LS2 under the second thin film transistor TR2 is used as a mask for conductorization, and the gate electrode G2 is used as a mask. Not used. Accordingly, the first capacitor C1 may be formed by extending the area of the gate electrode G2 so that a part of the gate electrode G2 overlaps with at least a part of the drain region 133.

In addition, according to another embodiment of the present invention, the contact hole CH3 for connecting the drain electrode D1 of the first thin film transistor TR1 and the second electrode C12 of the first capacitor is unnecessary. do. Instead, the drain electrode D1 of the first thin film transistor TR1 is located at the position where the contact hole CH3 for connecting the drain electrode D1 of the first thin film transistor TR1 and one electrode C12 of the first capacitor is located. ) And a contact hole for connecting the gate electrode G2 of the second thin film transistor TR2 to each other. As a result, the range of the contact hole formation possible region becomes wider, and the efficiency of the contact hole forming process and the accuracy of the process are improved.

As such, according to another embodiment of the present invention, the capacitor forming process may be simplified, and the accuracy of the process may be improved.

Hereinafter, a method of manufacturing the thin film transistor substrate 100 according to an embodiment of the present invention will be described with reference to FIGS. 13A to 13G. 13A to 13G illustrate a manufacturing process of a thin film transistor substrate 100 according to an exemplary embodiment of the present invention.

Referring to FIG. 13A, the light blocking layer LS is formed on the substrate 110.

Glass may be used as the substrate 110, and plastic that can be bent or bent may be used. An example of the plastic used as the substrate 110 is polyimide.

When plastic is used as the substrate 110, a process such as deposition and etching may be performed while the plastic substrate is disposed on a carrier substrate made of a highly durable material such as glass.

The light blocking layer LS may be made of a material that reflects or absorbs light. For example, the light blocking layer LS may be made of an electrically conductive material such as metal.

Referring to FIG. 13B, a buffer layer 120 is formed on a substrate 110 on which the light blocking layer LS is formed, and a semiconductor having a region overlapping with the light blocking layer LS and a non-overlapping region on the buffer layer 120. Layer 130 is formed.

The semiconductor layer 130 includes IZO (InZnO), IGO (InGaO), ITO (InSnO), IGZO (InGaZnO), IGZTO (InGaZnSnO), GZTO (GaZnSnO), GZO (GaZnO) and ITZO ( InSnZnO) -based oxide semiconductor material may include at least one. The semiconductor layer 130 may be formed by deposition or sputtering. Although the semiconductor layer 130 having the single layer structure is illustrated in FIG. 13B, an embodiment of the present invention is not limited thereto, and the semiconductor layer 130 may have a multilayer structure. For example, the semiconductor layer 130 may have a bi-layer structure of two layers (see FIG. 2).

Next, referring to FIG. 13C, a gate insulating layer 140 is formed on the semiconductor layer 130, and the gate electrode 160 spaced apart from the semiconductor layer 130 and at least partially overlaps the semiconductor layer 130. Is formed.

Referring to FIG. 13D, light L is irradiated onto the substrate 110 toward the light blocking layer LS. In this case, the light blocking layer LS serves as a mask to block the light L. Accordingly, the light L is not irradiated to the region overlapping the light blocking layer LS of the semiconductor layer 130, and the light L is irradiated only to the region not overlapping the light blocking layer LS. By the light L irradiation, a part of the semiconductor layer 130 is conductorized. As a result, a region of the semiconductor layer 130 that does not overlap the light blocking layer LS is conductorized.

As the light L, for example, ultraviolet rays can be used.

However, an embodiment of the present invention is not limited thereto, and light (L) irradiation may be performed even before forming the gate electrode 160. Specifically, light L irradiation may be performed before or after the step of forming the gate electrode 160.

FIG. 13E shows that the conductorization parts 132 and 133 are formed. One of the conductors 132 and 133 is the source region 132, and the other is the drain region 133.

The gate electrode 160 overlaps the channel portion 131, which is an area overlapping the light blocking layer LS, of the semiconductor layer 130, and is a conductive part 132, 133, which is an area not overlapping the light blocking layer LS. Overlap with at least part of).

The drain region 133 overlapping the gate electrode 160 among the conductive parts 132 and 133 of the semiconductor layer 130 becomes the first electrode 511 of the capacitor Cap and overlaps the drain region 133. A portion of the gate electrode 160 becomes the second electrode 512 of the capacitor Cap to form a capacitor Cap.

Referring to FIG. 13F, an interlayer insulating layer 150 is formed on the gate electrode 160. In this case, a contact hole CH is formed in the interlayer insulating layer 150.

Referring to FIG. 13G, a connection electrode 185 is formed on the interlayer insulating layer 150. The connection electrode 185 is connected to the gate electrode 160. By this process, the thin film transistor substrate 100 according to the exemplary embodiment of the present invention may be formed.

14A and 14B illustrate a process chart of manufacturing a thin film transistor substrate according to another exemplary embodiment.

Referring to FIG. 14A, after the light blocking layer LS is formed on the substrate 110 and the semiconductor layer 130 is formed on the light blocking layer LS, light L may be irradiated.

Referring to FIG. 14B, the conductor parts 132 and 133 of the semiconductor layer 130 are formed by the light L irradiation, and the channel part 131 is defined. Next, the gate insulating layer 140 and the gate electrode 160 may be formed.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field to which the present invention pertains without departing from the technical matters of the present invention. It will be apparent to those of ordinary knowledge. Therefore, the scope of the present invention is represented by the following claims, and it should be construed that all changes or modifications derived from the meaning, scope and equivalent concept of the claims are included in the scope of the present invention.

100, 200, 300, 400: thin film transistor substrate
600: display device
110: substrate 120: buffer layer
130: semiconductor layer 131: channel portion
132: source region 133: drain region
140: gate insulating film 150: interlayer insulating film
155: protective film 160: gate electrode
170: source electrode 180: drain electrode
710: pixel electrode 720: light emitting layer
730: common electrode 750: bank
OLED: organic light emitting diode

Claims (16)

Board;
A light blocking layer on the substrate;
A buffer layer on the light blocking layer;
A semiconductor layer on the buffer layer; And
A gate electrode spaced apart from the semiconductor layer and at least partially overlapping the semiconductor layer;
The semiconductor layer includes a channel portion and a conductorization portion,
Some of the conductive parts are source regions, others are drain regions,
The light blocking layer overlaps with the channel portion of the semiconductor layer and does not overlap with the conductorization portion.
Thin film transistor substrate. The method of claim 1,
And the semiconductor layer comprises an oxide semiconductor material. The method of claim 1,
And the gate electrode overlaps the channel portion of the semiconductor layer and overlaps at least a portion of the conductorization portion. The method of claim 1,
And the gate electrode overlaps the conductorization portion of the semiconductor layer to form a capacitor. The method of claim 1,
And the semiconductor layer comprises a first semiconductor layer on the substrate and a second semiconductor layer on the first semiconductor layer. Board;
A light blocking layer on the substrate;
A buffer layer on the light blocking layer;
A pixel driver disposed on the buffer layer and including at least one thin film transistor; And
And a light emitting device connected to the pixel driver.
The thin film transistor,
A semiconductor layer on the buffer layer; And
A gate electrode spaced apart from the semiconductor layer and at least partially overlapping the semiconductor layer;
The semiconductor layer includes a channel portion and a conductorization portion,
Some of the conductive parts are source regions, others are drain regions,
The light blocking layer overlaps with the channel portion of the semiconductor layer and does not overlap with the conductorization portion.
Display. The method of claim 6,
And the semiconductor layer comprises an oxide semiconductor material. The method of claim 6,
And the gate electrode overlaps the channel portion of the semiconductor layer and overlaps at least a portion of the conductorization portion. The method of claim 8,
And the capacitor and the gate electrode overlapping each other form a capacitor. The method of claim 6,
And the semiconductor layer includes a first semiconductor layer on the substrate and a second semiconductor layer on the first semiconductor layer. The method of claim 6,
The light emitting device is an organic light emitting diode. Forming a light blocking layer on the substrate;
Forming a buffer layer on the light blocking layer;
Forming a semiconductor layer on the buffer layer, the semiconductor layer having a region overlapping with the light blocking layer and a region not overlapping with each other;
Forming a gate electrode spaced apart from the semiconductor layer, the gate electrode at least partially overlapping the semiconductor layer; And
Irradiating light to the substrate on the side of the light blocking layer to conduct conductors in the semiconductor layer that do not overlap the light blocking layer.
Method of manufacturing a thin film transistor substrate. The method of claim 12,
And the semiconductor layer comprises an oxide semiconductor material. The method of claim 12,
The light irradiation is performed before or after the step of forming the gate electrode. The method of claim 12,
And said light is ultraviolet rays. The method of claim 12,
The gate electrode overlaps with a region overlapping with the light blocking layer in the semiconductor layer and overlaps with at least a portion of a region not overlapping with the light blocking layer.

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