KR102655208B1 - Thin film trnasistor having multi-layered gate insulating layer, method of manufacturing the same and display device comprising the same - Google Patents

Abstract

One embodiment of the present invention includes an active layer, a gate insulating film, and a gate electrode, wherein the gate insulating film includes the first insulating film and the second insulating film, and a region of the active layer overlapping with the gate electrode is the first insulating film. 1 is covered by an insulating film, and at least a portion of a region of the active layer that does not overlap the gate electrode is exposed from the first insulating film to provide a thin film transistor in contact with the second insulating film. One embodiment of the present invention also provides a method of manufacturing the thin film transistor and a display device including the thin film transistor.

Description

Thin film transistor having a multi-layer gate insulating film, manufacturing method thereof, and display device including the same

The present invention relates to a thin film transistor having a multilayer gate insulating film, a manufacturing method thereof, and a display device including the same. More specifically, the present invention relates to a thin film transistor having a gate insulating film including a first insulating film and a second insulating film, a method of manufacturing the thin film transistor, and a display device including the thin film transistor.

Since a thin film transistor can be manufactured on a glass or plastic substrate, it is used as a switching element or driving element in a display device such as a liquid crystal display device or an organic light emitting device. It is widely used.

Based on the material constituting the active layer, the thin film transistor is an amorphous silicon thin film transistor in which amorphous silicon is used as the active layer, a polycrystalline silicon thin film transistor in which polycrystalline silicon is used as the active layer, and an oxide semiconductor in which an oxide semiconductor is used as the active layer. It can be classified into an oxide semiconductor thin film transistor.

Since amorphous silicon can be deposited to form an active layer in a short time, amorphous silicon thin film transistors (a-Si TFTs) have the advantage of short manufacturing process time and low production costs. On the other hand, amorphous silicon thin film transistors have disadvantages that limit their use in active matrix organic light emitting devices (AMOLED), etc., due to low mobility, poor current driving ability, and changes in threshold voltage.

A polycrystalline silicon thin film transistor (poly-Si TFT) is made by depositing amorphous silicon and then crystallizing the amorphous silicon. Polycrystalline silicon thin film transistors have the advantages of high electron mobility, excellent stability, thin thickness, high resolution, and high power efficiency. Such polycrystalline silicon thin film transistors include low temperature polysilicon (LTPS) thin film transistors, or polysilicon thin film transistors. However, since a process for crystallizing amorphous silicon is required in the manufacturing process of a polycrystalline silicon thin film transistor, the number of processes increases, increasing manufacturing costs, and crystallization must occur at a high temperature. Therefore, it is difficult to apply polycrystalline silicon thin film transistors to large-area devices.

Oxide semiconductor TFTs, which have high mobility and a large change in resistance depending on the oxygen content, have the advantage of being able to easily obtain desired physical properties. In addition, the manufacturing cost is low because the oxide constituting the active layer can be formed at a relatively low temperature during the manufacturing process of the oxide semiconductor thin film transistor. Due to the nature of oxide, oxide semiconductors are transparent, so they are advantageous for implementing transparent displays.

Recently, the pixel density of high-resolution or mobile display devices has increased, and as many pixels are placed in a small space, the area of the thin film transistor is decreasing. Multilayer wiring is used for durability as well as electrical characteristics, and electrodes with a multilayer structure are used. However, when electrodes with a multi-layer structure are used, there are cases where defects such as seams occur in the insulating layer and the insulating properties deteriorate. Therefore, it is necessary to ensure the stability of the insulating layer to improve the quality of thin film transistors and display devices using them.

One embodiment of the present invention seeks to provide a thin film transistor having a gate insulating film with a multilayer structure.

Another embodiment of the present invention seeks to provide a gate insulating film that can prevent dielectric breakdown between a gate electrode and another electrode or wiring.

In another embodiment of the present invention, an object of the present invention is to provide a gate insulating film that can stably ensure insulation between the gate electrode and the source electrode or drain electrode, even if the gate electrode has a multi-layer stacked structure.

Another embodiment of the present invention seeks to provide a thin film transistor with improved stability and reliability.

Another embodiment of the present invention seeks to provide a display device including the above thin film transistor.

Another embodiment of the present invention seeks to provide a method of manufacturing the above thin film transistor.

One embodiment of the present invention for achieving the above-described technical problem includes an active layer, a gate electrode spaced apart from the active layer and at least partially overlapping the active layer, and a gate insulating film between the active layer and the gate electrode, , the gate insulating film includes a first insulating film on the active layer and a second insulating film on the first insulating film, and an area where the gate electrode and the active layer overlap is an area defined by the first insulating film in a plan view. It provides a thin film transistor in which at least a portion of a region of the active layer that does not overlap the gate electrode is exposed from the first insulating layer and is in contact with the second insulating layer.

The first insulating layer on the active layer has a width greater than that of the gate electrode. Here, the width of the first insulating layer and the width of the gate electrode are the distance across the first insulating layer and the gate electrode along the same direction as the direction of the current flowing through the active layer when the thin film transistor is turned on. Each is defined.

The first insulating film is disposed inside an area defined by the active layer in a plan view.

The gate electrode includes a titanium (Ti) film, an aluminum (Al) film, and a titanium (Ti) film sequentially stacked.

The taper angle of the edge of the first insulating film is 60° or less.

The active layer includes an oxide semiconductor material.

The active layer includes a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer.

Another embodiment of the present invention includes a substrate, a pixel driver on the substrate, and a display element connected to the pixel driver, wherein the pixel driver includes a thin film transistor, and the thin film transistor has an active layer and is spaced apart from the active layer. and a gate electrode that at least partially overlaps the active layer and a gate insulating film between the active layer and the gate electrode, wherein the gate insulating film includes a first insulating film on the active layer and a second insulating film on the first insulating film. The area where the gate electrode and the active layer overlap is located in an area defined by the first insulating film on a planar surface, and at least a portion of the area of the active layer that does not overlap the gate electrode is the first insulating film. A display device is provided that is exposed from and contacts the second insulating film.

The first insulating layer has a width greater than that of the gate electrode.

The first insulating film is disposed inside an area defined by the active layer in a plan view.

The active layer includes an oxide semiconductor material.

Another embodiment of the present invention includes sequentially stacking an oxide active material layer and a first insulating material layer on a substrate, selectively etching the active material layer and the first insulating material layer to form the active layer and the first insulating material layer. Forming a first insulating film on the active layer, forming a second insulating film on the active layer and the first insulating film, and forming a gate electrode on the second insulating film, wherein the gate electrode is A method of manufacturing a thin film transistor is provided, wherein the active layer overlaps, and the area where the gate electrode and the active layer overlap is located in an area defined by the first insulating film in a plan view.

At least a portion of a region of the active layer that does not overlap the gate electrode is exposed from the first insulating layer and contacts the second insulating layer.

On the active layer, the first insulating layer has a width greater than that of the gate electrode.

The first insulating film is formed inside a region defined by the active layer in a planar view.

The active layer is formed of an oxide semiconductor material.

The thin film transistor according to an embodiment of the present invention has a gate insulating film with a multi-layer structure, so that the taper angle of the gate insulating film is reduced and the tail of the gate insulating film can be sufficiently secured. The object is to provide a thin film transistor.

According to one embodiment of the present invention, since the gate insulating film has a multilayer structure and the taper angle of the gate insulating film can be reduced, the interlayer insulating film insulating between the gate electrode and the source electrode or the gate electrode and the drain electrode is interlayered. Defects such as seams are prevented from occurring, and the insulation of the gate electrode is improved. As a result, insulation breakdown between the gate electrode and the source electrode or between the gate electrode and the drain electrode is prevented, improving the stability and reliability of the thin film transistor.

In one embodiment of the present invention, even if the gate electrode has a multi-layer stacked structure, insulation between the gate electrode and the source electrode or drain electrode is stably secured, thereby improving the stability and reliability of the thin film transistor.

Additionally, according to one embodiment of the present invention, a thin film transistor having a multi-layered gate insulating film can be produced without adding a mask fixation.

When the thin film transistor according to an embodiment of the present invention is used in a display device, the stability and reliability of the display device can be improved.

In addition to the effects mentioned above, other features and advantages of the present invention are described below, or can be clearly understood by those skilled in the art from such description and description.

1 is a plan view of a thin film transistor according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line II' of FIG. 1.
FIG. 3 is a cross-sectional view taken along line II-II' of FIG. 1.
Figure 4 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention.
Figure 5 is a top view of a thin film transistor according to related technology.
FIG. 6A is a cross-sectional view taken along line III-III' of FIG. 5, and FIG. 6b is a cross-sectional view taken along line IV-IV' of FIG. 5.
Figure 7 is a photograph of a portion of a thin film transistor according to related technology.
Figures 8a and 8b are graphs of the threshold voltage of a thin film transistor.
9A and 9B are graphs of changes in threshold voltage of a thin film transistor.
10A to 10J are cross-sectional views of the manufacturing process of a thin film transistor according to an embodiment of the present invention.
Figure 11 is a schematic diagram of a display device according to another embodiment of the present invention.
FIG. 12 is a circuit diagram of one pixel of FIG. 11.
Figure 13 is a top view of the pixel of Figure 12.
FIG. 14 is a cross-sectional view taken along line V-V' of FIG. 13.
Figure 15 is a circuit diagram of a pixel of a display device according to another embodiment of the present invention.
Figure 16 is a circuit diagram of a pixel of a display device according to another embodiment of the present invention.
Figure 17 is a cross-sectional view of a portion of a pixel of a display device according to another embodiment of the present invention.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present invention is complete and are within the scope of common knowledge in the technical field to which the present invention pertains. It is provided to inform those who have the scope of the invention. The invention is defined only by the scope of the claims.

The shape, size, ratio, angle, number, etc. shown in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown in the drawings. Like components may be referred to by the same reference numerals throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the gist of the present invention, the detailed description is omitted.

When 'includes', 'has', 'consists of', etc. mentioned in this specification are used, other parts may be added unless the expression 'only' is used. If a component is expressed in the singular, the plural is included unless specifically stated.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

For example, when the positional relationship between two parts is described as ‘on top’, ‘on the top’, ‘on the bottom’, ‘next to’, etc., the expressions ‘immediately’ or ‘directly’ are used. Unless otherwise specified, one or more other parts may be located between the two parts.

Spatially relative terms such as “below, beneath,” “lower,” “above,” and “upper” refer to one element or component as shown in the drawing. It can be used to easily describe the correlation with other elements or components. Spatially relative terms should be understood as terms that include different directions of the element during use or operation in addition to the direction shown in the drawings. For example, if an element shown in the drawings is turned over, an element described as “below” or “beneath” another element may be placed “above” the other element. Accordingly, the illustrative term “down” may include both downward and upward directions. Likewise, the illustrative terms “up” or “on” can include both up and down directions.

In the case of a description of a temporal relationship, for example, if a temporal relationship is described as 'after', 'successfully after', 'after', 'before', etc., 'immediately' or 'directly' Unless the expression is used, non-continuous cases may also be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, “at least one of the first, second, and third items” means each of the first, second, or third items, as well as two of the first, second, and third items. It can mean a combination of all items that can be presented from more than one.

Each feature of the various embodiments of the present invention can be combined or combined with each other, partially or entirely, and various technical interconnections and operations are possible, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship. It may be possible.

In adding reference numerals to components in each drawing for explaining embodiments of the present invention, the same components may have the same reference numerals as much as possible even if they are shown in different drawings.

In embodiments of the present invention, the source electrode and the drain electrode are distinguished only for convenience of explanation, and the source electrode and the drain electrode may be interchanged. The source electrode may become a drain electrode, and the drain electrode may become a source electrode. Additionally, the source electrode in one embodiment may become a drain electrode in another embodiment, and the drain electrode in one embodiment may become a source electrode in another embodiment.

In some embodiments of the present invention, for convenience of explanation, a source region and a source electrode and a drain region and a drain electrode are distinguished, but the embodiments of the present invention are not limited thereto. The source region can be a source electrode, and the drain region can be a drain electrode. Additionally, the source region may be a drain electrode, and the drain region may be a source electrode.

FIG. 1 is a plan view of a thin film transistor 100 according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along II-I' of FIG. 1, and FIG. 3 is a cross-sectional view taken along II-II' of FIG. 1. am.

The thin film transistor 100 according to an embodiment of the present invention includes an active layer 130, a gate insulating film 120, and a gate electrode 140.

Referring to FIG. 1, the active layer 130 is disposed on the substrate 110.

Glass or plastic may be used as the substrate 110. A transparent plastic with flexible properties, for example, polyimide, may be used as the plastic.

A buffer layer 115 may be disposed on the substrate 110. The buffer layer 115 may include at least one of silicon oxide and silicon nitride. The buffer layer 115 may be made of a single layer, or may have a stacked structure in which two or more layers are stacked. The buffer layer 115 has excellent insulating and planarization characteristics and can protect the active layer 130. The buffer layer 115 may be omitted.

Referring to FIGS. 2 and 3 , the active layer 130 may be disposed on the buffer layer 115 on the substrate 110.

According to one embodiment of the present invention, the active layer 130 is an oxide semiconductor layer containing an oxide semiconductor material.

The active layer 130 is, for example, IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, ITZO (InSnZnO)-based IGTO (InGaSnO). It may include at least one of GO (GaO)-based, GZTO (GaZnSnO)-based, and GZO (GaZnO)-based oxide semiconductor materials. However, the embodiment of the present invention is not limited to this, and the active layer 130 may be made of other oxide semiconductor materials known in the art.

The active layer 130 may include a channel portion 131 overlapping the gate electrode 140 and conductive portions 132 and 133 spaced apart from each other around the channel portion 131. The conductive parts 132 and 133 can be made by selectively making the oxide semiconductor layer into a conductor. For example, the conductive portions 132 and 133 may be created by plasma treatment or hydrogen treatment of the oxide semiconductor layer excluding the channel portion 131.

The first conductive part 132 located on either side of the channel part 131 is connected to the source electrode 150. Accordingly, the first conductive portion 132 is also referred to as the source region.

The second conductive part 133 located on the other side of the channel part 131 is connected to the drain electrode 160. Therefore, the second conductive portion 133 is also called a drain region.

In one embodiment of the present invention, for convenience of explanation, a source region and a source electrode are distinguished, and a drain region and a drain electrode are distinguished. However, embodiments of the present invention are not limited to this, and the source region may be a source electrode and the drain region may be a drain electrode. Additionally, the source region may be a drain electrode, and the drain region may be a source electrode.

Therefore, according to an embodiment of the present invention, the first conductive portion 132 may serve as a source electrode and the second conductive portion 133 may serve as a drain electrode. Additionally, the first conductive portion 132 may serve as a drain electrode, and the second conductive portion 133 may serve as a source electrode.

A gate insulating layer 120 is disposed on the active layer 130. The gate insulating layer 120 is disposed between the active layer 130 and the gate insulating layer 120. According to one embodiment of the present invention, the gate insulating layer 120 includes a first insulating layer 121 on the active layer 130 and a second insulating layer 122 on the first insulating layer 121.

Specifically, the first insulating film 121 is disposed on the active layer 130.

The first insulating film 121 may include an insulating material such as silicon oxide or silicon nitride. For example, the first insulating film 121 may be made of silicon oxide such as SiO ₂ . According to one embodiment of the present invention, the first insulating film 121 is disposed in an area defined by the active layer 130 in a plan view.

The second insulating film 122 is disposed on the first insulating film 121.

The second insulating film 122 may include an insulating material such as silicon oxide or silicon nitride. The second insulating film 122 may be made of the same material as the first insulating film 121 or may be made of a different material. For example, the second insulating film 122 may be made of silicon oxide such as SiO ₂ .

The gate electrode 140 is disposed on the gate insulating film 120. Specifically, the gate electrode 140 is spaced apart from the active layer 130 and overlaps at least a portion of the active layer 130.

The gate electrode 140 is made of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, or molybdenum ( It may include at least one of molybdenum-based metals such as Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 140 may have a multilayer structure including two or more conductive films with different physical properties.

Detailed structures of the gate insulating film 120 and the gate electrode 140 will be described later.

Referring to FIG. 2, an interlayer insulating film 170 is disposed on the gate electrode 140 and the second insulating film 122. The interlayer insulating film 170 is made of an insulating material. The interlayer insulating film 170 may be made of an organic material, an inorganic material, or a laminate of an organic material layer and an inorganic material layer.

The thin film transistor 100 according to an embodiment of the present invention includes a source electrode 150 and a drain electrode 160. The source electrode 150 and the drain electrode 160 are disposed on the interlayer insulating film 170. The source electrode 150 and the drain electrode 160 are spaced apart from each other and are respectively connected to the active layer 130. Referring to FIG. 2, the source electrode 150 and the drain electrode 160 are each connected to the active layer 130 through a contact hole formed in the interlayer insulating film 170.

The source electrode 150 and the drain electrode 160 are made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper ( Cu), and may include at least one of their alloys. The source electrode 150 and the drain electrode 160 may each be made of a single layer made of metal or a metal alloy, or may be made of two or more multiple layers.

The active layer 130, gate electrode 140, source electrode 150, and drain electrode 160 shown in FIGS. 1 and 2 constitute the thin film transistor 100.

However, one embodiment of the present invention is not limited thereto. The first conductive portion 132 and the second conductive portion 133 formed by conducting areas other than the channel portion 131 of the active layer 130 may serve as a source electrode and a drain electrode, respectively.

Hereinafter, the gate insulating film 120 and the gate electrode 140 will be described in more detail.

According to an embodiment of the present invention, the gate electrode 140 may have a three-layer film structure to improve reliability.

In the thin film transistor 100, when hydrogen (H) contained in the insulating layer adjacent to the gate electrode 140 or in the insulating layer above the gate electrode 140 moves to the active layer 130, the active layer 130 )'s electrical characteristics may change. When the electrical properties of the active layer 130 change, the electrical properties of the thin film transistor 100 change and the reliability of the thin film transistor 100 deteriorates. Therefore, in order to ensure the reliability of the thin film transistor 100, it is necessary to prevent the electrical characteristics of the active layer 130 from changing by blocking hydrogen (H) moving into the active layer 130.

In order to block hydrogen (H) moving to the active layer 130, the gate electrode 140 has a three-layer film structure in which a titanium (Ti) layer, an aluminum (Al) layer, and a titanium (Ti) layer are sequentially stacked. You can. The titanium (Ti) layer included in the gate electrode 140 of the three-layer structure can block or adsorb hydrogen (H) and block hydrogen (H) from moving into the active layer 130.

However, due to the etching rate of titanium (Ti), the edge of the gate electrode 140 including the titanium (Ti) layer, aluminum (Al) layer, and titanium (Ti) layer has a tape angle (θ1) close to 90°. You can. The inclination angle of the edge of the gate electrode 140 is called a taper angle (θ1).

When the gate insulating layer 120 is etched simultaneously with the gate electrode 140, if the taper angle θ1 at the edge of the gate electrode 140 increases, the taper angle at the edge of the gate insulating layer 120 may also increase. When the taper angle of the edge of the gate insulating film 120 increases, defects such as seams occur in the interlayer insulating film 170 disposed on the top of the gate electrode 140, causing damage to the gate electrode 140 and other electrodes or Insulation between wires may deteriorate, causing a short circuit.

For example, when a seam occurs in the interlayer insulating film 170, a short occurs between the gate electrode 140 and the source electrode 150 and between the gate electrode 140 and the drain electrode 160. This may cause the reliability of the thin film transistor 100 to decrease.

According to an embodiment of the present invention, the structure of the gate insulating film 120 is improved to prevent short circuits between the gate electrode 140 and the source electrode 150 and between the gate electrode 140 and the drain electrode 160. This can be prevented.

Specifically, according to one embodiment of the present invention, the gate insulating film 120 is formed by the first insulating film 121 and the second insulating film 122 on the first insulating film 121.

Referring to FIG. 2 , the area of the active layer 130 that overlaps the gate electrode 140 is covered by the first insulating film 121 . Specifically, the area where the gate electrode 140 and the active layer 130 overlap is located within an area defined by the first insulating film 121 on a planar view. For example, the area where the gate electrode 140 and the active layer 130 overlap may be the channel portion 131. The width of the channel portion 131 may be less than or equal to the width of the first insulating layer 121. A first insulating film 121 and a second insulating film 122 may be disposed between the gate electrode 140 and the active layer 130. The gate electrode 140 may be located in an area where the first insulating film 121 and the active layer 130 overlap.

At least a portion of the area of the active layer 130 that does not overlap the gate electrode 140 is exposed from the first insulating layer 121 and contacts the second insulating layer 122. For example, referring to FIG. 2, at least a portion of the area of the active layer 130 that does not overlap the gate electrode 140 may be disposed so that the second insulating film 122 is in direct contact with the active layer 130. . Additionally, the source electrode 150 and the drain electrode 160 may contact the active layer 130 in a region of the active layer 130 that does not overlap the gate electrode 140. Upper surfaces on both sides of the active layer 130 may directly contact the lower surfaces of the second insulating film 122.

Additionally, the first insulating film 121 is disposed inside the area defined by the active layer 130 in plan view. This first insulating film 121 may not be formed through a batch process with the gate electrode 140, but may be formed through a batch process with the active layer 130.

As a result, the taper angle θ2 of the edge of the first insulating film 121 may not be affected by the taper angle θ1 of the edge of the gate electrode 140. Therefore, according to an embodiment of the present invention, the taper angle θ2 of the edge of the first insulating film 121 may have a gentle inclination angle. For example, the taper angle θ2 of the edge of the first insulating film 121 may have an inclination angle of 60° or less. When the taper angle θ2 of the edge of the first insulating film 121 is 60° or less, the occurrence of seams can be prevented during the subsequent formation of the interlayer insulating film 170.

Additionally, referring to FIGS. 1 and 2 , the first insulating layer 121 on the active layer 130 may have a width greater than that of the gate electrode 140 . Here, the width of the first insulating film 121 and the width of the gate electrode 140 are in the same direction as the direction of the current flowing through the active layer 130 when the thin film transistor 100 is turned on. ) and the distance crossing the gate electrode 140, respectively. Specifically, the x-axis direction in FIG. 1 is the width direction of the first insulating film 121 and the gate electrode 140.

For reference, referring to FIG. 3 , in a cross section cut along the y-axis direction perpendicular to the width direction, the gate electrode 140 may extend to an area other than the area overlapping the active layer 130. However, the first insulating film 121 does not extend to areas other than the active layer 130 area. On the other hand, the second insulating film 121 may be disposed to extend to an area other than the active layer 130 area.

According to one embodiment of the present invention, the taper angle θ2 of the edge of the first insulating film 121 is gentle, and the first insulating film 121 has a width greater than the gate electrode 140 along the x-axis direction of FIG. 1. Since the first insulating film 121 is exposed to the outside of the gate electrode 140, the slope of the gate insulating film 120 is gentle at the bottom of the gate electrode 140.

Accordingly, defects such as seams are prevented from occurring in the interlayer insulating film 170 at the boundary with the gate electrode 140 or the gate insulating film 120. As a result, the insulation between the gate electrode 140 and other electrodes or wiring is reduced, thereby preventing a short circuit from occurring. In this way, according to an embodiment of the present invention, the insulation for the gate electrode 140 is improved, and the insulation between the gate electrode 140 and the source electrode 150 or between the gate electrode 140 and the drain electrode 160 is improved. By ensuring excellent insulation, the stability and reliability of the thin film transistor 100 can be improved.

The thin film transistor 100 shown in FIGS. 1, 2, and 3 can be used as a switching transistor in a display device.

Figure 4 is a cross-sectional view of a thin film transistor 200 according to another embodiment of the present invention. Hereinafter, to avoid duplication, descriptions of already described components are omitted.

Compared to the thin film transistor 100 shown in FIG. 2, the thin film transistor 200 of FIG. 4 further includes a light blocking layer 180 disposed between the substrate 110 and the buffer layer 115. The light blocking layer 180 overlaps the active layer 130.

The light blocking layer 180 blocks light incident on the active layer 130 of the thin film transistor 200 from the outside and prevents damage to the active layer 130 caused by external incident light.

The light blocking layer 180 may be made of an electrically conductive material such as metal. The buffer layer 115 insulates the light blocking layer 180 and the active layer 130. The light blocking layer 180 may be electrically connected to either the source electrode 150 or the drain electrode 160.

Additionally, referring to FIG. 4 , the active layer 130 includes a first oxide semiconductor layer 130a and a second oxide semiconductor layer 130b on the first oxide semiconductor layer 130a. The first oxide semiconductor layer 130a serves as a support layer for supporting the second oxide semiconductor layer 130b, and the second oxide semiconductor layer 130b serves as a channel layer. The channel of the active layer 130 is mainly formed in the second oxide semiconductor layer 130b.

The first oxide semiconductor layer 130a, which serves as a support layer, has excellent film stability and mechanical properties. For film stability, the first oxide semiconductor layer 130a may include gallium (Ga). Gallium (Ga) forms a stable bond with oxygen, and gallium oxide has excellent film stability.

The first oxide semiconductor layer 130a is, for example, IGZO (InGaZnO)-based, IGO (InGaO)-based, IGTO (InGaSnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, and It may include at least one of GO (GaO)-based oxide semiconductor materials.

The second oxide semiconductor layer 130b serving as a channel layer is, for example, IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO It may include at least one of (GaZnSnO)-based and ITZO (InSnZnO)-based oxide semiconductor materials. However, another embodiment of the present invention is not limited to this, and the second oxide semiconductor layer 130b may be made of other oxide semiconductor materials known in the art.

FIG. 5 is a plan view of a thin film transistor 10 according to a related technology, FIG. 6A is a cross-sectional view taken along line III-III' of FIG. 5, and FIG. 6b is a cross-sectional view taken along line IV-IV' of FIG. 5. Figure 7 is a photograph of a portion of a thin film transistor according to related technology.

Referring to FIGS. 5, 6A, and 6B, the gate insulating film 120 of the thin film transistor 10 according to the related technology has the same pattern shape as the gate electrode 140.

Referring to FIGS. 6A and 6B, the gate insulating film 120 of the thin film transistor 10 according to the related technology is disposed between the gate electrode 140 and the active layer 130 (FIG. 6A), and the gate electrode 140 is When extended to the external area of the active layer 130, the gate insulating film 120 also extends to the external area of the active layer 130 (FIG. 6B).

The gate insulating film 120 of the thin film transistor 10 according to related technology may be formed in a batch process together with the gate electrode 140.

According to related technology, in order to block hydrogen (H) moving to the active layer 130, a gate electrode with a three-layer structure in which a titanium (Ti) layer, an aluminum (Al) layer, and a titanium (Ti) layer are sequentially stacked. (140) is used. The titanium (Ti) layer included in the gate electrode 140 of the three-layer structure can block or adsorb hydrogen (H) and block hydrogen (H) from moving into the active layer 130.

Due to the etch rate of titanium (Ti), the gate electrode 140 including a titanium (Ti) layer, an aluminum (Al) layer, and a titanium (Ti) layer has a tape angle (θ3) close to 90°. Referring to FIG. 7, it can be seen that the tape angle θ3 is approximately 90° at the edge of the gate electrode 140 including the titanium (Ti) layer, the aluminum (Al) layer, and the titanium (Ti) layer.

According to related technology, the gate insulating film 120 is formed by etching the gate electrode 140 in batches. Referring to FIGS. 6A and 7 , the taper angle θ3 at the edge of the gate electrode 140 is about 90°, and accordingly, the taper angle θ4 at the edge of the gate insulating film 120 is also about 90°. do.

Referring to FIG. 7, when the taper angle θ4 of the edge of the gate insulating film 120 increases, defects such as seams occur in the interlayer insulating film 170 disposed on the top of the gate electrode 140. You can check it.

As shown in FIG. 7, when a seam occurs in the interlayer insulating film 170, a short circuit occurs between the gate electrode 140 and the source electrode 150 and between the gate electrode 140 and the drain electrode 160. short) may occur, and the reliability of the thin film transistor 100 may deteriorate. To prevent such defects, it is necessary to reduce the taper angle (θ4) of the edge of the gate insulating film 120. However, according to related technology, it is necessary to pattern the gate insulating film 120 twice in order to reduce the taper angle θ4 of the edge of the gate insulating film 120. Therefore, in this case, the number of processes using the mask increases, and the process cost increases.

Figures 8a and 8b are graphs of the threshold voltage of a thin film transistor.

Specifically, Figure 8a is a threshold voltage graph for a thin film transistor in which a 200 nm thick molybdenum (Mo) layer was used as the gate electrode 140, and 8b is a 50 nm thick aluminum (Al) layer and a 100 nm thick molybdenum (Mo) layer. This is a threshold voltage graph for a thin film transistor including a gate electrode 140 made of a stacked aluminum (Al) layer with a thickness of 50 nm.

Referring to FIG. 8B, it can be seen that the thin film transistor including the gate electrode 140 formed by stacking an aluminum (Al) layer, a molybdenum (Mo) layer, and an aluminum (Al) layer has excellent threshold voltage characteristics.

9A and 9B are graphs of changes in threshold voltage of a thin film transistor.

Specifically, Figure 9a is a graph of the threshold voltage change for a thin film transistor in which a 200 nm thick molybdenum (Mo) layer was used as the gate electrode 140, and 9b is a 50 nm thick aluminum (Al) layer and a 100 nm thick molybdenum (Mo) layer. ) layer and a gate electrode 140 formed by stacking a 50 nm thick aluminum (Al) layer.

More specifically, FIGS. 9A and 9B show the threshold voltage change (ΔVth) measured under NBTS (Negative Bias Temperature Stress) conditions for a thin film transistor according to related technology. At a temperature of 90°C, when a gate voltage of 10V and a drain voltage (Vd) of OV were applied, the change in threshold voltage (ΔVth) over time was measured for 90 minutes. The threshold voltage change (ΔVth) was measured multiple times.

Referring to FIGS. 9A and 9B, compared to the thin film transistor in which a 200 nm thick molybdenum (Mo) layer was used as the gate electrode 140, a 50 nm thick aluminum (Al) layer, a 100 nm thick molybdenum (Mo) layer, and a 50 nm thick molybdenum (Mo) layer were used as the gate electrode 140. It can be confirmed that the threshold voltage change is small in the thin film transistor including the gate electrode 140 formed by stacking thick aluminum (Al) layers.

Hereinafter, a method of manufacturing the thin film transistor 100 according to an embodiment of the present invention will be described with reference to FIGS. 10A to 10J.

10A to 10J are cross-sectional views of the manufacturing process of the thin film transistor 100 according to an embodiment of the present invention.

Referring to FIG. 10A, a buffer layer 115, an active material layer 130m, and a first insulating material layer 121a are formed on the substrate 110. The active material layer 130m may be formed of an oxide semiconductor material. Therefore, according to one embodiment of the present invention, the active material layer 130m is an oxide semiconductor material layer. The active material layer (130m) is patterned to become the active layer (130).

The first insulating material layer 121a may be made of an insulating material. As an insulating material for forming the first insulating material layer 121a, for example, silicon oxide or silicon nitride may be used. The first insulating material layer 121a is patterned to become the first insulating film 121.

Referring to FIG. 10b, a photoresist pattern 310 is formed on the first insulating material layer 121a. The photoresist pattern 310 has thickness steps. This photoresist pattern 310 can be created through exposure and development using a halftone mask.

As such, according to an embodiment of the present invention, the active layer 130 and the first insulating layer 121 are formed through selective exposure and etching using a halftone mask.

Referring to FIG. 10C, the first insulating material layer 121a is etched by etching using the photoresist pattern 310 as a mask. Wet etching or dry etching may be applied to etch the first insulating material layer 121a. According to one embodiment of the present invention, wet etching may be applied.

Referring to FIG. 10D, the active material layer 130m is etched by etching using the photoresist pattern 310 as a mask. Wet etching or dry etching may be applied to etch the active material layer (130m). According to one embodiment of the present invention, wet etching may be applied. As a result, the active layer 130 is formed.

Etching of the first insulating material layer 121a and etching of the active material layer 130m may be performed through a process.

Referring to FIG. 10E, a portion of the photo resist pattern 310 is removed by ashing to form a secondary photo resist pattern 312.

Referring to FIG. 10F, a portion of the first insulating material layer 121a is removed by etching using the secondary photo resist pattern 312 as a mask. This is called secondary etching of the first insulating material layer 121a. The first insulating film 121 is formed by secondary etching of the first insulating material layer 121a.

For example, secondary etching of the first insulating material layer 121a may be performed using a dry etching method. A separate pattern mask is not used for the secondary etching of the first insulating material layer 121a, and the secondary photo resist pattern 312 functions as a mask.

During the secondary etching process of the first insulating material layer 121a, a portion of the active layer 130 becomes conductive. Specifically, a region of the active layer 130 that is not protected by the first insulating film 121 may be made into a conductor to form the first conductive portion 132 and the second conductive portion 133.

Referring to FIG. 10g, the secondary photo resist pattern 312 is removed by ashing.

Referring to FIG. 10H, a second insulating layer 122 is formed on the active layer 130 and the first insulating layer 121. The second insulating film 122 may be made of an insulating material. As an insulating material for forming the second insulating film 122, for example, silicon oxide or silicon nitride may be used.

Referring to Figure 10h. At least a portion of the active layer 130 is exposed from the first insulating layer 121 and contacts the second insulating layer 122. As such, according to one embodiment of the present invention, the active layer 130 and the gate insulating layer 120 are formed through a single halftone mask process, and the gate insulating layer 120 may have a gentle inclination angle. In particular, the edge of the first insulating film 121 may have a gentle inclination angle.

Referring to FIG. 10I, a gate electrode 140 is formed on the second insulating film 122.

The gate electrode 140 overlaps the active layer. The area where the gate electrode 140 and the active layer 130 overlap is located in an area defined by the first insulating film 121 on a planar view.

Referring to FIG. 10J, an interlayer insulating film 170 is formed on the second insulating film 122, and a source electrode 150 and a drain electrode 160 are formed on the interlayer insulating film 170 to form a thin film transistor 100. It is completed.

Hereinafter, a display device 300 according to another embodiment of the present invention will be described with reference to FIGS. 11 to 14.

The display device 300 according to another embodiment of the present invention includes a substrate 110, a pixel driver (PDC) on the substrate 110, and a display element 710 connected to the pixel driver (PDC). The pixel driver (PDC) includes a thin film transistor.

As a thin film transistor, the thin film transistors 100 and 200 shown in FIGS. 2 and 4 can be used, respectively. Therefore, to avoid redundant description, description of the thin film transistors 100 and 200 is omitted below.

Figure 11 is a schematic diagram of a display device 300 according to another embodiment of the present invention.

As shown in FIG. 11, the display device 300 according to another embodiment of the present invention includes a pixel (P), a gate driver 220, a data driver 230, and a control unit 240 on a substrate 110. ) includes.

Gate lines GL and data lines DL are disposed on the substrate 110, and pixels P are disposed in intersection areas of the gate lines GL and data lines DL. The pixel P includes a display element 710 and a pixel driver (PDC) that drives the display element 710 . An image is displayed by driving the pixel (P).

The control unit 240 controls the gate driver 220 and the data driver 230.

The control unit 240 controls the gate control signal (GCS) for controlling the gate driver 220 and the data driver 230 using vertical/horizontal synchronization signals and clock signals supplied from an external system (not shown). Outputs a data control signal (DCS) for Additionally, the control unit 240 samples input image data input from an external system, rearranges it, and supplies the rearranged digital image data (RGB) to the data driver 230.

The gate control signal (GCS) includes a gate start pulse (GSP), gate shift clock (GSC), gate output enable signal (GOE), start signal (Vst), and gate clock (GCLK). Additionally, the gate control signal (GCS) may include control signals for controlling the shift register.

The data control signal (DCS) includes a source start pulse (SSP), source shift clock signal (SSC), source output enable signal (SOE), and polarity control signal (POL).

The data driver 230 supplies data voltage to the data lines DL on the substrate 110. Specifically, the data driver 230 converts the image data (RGB) input from the control unit 240 into an analog data voltage and supplies the data voltage to the data lines DL.

The gate driver 220 sequentially supplies gate pulses GP to the gate lines GL during one frame. Here, one frame refers to the period during which one image is output through the display panel. Additionally, the gate driver 220 supplies a gate off signal (Goff) that can turn off the switching element to the gate line (GL) during the remaining period in one frame in which the gate pulse (GP) is not supplied. Hereinafter, the gate pulse (GP) and the gate off signal (Goff) are collectively referred to as the scan signal (SS).

According to one embodiment of the present invention, the gate driver 220 may be mounted on the display panel. In this way, the structure in which the gate driver 220 is directly mounted on the substrate 110 is called a gate in panel (GIP) structure.

FIG. 12 is a circuit diagram of a pixel (P) in FIG. 11, FIG. 13 is a plan view of a pixel (P) in FIG. 12, and FIG. 14 is a cross-sectional view taken along line V-V' of FIG. 13.

The circuit diagram of FIG. 12 is an equivalent circuit diagram for one pixel (P) of the display device 300 including an organic light emitting diode (OLED) as the light emitting element 710. The pixel driver PDC of FIG. 12 includes a first thin film transistor TR1, which is a switching transistor, and a second thin film transistor TR2, which is a driving transistor.

As the first thin film transistor TR1 and the second thin film transistor TR2, the thin film transistors 100 and 200 shown in FIGS. 2 and 4 may be used, respectively. More specifically, the thin film transistors 100 and 200 of FIGS. 2 and 3 may be used as the first thin film transistor TR1, which is a switching transistor.

The first thin film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS supplied through the gate line GL.

The data line DL provides the data voltage Vdata to the pixel driver PDC, and the first thin film transistor TR1 controls the application of the data voltage Vdata.

The driving voltage line PL provides a driving voltage (Vdd) to the display element 710, and the second thin film transistor TR2 controls the driving voltage (Vdd). The driving voltage (Vdd) is a pixel driving voltage for driving an organic light emitting diode (OLED), which is the display element 710.

When the first thin film transistor TR1 is turned on by the scan signal SS applied from the gate driver 220 through the gate line GL, the data voltage Vdata supplied through the data line DL emits light. It is supplied to the gate electrode (G2) of the second thin film transistor (TR2) connected to the device 710. The data voltage Vdata is charged in the first capacitor C1 formed between the gate electrode G2 and the source electrode S2 of the second thin film transistor TR2. The first capacitor C1 is a storage capacitor Cst. The first capacitor C1 includes a first capacitor electrode C11 connected to the gate electrode G2 of the second thin film transistor TR2 and a second capacitor electrode connected to the source electrode S2 of the second thin film transistor TR2 ( C12).

The amount of current supplied to the organic light emitting diode (OLED), which is the display element 710, through the second thin film transistor TR2 is controlled according to the data voltage (Vdata), and accordingly, the light output from the display element 710 is controlled. Gradation can be controlled.

Referring to FIGS. 13 and 14 , the pixel driver (PDC) is disposed on the substrate 110 .

The substrate 110 may be made of glass or plastic.

The pixel driver (PDC) includes a light blocking layer 180 on the substrate 110, a buffer layer 115 on the light blocking layer 180, an active layer 130 (A1, A2) on the buffer layer 115, and an active layer 130. It includes gate electrodes (G1, G2) that at least partially overlap with (A1, A2), and source electrodes (S1, S2) and drain electrodes (D1, D2) respectively connected to the active layer 130 (A1, A2).

The light blocking layer 180 is made of a conductive material such as metal. The light blocking layer 180 protects the active layer 130 by blocking light incident from the outside.

A buffer layer 115 is disposed on the light blocking layer 180. The buffer layer 115 is made of an insulating material and protects the active layer 130 from moisture or oxygen introduced from the outside.

The first active layer A1 of the first thin film transistor TR1 and the second active layer A2 of the second thin film transistor TR2 are disposed on the buffer layer 115. At least one of the first active layer A1 of the first thin film transistor TR1 and the second active layer A2 of the second thin film transistor TR2 may be made of an oxide semiconductor material.

A gate insulating layer 120 is disposed on the active layer 130. The gate insulating layer 120 includes a first insulating layer 121 and a second insulating layer 122.

Gate electrodes G1 and G2 are disposed on the gate insulating film 129. The gate electrodes G1 and G2 may be extended from the gate line GL or may be a part of the gate line GL.

An interlayer insulating film 170 is disposed on the gate electrodes G1 and G2.

Source electrodes (S1, S2) and drain electrodes (D1, D2) are disposed on the interlayer insulating film 170. According to an embodiment of the present invention, the source electrodes (S1, S2) and the drain electrodes (D1, D2) are only distinguished for convenience of explanation, and the source electrodes (S1, S2) and the drain electrodes (D1, D2) can be interchanged. Accordingly, the source electrodes S1 and S2 may become the drain electrodes D1 and D2, and the drain electrodes D1 and 2 may become the source electrodes S1 and S2.

According to one embodiment of the present invention, the source electrode (S1) and the drain electrode (D1) of the first thin film transistor (TR1) are spaced apart from each other and are respectively connected to the first active layer (A1) of the first thin film transistor (TR1). do. The source electrode S2 and the drain electrode D2 of the second thin film transistor TR2 are spaced apart from each other and are respectively connected to the second active layer A2 of the second thin film transistor TR2.

Additionally, a data line DL and a driving power line PL are disposed on the interlayer insulating film 170. According to one embodiment of the present invention, the source electrode S1 of the first thin film transistor TR1 is connected to the data line DL. The drain electrode D2 of the second thin film transistor TR2 is connected to the driving power line PL.

A planarization layer 750 is disposed on the source electrodes S1 and S2, the drain electrodes D1 and D2, the data line DL, and the driving power line PL. The planarization layer 190 planarizes the upper portions of the first thin film transistor TR1 and the second thin film transistor TR2 and protects the first thin film transistor TR1 and the second thin film transistor TR2.

The first electrode 711 of the display element 710 is disposed on the planarization layer 190. The first electrode 711 of the display element 710 is connected to the source electrode S2 of the second thin film transistor TR2 through a contact hole formed in the planarization layer 190.

A bank layer 750 is disposed at the edge of the first electrode 711. The bank layer 750 defines the light-emitting area of the display element 710.

An organic emission layer 712 is disposed on the first electrode 711, and a second electrode 713 is disposed on the organic emission layer 712. Accordingly, the display element 710 is completed. The display element 710 shown in FIG. 14 is an organic light emitting diode (OLED). Accordingly, the display device 300 according to an embodiment of the present invention is an organic light emitting display device.

Figure 15 is a circuit diagram of a pixel P of the display device 400 according to another embodiment of the present invention. Figure 15 is an equivalent circuit diagram for a pixel (P) of an organic light emitting display device.

The pixel P of the display device 400 shown in FIG. 15 includes an organic light emitting diode (OLED), which is the display element 710, and a pixel driver (PDC) that drives the display element 710. The display element 710 is connected to a pixel driver (PDC).

In the pixel P, signal lines DL, GL, PL, RL, and SCL that supply signals to the pixel driver PDC are disposed.

A data voltage (Vdata) is supplied to the data line (DL), a scan signal (SS) is supplied to the gate line (GL), and a driving voltage (Vdd) for driving the pixel is supplied to the driving voltage line (PL). The reference voltage (Vref) is supplied to the reference line (RL), and the sensing control signal (SCS) is supplied to the sensing control line (SCL).

Referring to FIG. 15, when the gate line of the n-th pixel (P) is called "GLn", the gate line of the neighboring n-1th pixel (P) is "GLn-1", and the gate line of the n-1th pixel (P) is "GLn-1". The gate line “GLn-1” of P) serves as the sensing control line (SCL) of the nth pixel (P).

For example, the pixel driver PDC may include a first thin film transistor TR1 (switching transistor) connected to the gate line GL and the data line DL, and a data voltage transmitted through the first thin film transistor TR1 ( A second thin film transistor (TR2) (driving transistor) that controls the size of the current output to the display element 710 according to (Vdata), and a third thin film transistor (TR3) for detecting the characteristics of the second thin film transistor (TR2) (reference transistor).

The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, and the data voltage Vdata supplied to the data line DL is connected to the gate electrode of the second thin film transistor TR2. Send to (G2).

The third thin film transistor TR3 is connected to the first node (n1) and the reference line (RL) between the second thin film transistor (TR2) and the light emitting device 710, and is turned on or turned on by the sensing control signal (SCS). It is turned off, and the characteristics of the second thin film transistor (TR2), which is a driving transistor, are sensed during the sensing period.

The second node (n2) connected to the gate electrode (G2) of the second thin film transistor (TR2) is connected to the first thin film transistor (TR1). A first capacitor C1 is formed between the second node n2 and the first node n1. The first capacitor (C1) is also called a storage capacitor (Cst).

When the first thin film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode G2 of the second thin film transistor TR2. The data voltage Vdata is charged in the first capacitor C1 formed between the gate electrode G2 and the source electrode of the second thin film transistor TR2.

When the second thin film transistor TR2 is turned on, current is supplied to the light emitting device 710 through the second thin film transistor TR2 by the driving voltage Vdd that drives the pixel, and light is emitted from the light emitting device 710. This is output.

The first thin film transistor TR1, second thin film transistor TR2, and third thin film transistor TR2 of FIG. 15 have the same structure as any one of the thin film transistors 100 and 200 shown in FIGS. 2 and 4, respectively. You can have

FIG. 16 is a circuit diagram of a pixel P of the display device 500 according to another embodiment of the present invention.

The pixel P of the display device 500 shown in FIG. 16 includes an organic light emitting diode (OLED), which is the display element 710, and a pixel driver (PDC) that drives the display element 710. The display element 710 is connected to a pixel driver (PDC).

The pixel driver (PDC) includes thin film transistors (TR1, TR2, TR3, and TR4).

In the pixel P, signal lines DL, EL, GL, PL, SCL, and RL that supply driving signals to the pixel driver PDC are disposed.

Compared to the pixel P in FIG. 15, the pixel P in FIG. 16 further includes an emission control line EL. The emission control signal (EM) is supplied to the emission control line (EL).

In addition, compared to the pixel driver PDC of FIG. 15, the pixel driver PDC of FIG. 16 further includes a fourth thin film transistor TR4, which is a light emission control transistor for controlling the timing of light emission of the second thin film transistor TR2. Includes.

Referring to FIG. 16, when the gate line of the n-th pixel (P) is called "GL _n ", the gate line of the neighboring n-1th pixel (P) is "GL _n-1 ", and the gate line of the n-1th pixel (P) is "GL n-1". The gate line “GL _n-1 ” of the pixel (P) serves as the sensing control line (SCL) of the nth pixel (P).

The first capacitor C1 is located between the gate electrode G2 of the second thin film transistor TR2 and the display element 710. Additionally, the second capacitor C2 is located between the terminal to which the driving voltage Vdd is supplied among the terminals of the fourth thin film transistor TR4 and one electrode of the display element 710.

The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, and the data voltage Vdata supplied to the data line DL is connected to the gate electrode of the second thin film transistor TR2. Send to (G2).

The third thin film transistor TR3 is connected to the reference line RL, is turned on or off by the sensing control signal SCS, and detects the characteristics of the second thin film transistor TR2, which is a driving transistor, during the sensing period.

The fourth thin film transistor TR4 transfers the driving voltage (Vdd) to the second thin film transistor (TR2) or blocks the driving voltage (Vdd) according to the emision control signal (EM). When the fourth thin film transistor TR4 is turned on, current is supplied to the second thin film transistor TR2, and light is output from the display element 710.

The first thin film transistor TR1, the second thin film transistor TR2, the third thin film transistor TR3, and the fourth thin film transistor TR4 of FIG. 16 are the thin film transistors 100 shown in FIGS. 2 and 4, respectively. 200) may have the same structure as any one of the following.

The pixel driver (PDC) according to another embodiment of the present invention may be formed in various structures other than those described above. The pixel driver (PDC) may include, for example, five or more thin film transistors.

Figure 17 is a cross-sectional view of a portion of a pixel of a display device 600 according to another embodiment of the present invention.

The display device 600 of FIG. 17 includes both an oxide semiconductor thin film transistor and a polycrystalline silicon thin film transistor. Oxide semiconductor thin film transistors can be used as switching transistors, and polycrystalline silicon thin film transistors can be used as driving transistors.

Specifically, the display device 600 of FIG. 17 includes a first thin film transistor TR1, which is a switching transistor, and a second thin film transistor TR2, which is a driving transistor.

The first thin film transistor TR1 is an oxide semiconductor thin film transistor. The thin film transistors 100 and 200 shown in FIGS. 2 and 4 may be used as the first thin film transistor TR1.

The second thin film transistor (TR2) is a polycrystalline silicon thin film transistor. Polycrystalline silicon thin film transistors are also called “polysilicon thin film transistors.” Polycrystalline silicon thin film transistors, for example low temperature silicon polycrystallization (LTPS) thin film transistors, are used. A polycrystalline silicon thin film transistor includes a polycrystalline silicon semiconductor layer.

According to another embodiment of the present invention, the first thin film transistor TR1 and the second thin film transistor TR2 are stacked vertically. Referring to FIG. 17, the second thin film transistor TR2, which is a polycrystalline silicon thin film transistor, is disposed on a lower layer than the first thin film transistor TR1, which is an oxide semiconductor thin film transistor, and the first thin film transistor TR1 is relatively disposed on an upper layer. do.

In this way, when thin film transistors are stacked on the top and bottom, the thin film transistors and wiring can be arranged more densely. This stacked structure can be usefully applied to high-resolution display devices.

Referring to FIG. 17, a light blocking layer 180 is disposed on the substrate 110, and a buffer layer 115 of the light blocking layer 180 is disposed. The active layer 530 of the second thin film transistor TR2 made of a polycrystalline silicon semiconductor layer is disposed on the buffer layer 115. The active layer 530 of the second thin film transistor TR2 may include a channel portion 531 and conductive portions 532 and 533.

A gate insulating layer 125 is disposed on the active layer 530, and a gate electrode 540 is disposed on the gate insulating layer 125. A connection electrode 512 may be disposed on the gate insulating layer 125.

A buffer layer 175 is disposed on the gate electrode 540 and the connection electrode 512, and the active layer 130 of the first thin film transistor TR1 made of an oxide semiconductor layer is disposed on the buffer layer. A gate insulating film 120 composed of a first insulating film 121 and a second insulating film 122 is disposed on the active layer 130, and a gate electrode 140 is disposed on the gate insulating film 120. An interlayer insulating film 170 is disposed on the gate electrode 140, and a source electrode 150 and a drain electrode 160 are disposed on the interlayer insulating film 170. The source/drain electrode 560 of the second thin film transistor TR2 and other electrodes or wires 511 and 513 may be disposed on the interlayer insulating film 170. A passivation layer 172 is disposed on the source electrode 150 and the drain electrode 160, and a planarization layer 190 is disposed on the passivation layer 172. A display element 710 and a bank layer 750 are disposed on the planarization layer 190. The display element includes a first electrode 711 that is a pixel electrode, an organic light-emitting layer 712 on the first electrode 711, and a second electrode 713 on the organic light-emitting layer 712.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications and changes can be made without departing from the technical details of the present invention in the technical field to which the present invention pertains. It will be obvious to anyone with ordinary knowledge. Therefore, the scope of the present invention is indicated by the claims described below, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

100, 200, 300, 400: thin film transistor
110: substrate 115: buffer layer
120: Gate insulating film
121: first insulating film 122: second insulating film
130: active layer 140: gate electrode
150: source electrode 160: drain electrode
170: Interlayer insulating film 180: Light blocking layer
190: Planarization layer 710: Display element
711: first electrode 712: organic light emitting layer
713: second electrode 750: bank layer
220: gate driver 230: data driver
240: Control unit A1, A2: Active layer

Claims (16)

active layer;
a gate electrode spaced apart from the active layer and at least partially overlapping the active layer; and
It includes a gate insulating film between the active layer and the gate electrode,
The gate insulating film is,
a first insulating layer on the active layer; and
It includes a second insulating film on the first insulating film,
The area where the gate electrode and the active layer overlap is located in an area defined by the first insulating film in a plan view,
Both the first insulating film and the second insulating film are disposed between the active layer and the gate electrode,
The second insulating film is disposed between the first insulating film and the gate electrode,
A thin film transistor, wherein at least a portion of a region of the active layer that does not overlap the gate electrode is exposed from the first insulating film and contacts the second insulating film. According to paragraph 1,
A thin film transistor wherein the first insulating film on the active layer has a width greater than the gate electrode:
Here, the width of the first insulating layer and the width of the gate electrode are the distance across the first insulating layer and the gate electrode along the same direction as the direction of the current flowing through the active layer when the thin film transistor is turned on. Each is defined. According to paragraph 1,
A thin film transistor, wherein the first insulating film is disposed inside a region defined by the active layer in a plan view. According to paragraph 1,
A thin film transistor wherein the gate electrode includes a titanium (Ti) film, an aluminum (Al) film, and a titanium (Ti) film sequentially stacked. According to paragraph 1,
A thin film transistor wherein the taper angle of the edge of the first insulating film is 60° or less. According to paragraph 1,
A thin film transistor, wherein the active layer includes an oxide semiconductor material. According to paragraph 1,
The active layer is,
A first oxide semiconductor layer; and
A thin film transistor comprising; a second oxide semiconductor layer on the first oxide semiconductor layer. Board;
a pixel driver on the substrate; and
Includes a display element connected to the pixel driver,
The pixel driver includes a thin film transistor,
The thin film transistor is,
active layer;
a gate electrode spaced apart from the active layer and at least partially overlapping the active layer; and
It includes a gate insulating film between the active layer and the gate electrode,
The gate insulating film is,
a first insulating layer on the active layer; and
It includes a second insulating film on the first insulating film,
The area where the gate electrode and the active layer overlap are located in an area defined by the first insulating film on a planar view,
Both the first insulating film and the second insulating film are disposed between the active layer and the gate electrode,
The second insulating film is disposed between the first insulating film and the gate electrode,
At least a portion of a region of the active layer that does not overlap the gate electrode is exposed from the first insulating layer and contacts the second insulating layer. According to clause 8,
The display device wherein the first insulating film has a width greater than the gate electrode. According to clause 8,
The display device wherein the first insulating film is disposed inside an area defined by the active layer in a plan view. According to clause 8,
A display device, wherein the active layer includes an oxide semiconductor material. sequentially stacking an oxide active material layer and a first insulating material layer on a substrate;
selectively etching the active material layer and the first insulating material layer to form an active layer and a first insulating film on the active layer;
forming a second insulating layer on the active layer and the first insulating layer; and
It includes forming a gate electrode on the second insulating film,
The gate electrode overlaps the active layer,
The area where the gate electrode and the active layer overlap is located in an area defined by the first insulating film in a plan view,
Both the first insulating film and the second insulating film are disposed between the active layer and the gate electrode,
The second insulating film is disposed between the first insulating film and the gate electrode,
A method of manufacturing a thin film transistor, wherein at least a portion of a region of the active layer that does not overlap the gate electrode is exposed from the first insulating film and contacts the second insulating film. According to clause 12,
A method of manufacturing a thin film transistor, wherein at least a portion of a region of the active layer that does not overlap the gate electrode is exposed from the first insulating film and contacts the second insulating film. According to clause 12,
A method of manufacturing a thin film transistor, wherein the first insulating film on the active layer has a width greater than the gate electrode, According to clause 12,
The method of manufacturing a thin film transistor, wherein the first insulating film is formed inside a region defined by the active layer in a planar view. According to clause 12,
A method of manufacturing a thin film transistor, wherein the active layer is formed of an oxide semiconductor material.

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