KR102468510B1 - Thin film trnasistor substrate, method for manufacturing the same and display device comprising the same - Google Patents

Abstract

One embodiment of the present invention includes a substrate, a light blocking layer on the substrate, a buffer layer on the light blocking layer, a semiconductor layer on the buffer layer, and a gate electrode spaced apart from the semiconductor layer and at least partially overlapping the semiconductor layer, wherein the The semiconductor layer includes a channel portion and a conductor portion, a portion of the conductor portion is a source region and another portion is a drain region, and the light blocking layer overlaps the channel portion of the semiconductor layer and does not overlap the conductor portion. However, a thin film transistor substrate is provided.

Description

Thin film transistor substrate, method for manufacturing the same, and display device including the same

The present invention relates to a thin film transistor substrate, a manufacturing method thereof, and a display device including the thin film transistor substrate.

Transistors are widely used as switching devices or driving devices in the field of electronic devices. In particular, since a thin film transistor can be manufactured on a glass substrate or a plastic substrate, it is used as a switching element of a display device such as a liquid crystal display device or an organic light emitting device. It is widely used.

Based on the material constituting the active layer, the thin film transistor is an amorphous silicon thin film transistor in which amorphous silicon is used as an active layer, a polycrystalline silicon thin film transistor in which polycrystalline silicon is used as an active layer, and an oxide semiconductor used as an active layer. It can be classified as an oxide semiconductor thin film transistor.

Since amorphous silicon can be deposited in a short time to form an active layer, the amorphous silicon thin film transistor (a-Si TFT) has a short manufacturing process time and low production cost. On the other hand, since mobility is low, current driving capability is poor, and threshold voltage changes occur, amorphous silicon thin film transistors have disadvantages in that their use is limited in active matrix organic light emitting diodes (AMOLEDs).

A poly-Si TFT is made by depositing amorphous silicon and then crystallizing the amorphous silicon. Since a process in which amorphous silicon is crystallized is required during the manufacturing process of a polycrystalline silicon thin film transistor, the number of processes increases and manufacturing cost increases, and since the crystallization process is performed at a high process temperature, polycrystalline silicon thin film transistors are applied to large-area devices. It is difficult to become In addition, due to polycrystalline characteristics, it is difficult to secure uniformity of the polycrystalline silicon thin film transistor.

Since the oxide constituting the active layer can be formed at a relatively low temperature, has high mobility, and has a large resistance change according to the content of oxygen, an oxide semiconductor thin film transistor has desired physical properties. It has the advantage of being easily obtainable. In addition, since the oxide semiconductor is transparent due to the nature of the oxide, it is also advantageous for realizing a transparent display.

In order to apply an oxide semiconductor to a thin film transistor, it is necessary to conduct a part of the oxide semiconductor layer made of the oxide semiconductor. Conductorization is performed by various methods such as plasma treatment and ultraviolet treatment. In order to reduce the manufacturing process cost of an oxide semiconductor thin film transistor, it is necessary to simplify the conductorization process.

1. Korean Patent Publication No. 10-2018-0062278 (published on June 8, 2018): Transistor substrate, organic light emitting display panel using the same, manufacturing method thereof, and organic light emitting display device using the same

One embodiment of the present invention is to provide a thin film transistor substrate including an oxide semiconductor layer having a conductor portion made conductive by light irradiation using a light blocking layer as a mask.

Another embodiment of the present invention is to provide a method of manufacturing a thin film transistor substrate in which a portion of an oxide semiconductor layer is conductive by light irradiation using a light blocking layer as a mask.

Another embodiment of the present invention is to provide a display device having a thin film transistor including an oxide semiconductor layer having a conductorized portion made conductive by light irradiation using a light blocking layer as a mask.

One embodiment of the present invention for achieving the above-described technical problem is a substrate, a light blocking layer on the substrate, a buffer layer on the light blocking layer, a semiconductor layer on the buffer layer, and spaced apart from the semiconductor layer to at least partially overlap the semiconductor layer a gate electrode, wherein the semiconductor layer includes a channel portion and a conductor portion, wherein a portion of the conductor portion is a source region and another portion is a drain region, and the light blocking layer overlaps the channel portion of the semiconductor layer; , It provides a thin film transistor substrate that does not overlap with the conductive portion.

The semiconductor layer includes an oxide semiconductor material.

The gate electrode overlaps the channel portion of the semiconductor layer and also overlaps at least a part of the conductive portion.

The gate electrode overlaps the conductive portion of the semiconductor layer to form a capacitor.

The semiconductor layer includes a first semiconductor layer on the substrate and a second semiconductor layer on the first semiconductor layer.

In another embodiment of the present invention, a substrate, a light blocking layer on the substrate, a buffer layer on the light blocking layer, a pixel driver disposed on the buffer layer and including at least one thin film transistor, and a light emitting element connected to the pixel driver, The thin film transistor includes a semiconductor layer on a buffer layer and a gate electrode spaced apart from the semiconductor layer and at least partially overlapping the semiconductor layer, wherein the semiconductor layer includes a channel portion and a conductor portion, and a portion of the conductor portion is a source region. , the other part is a drain region, and the light blocking layer overlaps the channel portion of the semiconductor layer and does not overlap the conductive portion.

The semiconductor layer includes an oxide semiconductor material.

The gate electrode overlaps the channel portion of the semiconductor layer and also overlaps at least a part of the conductive portion.

The conductive portion and the gate electrode overlapping each other form a capacitor.

The semiconductor layer includes a first semiconductor layer on the substrate and a second semiconductor layer on the first semiconductor layer.

The light emitting device is an organic light emitting diode.

Another embodiment of the present invention is a semiconductor having a light blocking layer on a substrate, forming a buffer layer on the light blocking layer, and a region overlapping the light blocking layer and a non-overlapping region on the buffer layer. Forming a layer, forming a gate electrode spaced apart from the semiconductor layer and at least partially overlapping the semiconductor layer, and irradiating light to the substrate on the light blocking layer side to overlap the light blocking layer of the semiconductor layer. It provides a method for manufacturing a thin film transistor substrate, including the step of conducting a non-conductive region.

The semiconductor layer includes an oxide semiconductor material.

The light irradiation may be performed before or after forming the gate electrode.

The light is ultraviolet.

The gate electrode overlaps with a region of the semiconductor layer overlapping with the light blocking layer, and also overlaps with at least a part of a region that does not overlap with the light blocking layer.

According to one embodiment of the present invention, since a portion of the semiconductor layer can be easily conducted by light irradiation using the light blocking layer as a mask, the conductorization process of the semiconductor layer is simplified and the cost of conductorization is reduced.

In a conventional self-align structure in which a gate electrode is used as a mask for conductorization of a semiconductor layer, when forming a capacitor electrode connected to the gate electrode, after forming the gate electrode, a separate capacitor for An electrode was formed, and the gate electrode and the capacitor electrode were connected using a separate bridge. On the other hand, according to one embodiment of the present invention, since the light blocking layer is used as a mask for conductorization, the gate electrode of the thin film transistor does not have to be used as a mask, and the area of the gate electrode is expanded so that a part of the gate electrode can be directly It can be one electrode of a capacitor. Therefore, according to an embodiment of the present invention, the capacitor formation process is simplified and the capacitor formation cost can be reduced.

In addition to the effects mentioned above, other features and advantages of the present invention will be described below, or will be clearly understood by those skilled in the art from such description and description.

1 is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present invention.
2 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
3 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
4 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
5 is a cross-sectional view of a thin film transistor substrate according to a comparative example.
6 is a schematic diagram of a display device according to another exemplary embodiment of the present invention.
FIG. 7 is a circuit diagram of one pixel of FIG. 6 .
FIG. 8 is a plan view of the pixel of FIG. 7 .
9 is a cross-sectional view taken along line II′ of FIG. 8 .
FIG. 10 is a cross-sectional view taken along line II-II' of FIG. 8 .
FIG. 11 is a cross-sectional view taken along line III-III' of FIG. 8 .
12A is a plan view of a pixel of a display device according to a comparative example.
FIG. 12B is a cross-sectional view taken along line IV-IV' of FIG. 12A.
13a and 13g are manufacturing process diagrams of a thin film transistor substrate according to an embodiment of the present invention.
14a and 14b are manufacturing process diagrams of a thin film transistor substrate according to another embodiment of the present invention.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various forms different from each other, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to inform those who have the scope of the invention. The invention is only defined by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, the present invention is not limited to those shown in the drawings. Like elements may be referred to by like reference numerals throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless the expression 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

For example, when the positional relationship of two parts is described as 'on ~', 'upon ~', 'on ~ below', 'beside ~', etc., the expression 'immediately' or 'directly' is used. Unless otherwise specified, one or more other parts may be located between the two parts.

The spatially relative terms "below, beneath", "lower", "above", "upper", etc., refer to one element or component as shown in the drawing. It can be used to easily describe the correlation between and other elements or components. Spatially relative terms should be understood as terms that include different orientations of elements in use or operation in addition to the directions shown in the figures. For example, when flipping elements shown in the figures, elements described as “below” or “beneath” other elements may be placed “above” the other elements. Thus, the exemplary term “below” may include directions of both below and above. Likewise, the exemplary terms "above" or "above" can include both directions of up and down.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal precedence relationship is described in terms of 'after', 'following', 'next to', 'before', etc. Unless the expression is used, non-continuous cases may also be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, "at least one of the first item, the second item, and the third item" means not only the first item, the second item, or the third item, respectively, but also two of the first item, the second item, and the third item. It may mean a combination of all items that can be presented from one or more.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship. may be

In the embodiments of the present invention, the source electrode and the drain electrode are only distinguished for convenience of description, and the source electrode and the drain electrode may be interchanged. Specifically, the source electrode of one embodiment may be used as a drain electrode, and the drain electrode may be used as a source electrode. Also, a source electrode of one embodiment may be a drain electrode in another embodiment, and a drain electrode of one embodiment may be a source electrode in another embodiment.

In the embodiments of the present invention, the source region and the source electrode are distinguished and the drain region and the drain electrode are distinguished for convenience of explanation, but the embodiments of the present invention are not limited thereto. The source region may serve as a source electrode, and the drain region may serve as a drain electrode. Also, the source region may serve as the drain electrode, and the drain region may serve as the source electrode.

Hereinafter, a thin film transistor, a manufacturing method thereof, and a display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings.

1 is a cross-sectional view of a thin film transistor substrate 100 according to an embodiment of the present invention.

The thin film transistor substrate 100 according to an embodiment of the present invention includes a substrate 110, a light blocking layer LS on the substrate 110, a buffer layer 120 on the light blocking layer LS, and a semiconductor layer on the buffer layer 120. 130 and a gate electrode 160 spaced apart from the semiconductor layer 130 and at least partially overlapping the semiconductor layer 130 . The semiconductor layer 130 includes a channel portion 131 and conductor portions 132 and 233, and some of the conductive portions 132 and 133 are source regions 132 and other portions are drain regions 133. . The light blocking layer LS overlaps the channel portion 131 of the semiconductor layer 130 and does not overlap the conductive portions 132 and 133 .

Hereinafter, components of the thin film transistor substrate 100 according to an embodiment of the present invention will be described in detail.

Glass or plastic may be used as the substrate 110 . As the plastic, a transparent plastic having a flexible property, such as polyimide, may be used. When polyimide is used as the substrate 110, considering that a high-temperature deposition process is performed on the substrate 110, heat-resistant polyimide that can withstand high temperatures may be used.

A light blocking layer LS is disposed on the substrate 110 . According to one embodiment of the present invention, the light blocking layer LS overlaps the channel portion 131 of the semiconductor layer 130 . The light blocking layer LS protects the semiconductor layer 130 by blocking light incident on the thin film transistor substrate 100 , and particularly protects the channel portion 131 .

In addition, the light blocking layer LS acts as a mask in the process of conducting the semiconductor layer 130 by light irradiation during the manufacturing process of the thin film transistor substrate 100, and the light blocking layer LS of the semiconductor layer 130 ) and overlapping areas are prevented from becoming conductive. As a result, a region of the semiconductor layer 130 overlapping the light blocking layer LS is not conductive and becomes the channel portion 131 . Therefore, according to one embodiment of the present invention, the light blocking layer LS does not overlap the conductor portions 132 and 133 of the semiconductor layer 130 .

Any material capable of blocking light may be used as the material of the light blocking layer LS without limitation. For example, the light blocking layer LS may be made of metal.

Referring to FIG. 1 , a buffer layer 120 is disposed on a substrate 110 . The buffer layer 120 includes an insulating material such as silicon oxide or silicon nitride. The buffer layer 120 protects the semiconductor layer 130 . In addition, the buffer layer 120 serves to planarize the top of the substrate 110 on which the light blocking layer LS is disposed. The buffer layer 120 is also referred to as a protective layer or an insulating layer.

The semiconductor layer 130 is disposed on the buffer layer 120 . According to one embodiment of the present invention, the semiconductor layer 130 includes an oxide semiconductor material. For example, the semiconductor layer 130 may be IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, or GZO (GaZnO)-based and ITZO (InSnZnO)-based oxide semiconductor materials. However, one embodiment of the present invention is not limited thereto, and the semiconductor layer 130 may include other oxide semiconductor materials known in the art.

Referring to FIG. 1 , the semiconductor layer 130 includes a channel portion 131 overlapping the light blocking layer LS and conductive portions 132 and 133 not overlapping the light blocking layer LS. The semiconductor layer 130 has at least two conductive parts 132 and 133 spaced apart with a channel part 131 interposed therebetween.

Some of the conductive parts 132 and 133 become the source region 132 and the other part becomes the drain region 133 . The source region 132 and the drain region 133 are spaced apart from each other with the channel portion 131 interposed therebetween. According to an embodiment of the present invention, the source region 132 may be referred to as a source electrode, and the drain region 133 may be referred to as a drain electrode.

A gate insulating layer 140 is disposed on the semiconductor layer 130 . The gate insulating layer 140 protects the semiconductor layer 130 . The gate insulating layer 140 may include at least one of silicon oxide, silicon nitride, and metal-based oxide. However, one embodiment of the present invention is not limited thereto, and the gate insulating layer 140 may include other insulating materials. The gate insulating film 140 may have a single film structure or a multi-layer structure.

Referring to FIG. 1 , a gate insulating layer 140 may be disposed on the entire surface of the substrate 110 including the entire upper portion of the semiconductor layer 130 . However, one embodiment of the present invention is not limited thereto, and the gate insulating layer 140 may be disposed on a portion of the semiconductor layer 130 . For example, the gate insulating layer 140 may be disposed only on the channel portion 131 of the semiconductor layer 130 .

The gate electrode 160 is disposed on the gate insulating layer 140 .

The gate electrode 160 is made of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, or molybdenum ( Mo) or a molybdenum-based metal such as a molybdenum alloy, at least one of chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 160 may have a multilayer structure including at least two conductive layers having different physical properties.

The gate electrode 160 at least partially overlaps the semiconductor layer 130 . Referring to FIG. 1 , the gate electrode 160 overlaps the channel portion 131 of the semiconductor layer 130 .

However, one embodiment of the present invention is not limited thereto, and the gate electrode 160 not only overlaps with the channel portion 131 of the semiconductor layer 130, but also the conductive portions 132 and 133 of the semiconductor layer 130 It may also overlap with at least some of them (see FIG. 4). In this case, a portion of the gate electrode 160 overlapping the channel portion 131 of the semiconductor layer 130 serves to turn on/off the thin film transistor TR, and the conductor portion 132 of the semiconductor layer 130 A portion of the gate electrode 160 overlapping with 133 forms a capacitor together with the conductive portions 132 and 133 of the semiconductor layer 130 .

An interlayer insulating film 150 is disposed on the gate electrode 160 . The interlayer insulating film 150 is made of an insulating material. The interlayer insulating film 150 may be made of an organic material, an inorganic material, or a laminate of an organic material layer and an inorganic material layer.

The thin film transistor substrate 100 according to an exemplary embodiment includes a source electrode 170 connected to a source region 132 and a drain electrode 180 connected to a drain region 133 . Referring to FIG. 1 , a source electrode 170 and a drain electrode 180 are disposed on an interlayer insulating layer 150 .

The source electrode 170 is connected to the channel portion 131 of the semiconductor layer 130 through the source region 132, and the drain electrode 180 is connected to the channel portion 131 of the semiconductor layer 130 through the drain region 133 ( 131) are connected. Referring to FIG. 1 , the source electrode 170 and the drain electrode 180 are connected to the source region 132 and the drain region 133 of the semiconductor layer 130 through contact holes formed in the interlayer insulating film 150, respectively. Each is connected to the channel unit 131.

However, one embodiment of the present invention is not limited thereto, and the source region 132 becomes the source electrode and the drain region 133 becomes the drain electrode without the separate source electrode 170 and the drain electrode 180. may be

The source electrode 170 and the drain electrode 180 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper ( Cu), and at least one of alloys thereof. The source electrode 170 and the drain electrode 180 may each be made of a single layer made of a metal or metal alloy, or may be made of multiple layers of two or more layers.

In one embodiment of the present invention, a portion of the thin film transistor substrate 100 excluding the substrate 110 may be referred to as a thin film transistor TR. Accordingly, the thin film transistor substrate 100 according to an embodiment of the present invention includes at least a light blocking layer LS, a semiconductor layer 130, a gate electrode 160, a source electrode 170, and a drain electrode 130. It includes one thin film transistor (TR).

2 is a cross-sectional view of a thin film transistor substrate 200 according to another embodiment of the present invention. Hereinafter, in order to avoid redundancy, descriptions of components already described are omitted.

Compared to the thin film transistor substrate 100 of FIG. 1 , the thin film transistor substrate 200 of FIG. 2 has a multilayer structure of the semiconductor layer 130 . Specifically, the semiconductor layer 130 includes a first semiconductor layer 130a on the substrate 110 and a second semiconductor layer 130b on the first semiconductor layer 130a. The first semiconductor layer 130a and the second semiconductor layer 130b may include the same semiconductor material or different semiconductor materials. When the first semiconductor layer 130a and the second semiconductor layer 130b include the same metal material, oxygen concentrations may be different from each other.

The first semiconductor layer 130a supports the second semiconductor layer 130b. Therefore, the first semiconductor layer 130a is also referred to as a “support layer”. The channel portion 131 is formed on the second semiconductor layer 130b. Therefore, the second semiconductor layer 130b is also referred to as a “channel layer”. However, one embodiment of the present invention is not limited thereto, and the channel portion 131 may also be formed in the first semiconductor layer 130a.

The first semiconductor layer 130a and the second semiconductor layer 130b may be formed by deposition. The first semiconductor layer 130a and the second semiconductor layer 130b may be formed through a continuous process.

A structure in which the semiconductor layer 130 includes the first semiconductor layer 130a and the second semiconductor layer 130b is also referred to as a bi-layer structure.

3 is a cross-sectional view of a thin film transistor substrate 300 according to another embodiment of the present invention.

Compared to the thin film transistor substrate 100 of FIG. 1 , the thin film transistor substrate 300 of FIG. 3 further includes a connection electrode 185 disposed on the interlayer insulating film 150 and connected to the gate electrode 160 . The connection electrode 185 may be connected to other elements or wires disposed on the thin film transistor substrate 300 (see FIGS. 8 and 10 ). Although not shown, the connection electrode 185 is connected to other elements on the substrate 110, so that the gate electrode 160 can be connected to other elements. Alternatively, the connection electrode 185 is connected to a wire (not shown) formed on the thin film transistor substrate 300 so that the gate electrode 160 is connected to the wire (not shown).

Also, although not shown in the drawings, the drain electrode 180 may be connected to the light blocking layer LS as well as the channel portion 131 of the semiconductor layer 130 (see FIGS. 9 and 11 ). However, one embodiment of the present invention is not limited thereto, and the light blocking layer LS may be connected to the source electrode 170 .

4 is a cross-sectional view of a thin film transistor substrate 400 according to another embodiment of the present invention.

Referring to FIG. 4 , the gate electrode 160 extends over the upper portion of the channel portion 131 and the upper portions of the conductive portions 132 and 133 of the semiconductor layer 130 .

Specifically, the gate electrode 160 overlaps the channel portion 131 of the semiconductor layer 130 and also overlaps at least a portion of the conductive portions 132 and 133 of the semiconductor layer 130 . The gate electrode 160 may overlap the conductor portions 132 and 133 of the semiconductor layer 130 to form a capacitor Cap.

In this case, a portion of the gate electrode 160 overlapping the channel portion 131 serves to turn on/off the thin film transistor TR, and the other portion of the gate electrode 160 overlapping the conductor portions 132 and 133 A portion of the semiconductor layer 130 may form a capacitance together with the conductive parts 132 and 133 .

Referring to FIG. 4 , the drain region 133 overlapping the gate electrode 160 among the conductive portions 132 and 133 of the semiconductor layer 130 becomes the first electrode 511 of the capacitor Cap, and the drain region A portion of the gate electrode 160 overlapping 133 becomes the second electrode 512 of the capacitor Cap, and the capacitor Cap is formed by the drain region 133 and a portion of the gate electrode 160. .

In addition, in the thin film transistor substrate 400 shown in FIG. 4 , the source region 132 of the semiconductor layer 130 is a source electrode, and the drain region 133 is a drain electrode.

A connection electrode 185 is disposed on the interlayer insulating layer 150 .

The connection electrode 185 is connected to the gate electrode 160 and applies a gate signal or voltage to the gate electrode 160 .

A protective layer 155 is disposed on the connection electrode 185 . The protective layer 155 is made of an insulating material and protects the thin film transistor TR. The protective layer 155 may be made of an organic material, an inorganic material, or a laminate of an organic material layer and an inorganic material layer. An upper portion of the thin film transistor TR is flattened by the passivation layer 155 . Therefore, the protective film 155 is also referred to as a planarization film.

5 is a cross-sectional view of a thin film transistor substrate 501 according to a comparative example.

In the thin film transistor substrate 501 shown in FIG. 5 , after the gate electrode 160 is patterned, a region other than the channel portion 131 of the semiconductor layer 130 is covered by using the patterned gate electrode 160 as a mask. It has a self-align structure that conducts. In the self-align structure, since the gate electrode 160 is used as a mask for making the semiconductor layer 130 a conductor, the gate electrode 160 is patterned to correspond to the channel portion 131, A region of the semiconductor layer 130 overlapping the gate electrode 160 becomes the channel portion 131 .

In the self-align structure shown in FIG. 5 , a separate capacitor electrode 513 is formed to form the capacitor Cap. In addition, the separate capacitor electrode 513 is connected to the gate electrode 160 through a separate bridge 165.

Specifically, after the intermediate protective film 145 is formed on the gate electrode 160, a separate capacitor electrode 513 overlapping at least partially with the conductive parts 132 and 133 of the semiconductor layer 130 is formed on the intermediate protective film 145. ), and a separate bridge 165 is formed to connect the gate electrode 160 and the separate capacitor electrode 513. Therefore, according to the comparative example, a process of forming a separate capacitor electrode 513 and a separate process of forming a bridge 165 are required to form the capacitor (Cap).

On the other hand, according to another embodiment of the present invention shown in FIG. 4, since the light blocking layer LS is used as a mask for conductorization, the gate electrode 160 is used as a mask for the channel portion 131. It doesn't work. Accordingly, the area of the gate electrode 160 may be expanded so that a portion of the gate electrode 160 overlaps at least a portion of the conductive portions 132 and 133 . As a result, a part of the conductive parts 132 and 133 (drain region 133) becomes one electrode 511 (first electrode) of the capacitor Cap, and a part of the gate electrode 160 becomes the other electrode 511 of the capacitor Cap. One electrode 512 (second electrode) is formed to form a capacitor (Cap). As such, according to another embodiment of the present invention, the process of forming the capacitor (Cap) is simplified compared to the comparative example. As a result, the cost of forming the capacitor Cap may be reduced.

Hereinafter, a display device to which the thin film transistor substrates 100, 200, 300, and 400 described above can be applied will be described.

6 is a schematic diagram of a display device 600 according to another embodiment of the present invention, FIG. 7 is a circuit diagram of a pixel 601 of FIG. 6, and FIG. 8 is a circuit diagram of a pixel 601 of FIG. FIG. 9 is a cross-sectional view taken along line II' of FIG. 8, FIG. 10 is a cross-sectional view taken along line II-II' of FIG. 8, and FIG. 11 is a cross-sectional view taken along line III-III' of FIG. to be.

A display device 600 according to another embodiment of the present invention includes a substrate 110, light blocking layers LS1, LS2, LS3, and LS4 on the substrate 100, and light blocking layers LS1, LS2, LS3, and LS4 on the substrate 100. It includes a buffer layer 120 , a pixel driver PDC on the buffer layer 120 , and a light emitting element connected to the pixel driver PDC. The pixel driver PDC includes at least one thin film transistor TR1 , TR2 , TR3 , TR4 .

The display device 600 according to another embodiment of the present invention includes an organic light emitting diode (OLED) as a light emitting device. Accordingly, the display device 600 according to another exemplary embodiment of the present invention is an organic light emitting display device, and includes gate lines GL, data lines DL, and gate lines GL and data lines DL. An organic light emitting display panel 610 having a plurality of pixels 601 defined by .

Specifically, in the display device 600 according to another embodiment of the present invention, the organic light emitting display panel 610 on which an image is output and the gate lines GL provided on the organic light emitting display panel 610 are sequentially a gate driver 620 supplying a gate pulse GP to the data driver 630 and a gate driver 620 supplying data voltages to the data lines DL provided in the organic light emitting display panel 610; A controller 640 controlling the data driver 630 is included.

The control unit 640 uses a timing signal supplied from an external system, for example, a vertical synchronization signal, a horizontal synchronization signal, and a clock, to control the gate driver 620 by using a gate control signal (GCS) and a data driver. A data control signal (DCS) for controlling 630 is output. The controller 640 samples input image data input from an external system, rearranges them, and supplies the rearranged digital image data to the data driver 630 .

The data driver 630 converts the video data (Data) input from the control unit 640 into an analog data voltage, and the data for one horizontal line for each horizontal period in which the gate pulse (GP) is supplied to the gate line (GL). Voltages Vdata are transmitted to data lines DL.

The gate driver 620 sequentially supplies gate pulses GP to the gate lines GL of the organic light emitting display panel 610 in response to the gate control signal GCS input from the controller 640 . Accordingly, transistors disposed in each pixel 601 to which the gate pulse GP is input are turned on, and an image may be output to each pixel 601 . The gate driver 620 may be formed independently of the organic light emitting display panel 610 and electrically connected to the organic light emitting display panel 610 in various ways, or may have a gate mounted in the organic light emitting display panel 610. It may have a gate-in-panel (GIP) configuration.

At least one of the data driver 630 and the gate driver 620 may be integrated with the control unit 640 .

The organic light emitting display panel 610 includes gate lines GL to which gate pulses GP are applied, data lines DL to which data voltages are applied, and the gate lines GL and data lines DL. It includes pixels 601 to be defined. Each of the pixels 601 includes at least one thin film transistor TR1 , TR2 , TR3 , and TR4 . According to another embodiment of the present invention, a coplanar type oxide thin film transistor is used as the thin film transistors TR1 , TR2 , TR3 , and TR4 .

As shown in FIG. 7 , each of the pixels 601 included in the organic light emitting display panel 610 includes an organic light emitting diode (OLED) that outputs light and a pixel driver (PDC) that drives the organic light emitting diode (OLED). ). Signal lines DL, EL, GL[GL _n , GL _{n -1} ], PLA, PLB, SL, and SPL for supplying driving signals to the pixel driver PDC are disposed in each of the pixels 601 . .

The data voltage Vdata is supplied to the data line DL, the gate pulse GP is supplied to the gate line GL, the first driving power ELVDD is supplied to the power supply line PLA, and the driving power The second driving power source EVSS is supplied to the line PLB, the reference voltage Vref is supplied to the sensing line SL, the sensing pulse SP is supplied to the sensing pulse line SPL, and the emission The emission control signal EM is supplied to the line EL. Referring to FIGS. 7 and 8 , when the gate line of the n-th pixel 601 is "GL _n ", the gate line of the n-1-th pixel 601 adjacent to it is "GL _{n -1} ", and n The gate line “GL _{n -1} ” of the -1 th pixel 601 serves as the sensing pulse line SPL of the n th pixel 601 .

As shown in FIG. 7 , for example, the pixel driver PDC includes a first thin film transistor TR1 (switching transistor) connected to the gate line GLn and the data line DL, and the first thin film transistor TR1. ) (switching transistor), the second thin film transistor TR2 (driving transistor) and the second thin film transistor TR2 control the amount of current output to the organic light emitting diode (OLED) according to the data voltage Vdata transmitted through the switching transistor. ) and a fourth thin film transistor TR4 (sensing transistor) for sensing characteristics of the third thin film transistor TR3 (emission transistor) and the second thin film transistor TR2.

According to another embodiment of the present invention, the first thin film transistor TR1 is referred to as a "switching transistor", the second thin film transistor TR2 is referred to as a "driving transistor", and the third thin film transistor TR3 is referred to as an "emission transistor". Transistor", 4 The thin film transistor TR4 is also referred to as a "sensing transistor". However, another embodiment of the present invention is not limited thereto. The pixel driver PDC may be formed in various structures other than the structure shown in FIG. 7 . The pixel driver PDC may include, for example, three or fewer thin film transistors or five or more thin film transistors.

A first capacitor C1 is positioned between the gate electrode of the second thin film transistor TR2 and the pixel electrode of the organic light emitting diode OLED. The first capacitor C1 is also referred to as a storage capacitor Cst.

The second capacitor C2 is positioned between a terminal of the third thin film transistor TR3 to which the first driving power supply ELVDD is supplied and the pixel electrode 710 of the organic light emitting diode OLED.

The first thin film transistor TR1 is turned on by the gate pulse GP supplied to the gate line GLn and applies the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin film transistor TR2. send to

The fourth thin film transistor TR4 is connected to the first node n1 between the second thin film transistor TR2 and the organic light emitting diode OLED and to the sensing line SL, and is turned on or turned on by the sensing pulse SP. It is turned off, and the characteristic of the second thin film transistor TR2 serving as a driving transistor is sensed during the sensing period.

The second node n2 connected to the gate electrode of the second thin film transistor TR2 is connected to the first thin film transistor TR1. A first capacitor C1 is positioned between the second node n2 and the first node n1.

The third thin film transistor TR3 transmits the first driving power ELVDD to the second thin film transistor TR2 or blocks the first driving power ELVDD according to the emission control signal EM. When the third thin film transistor TR3 is turned on, current is supplied to the second thin film transistor TR2 and light is output from the organic light emitting diode OLED.

Referring to FIGS. 7 to 11 , the pixel driver PDC is disposed on the buffer layer 120 and includes at least one thin film transistor TR1 , TR2 , TR3 , and TR4 .

Referring to FIGS. 8 and 9 , the thin film transistors TR1 , TR2 , TR3 , and TR4 are semiconductor layers 130 ( A1 , A2 , A3 , and A4 ) and semiconductor layers 130 ( A1 , A1 , A4 ) on the buffer layer 120 . It includes gate electrodes G1 , G2 , G3 , and G4 spaced apart from A2 , A3 , and A4 and at least partially overlapping the semiconductor layer 130 (A1 , A2 , A3 , A4 ). The semiconductor layer 130 (A1, A2, A3, A4) includes a channel portion 131 and conductive portions 132 and 133, and some of the conductive portions 132 and 133 are source regions 132 (S1, S2, S3, S4), and the other part is the drain region 133 (D1, D2, D3, D4). The light blocking layers LS1, LS2, LS3, and LS4 overlap the channel portion 131 of the semiconductor layer 130 (A1, A2, A3, and A4) and do not overlap the conductive portions 132 and 133.

Referring to FIGS. 7 and 8 , the n−1 th first light blocking layer LS1 may be the fourth light blocking layer LS4 of the n th pixel.

8 to 11, the source regions 132 of the semiconductor layers 130 of the thin film transistors TR1, TR2, TR3, and TR4 serve as source electrodes S1, S2, S3, and S4, and drain The region 133 may serve as the drain electrodes D1, D2, D3, and D4. In addition, the source electrodes S1 , S2 , S3 , and S4 may be formed separately from the source region 132 , and the drain electrodes D1 , D2 , D3 , and D4 may be formed separately from the drain region 133 .

According to another embodiment of the present invention, the semiconductor layer 130 (A1, A2, A3, A4) includes an oxide semiconductor material. For example, the semiconductor layers 130 (A1, A2, A3, A4) may be IZO (InZnO), IGO (InGaO), ITO (InSnO), IGZO (InGaZnO), IGZTO (InGaZnSnO), or GZTO. It may include at least one of (GaZnSnO)-based, GZO (GaZnO)-based, and ITZO (InSnZnO)-based oxide semiconductor materials. However, one embodiment of the present invention is not limited thereto, and the semiconductor layers 130 (A1, A2, A3, A4) may be made of other oxide semiconductor materials known in the art. Also, any one of the semiconductor layers A1, A2, A3, and A4 may be made of amorphous silicon or polycrystalline silicon.

In addition, the semiconductor layers 130 (A1, A2, A3, and A4) may include a first semiconductor layer 130a on the substrate 110 and a second semiconductor layer 130b on the first semiconductor layer 130a. (See Fig. 2). At this time, the first semiconductor layer 130a supports the second semiconductor layer 130b. The channel portion 131 may be formed in the second semiconductor layer 130b. However, another embodiment of the present invention is not limited thereto, and the channel portion 131 may also be formed in the first semiconductor layer 130a.

A gate insulating layer 140 is disposed on the semiconductor layer 130 (A1, A2, A3, and A4). The gate insulating layer 140 may include at least one of silicon oxide, silicon nitride, and metal-based oxide. The gate insulating film 140 may have a single film structure or a multi-layer structure.

The gate electrode 160 is disposed on the gate insulating layer 140 . The gate electrode 160 is made of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, or molybdenum ( Mo) or a molybdenum-based metal such as a molybdenum alloy, at least one of chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 160 may have a multilayer structure including at least two conductive layers having different physical properties.

8 and 9, the gate electrode G2 of the second thin film transistor TR2 overlaps the channel portion 131 of the semiconductor layer 130 (A2), and at least one of the conductor portions 132 and 133 overlap with some The overlapping conductive parts 132 and 133 and the gate electrode G2 form a capacitor. The capacitor formed in this way is referred to as a first capacitor C1.

Specifically, the gate electrode G2 of the second thin film transistor TR2 not only overlaps the channel portion 131 of the semiconductor layer 130 (A2), but also the drain region 133 of the conductor portions 132 and 133. overlap with The drain region 133 overlapping the gate electrode G2 becomes the first electrode C11 of the first capacitor C1, and a part of the gate electrode G2 overlapping the drain region 133 becomes the first capacitor ( It becomes the second electrode C12 of C1), and the first capacitor C1 is formed by a part of the drain region 133 and the gate electrode G2.

As such, since a portion of the gate electrode G2 of the second thin film transistor TR2 and a portion of the conductor portions 132 and 133 of the semiconductor layer 130 (A2) form the first capacitor C1, 1 A separate additional process for forming the capacitor C1 is not required. Accordingly, process efficiency may be improved and process costs may be reduced.

Referring to FIG. 8 , the second capacitor C2 is disposed overlapping the power supply line PLA. The second capacitor C2 includes a first electrode C21 extending from the drain region 133 of the second thin film transistor TR2 and a second electrode C22 connected to the power supply line PLA.

Referring to FIG. 9 , an interlayer insulating layer 150 is disposed on the entire surface of the substrate 110 including upper portions of the gate electrodes G1 , G2 , G3 , and G4 and the emission line EL.

The interlayer insulating film 150 is made of an insulating material. Specifically, the interlayer insulating layer 150 may be made of an organic material, an inorganic material, or a laminate of an organic material layer and an inorganic material layer.

The connection electrode 185 is disposed on the interlayer insulating layer 150 . 8 to 10 , the connection electrode 185 connects the drain electrode D1 of the first thin film transistor TR1 and the gate electrode G2 of the second thin film transistor TR2. Accordingly, the data voltage Vdata supplied to the data line DL may be transferred to the gate electrode D2 of the second thin film transistor TR2.

In addition, at least one of the source electrodes S1 , S2 , S3 , and S4 and the drain electrodes D1 , D2 , D3 , and D4 may be disposed on the interlayer insulating layer 150 . When the source region 132 serves as a source electrode, a separate source electrode may not be formed, and even when the drain region 133 serves as a drain electrode, a separate drain electrode may not be formed.

Referring to FIGS. 8, 9, and 11 , the drain electrode D2 of the second thin film transistor TR2 is formed on the interlayer insulating layer 150 . The drain electrode D2 of the second thin film transistor TR2 is connected to the drain region 133 of the semiconductor layer 130 through one contact hole H2 formed in the interlayer insulating film 150 .

In addition, the drain electrode D2 of the second thin film transistor TR2 is connected to the light blocking layer LS2 through the contact hole connecting portion 125 and another contact hole H3 formed in the interlayer insulating film 150 . Referring to FIGS. 8 and 9 , a portion of the drain electrode D2 of the second thin film transistor TR2 may serve as the light blocking layer connecting portion 125 .

A passivation layer 155 is disposed on the connection electrode 185 and the light blocking layer connection portion 125 . The passivation layer 155 covers and protects the thin film transistors TR1 , TR2 , TR3 , and TR4 and flattens upper portions of the thin film transistors TR1 , TR2 , TR3 , and TR4 . The protective layer 155 may be formed of at least one organic or inorganic material. The protective film 155 is also referred to as a planarization film.

An organic light emitting diode (OLED), which is a light emitting device, is disposed on the passivation layer 155 . An organic light emitting diode (OLED) includes a pixel electrode 710 , an emission layer 720 and a common electrode 730 .

The pixel electrode 710 of the organic light emitting diode (OLED) is connected to the second thin film transistor TR2. The pixel electrode 710 of the organic light emitting diode OLED is connected to the drain electrode D2 of the second thin film transistor TR2 through the contact hole H1 formed in the passivation layer 155 .

An organic light emitting diode (OLED) is surrounded by a bank 750 . Each of the pixels 601 may be distinguished by the bank 750 .

12A is a plan view of a pixel of a display device 801 according to a comparative example, and FIG. 12B is a cross-sectional view taken along line IV-IV′ of FIG. 12A.

The display device 801 shown in FIG. 12A includes a first thin film transistor T1 as a switching transistor, a second thin film transistor T2 as a driving transistor, a third thin film transistor T3 as an emission transistor, and 4 sensing transistors. A thin film transistor T4 is included.

After the gate electrode G2 is patterned, the second thin film transistor TR2 conducts a region other than the channel portion 131 of the semiconductor layer 130 by using the patterned gate electrode G2 as a mask. It has a self-align structure. In order for the gate electrode G2 to be used as a mask during the process of conducting the semiconductor layer 130 , the gate electrode G2 is patterned to correspond to the channel portion 131 . As a result, a region of the semiconductor layer 130 overlapping the gate electrode G2 becomes the channel portion 131 .

12A and 12B, the drain region 133 of the semiconductor layer A2 of the second thin film transistor TR2 becomes the first electrode C11 of the first capacitor C1, and the gate electrode G2 and A separately formed conductor pattern becomes the second electrode C12 of the first capacitor C1.

According to the comparative example, after the gate electrode G2 is formed to form the second electrode C12 of the first capacitor C1, a conductive pattern overlapping the drain region 133 of the semiconductor layer A2 is separately formed. is formed The second electrode C12 of the first capacitor C1 formed as described above is connected to the gate electrode G2 through the bridge 165 . Therefore, in the manufacturing process of the display device 801 according to the comparative example, the process of forming the second electrode C12 and the process of forming the bridge 165 are separately required to form the first capacitor C1. do.

Referring to FIGS. 12A and 12B , the drain electrode D1 of the first thin film transistor T1 and the gate of the second thin film transistor T2 are provided through the three contact holes CH1 , CH2 , and CH3 and the bridge 165 . The electrode and the second electrode C12 of the first capacitor C1 are connected to each other.

On the other hand, according to another embodiment of the present invention shown in FIG. 8, the light blocking layer LS2 under the second thin film transistor TR2 is used as a mask for conducting, and the gate electrode G2 is used as a mask. Not used. Accordingly, the first capacitor C1 may be formed by extending the area of the gate electrode G2 such that a portion of the gate electrode G2 overlaps at least a portion of the drain region 133 .

In addition, according to another embodiment of the present invention, a contact hole CH3 for connecting the drain electrode D1 of the first thin film transistor TR1 and the second electrode C12 of the first capacitor is not required. do. Instead, the drain electrode D1 of the first thin film transistor TR1 is located where the contact hole CH3 for connecting the drain electrode D1 of the first thin film transistor TR1 and one electrode C12 of the first capacitor was located. ) and the gate electrode G2 of the second thin film transistor TR2 may be formed. As a result, the range of the contact hole forming area is widened, thereby improving the efficiency and accuracy of the contact hole forming process.

In this way, according to another embodiment of the present invention, the process of forming the capacitor can be simplified and the accuracy of the process can be improved.

Hereinafter, a method of manufacturing the thin film transistor substrate 100 according to an embodiment of the present invention will be described with reference to FIGS. 13A to 13G. 13a to 13g are manufacturing process diagrams of the thin film transistor substrate 100 according to an embodiment of the present invention.

Referring to FIG. 13A , a light blocking layer LS is formed on the substrate 110 .

Glass may be used as the substrate 110, or plastic that can be bent or bent may be used. An example of a plastic used as the substrate 110 is polyimide.

When plastic is used as the substrate 110, processes such as deposition and etching may be performed while the plastic substrate is disposed on a carrier substrate made of a highly durable material such as glass.

The light blocking layer LS may be made of a material that reflects or absorbs light. For example, the light blocking layer LS may be made of an electrically conductive material such as metal.

Referring to FIG. 13B , a buffer layer 120 is formed on the substrate 110 on which the light blocking layer LS is formed, and a semiconductor having a region overlapping the light blocking layer LS and a region not overlapping the light blocking layer LS on the buffer layer 120 Layer 130 is formed.

The semiconductor layer 130 is IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based and ITZO ( It may include at least one of InSnZnO)-based oxide semiconductor materials. The semiconductor layer 130 may be formed by deposition or sputtering. Although the semiconductor layer 130 having a single-layer structure is shown in FIG. 13B, an embodiment of the present invention is not limited thereto, and the semiconductor layer 130 may have a multi-layer structure. For example, the semiconductor layer 130 may have a two-layer bi-layer structure (see FIG. 2).

Next, referring to FIG. 13C, a gate insulating film 140 is formed on the semiconductor layer 130, and thereon, the gate electrode 160 is spaced apart from the semiconductor layer 130 and at least partially overlaps the semiconductor layer 130. is formed

Referring to FIG. 13D , light L is irradiated to the substrate 110 on the light blocking layer LS side. At this time, the light blocking layer LS serves as a mask to block light L. Accordingly, the light L is not irradiated to a region of the semiconductor layer 130 that overlaps the light blocking layer LS, and the light L is irradiated only to a region that does not overlap the light blocking layer LS. By irradiating light (L), a portion of the semiconductor layer 130 is made conductive. As a result, a region of the semiconductor layer 130 that does not overlap with the light blocking layer LS becomes conductive.

As the light L, for example, ultraviolet light may be used.

However, an embodiment of the present invention is not limited thereto, and light L may be irradiated even before forming the gate electrode 160 . Specifically, light (L) irradiation may be performed before or after forming the gate electrode 160 .

FIG. 13E shows that the conductive parts 132 and 133 are formed. One of the conductive portions 132 and 133 is a source region 132 and the other is a drain region 133 .

The gate electrode 160 overlaps the channel portion 131, which is a region overlapping the light blocking layer LS, and the conductive portions 132 and 133, which are regions that do not overlap the light blocking layer LS, in the semiconductor layer 130. ) overlaps with at least a portion of

Among the conductive parts 132 and 133 of the semiconductor layer 130, the drain region 133 overlapping the gate electrode 160 becomes the first electrode 511 of the capacitor Cap and overlaps the drain region 133. A part of the gate electrode 160 becomes the second electrode 512 of the capacitor Cap to form the capacitor Cap.

Referring to FIG. 13F , an interlayer insulating layer 150 is formed on the gate electrode 160 . At this time, a contact hole CH is formed in the interlayer insulating film 150 .

Referring to FIG. 13G , a connection electrode 185 is formed on the interlayer insulating layer 150 . The connection electrode 185 is connected to the gate electrode 160 . Through this process, the thin film transistor substrate 100 according to an embodiment of the present invention may be formed.

14a and 14b are manufacturing process diagrams of a thin film transistor substrate according to another embodiment of the present invention.

Referring to FIG. 14A , light L may be irradiated after the light blocking layer LS is formed on the substrate 110 and the semiconductor layer 130 is formed on the light blocking layer LS.

Referring to FIG. 14B , conductor portions 132 and 133 of the semiconductor layer 130 are formed by light (L) irradiation, and a channel portion 131 is defined. Next, the gate insulating layer 140 and the gate electrode 160 may be formed.

The present invention described above is not limited by the above-described embodiments and the accompanying drawings, and it is in the technical field to which the present invention belongs that various substitutions, modifications, and changes are possible within the scope without departing from the technical details of the present invention. It will be clear to those skilled in the art. Therefore, the scope of the present invention is indicated by the claims to be described later, and all changes or modifications derived from the meaning, scope and equivalent concepts of the claims should be construed as being included in the scope of the present invention.

100, 200, 300, 400: thin film transistor substrate
600: display device
110: substrate 120: buffer layer
130: semiconductor layer 131: channel portion
132 source region 133 drain region
140: gate insulating film 150: interlayer insulating film
155: protective film 160: gate electrode
170: source electrode 180: drain electrode
710: pixel electrode 720: light emitting layer
730: common electrode 750: bank
OLED: organic light emitting diode

Claims (16)

Board;
a light blocking layer on the substrate;
a buffer layer on the light blocking layer;
a semiconductor layer on the buffer layer; and
A gate electrode spaced apart from the semiconductor layer and at least partially overlapping the semiconductor layer; includes,
The semiconductor layer includes a channel portion and a conductor portion,
Some of the conductive parts are source regions and others are drain regions;
the light blocking layer overlaps the channel portion of the semiconductor layer and does not overlap the conductive portion;
Of the semiconductor layer, a region overlapping the light blocking layer is the channel portion, and a region not overlapping the light blocking layer is the conducting portion.
thin film transistor substrate. According to claim 1,
The thin film transistor substrate of claim 1 , wherein the semiconductor layer includes an oxide semiconductor material. According to claim 1,
The thin film transistor substrate of claim 1 , wherein the gate electrode overlaps the channel portion of the semiconductor layer and also overlaps at least a part of the conductive portion. According to claim 1,
The gate electrode overlaps the conductive portion of the semiconductor layer to form a capacitor. According to claim 1,
The thin film transistor substrate, wherein the semiconductor layer includes a first semiconductor layer on the substrate and a second semiconductor layer on the first semiconductor layer. Board;
a light blocking layer on the substrate;
a buffer layer on the light blocking layer;
a pixel driver disposed on the buffer layer and including at least one thin film transistor; and
It includes; a light emitting element connected to the pixel driver,
The thin film transistor,
a semiconductor layer on the buffer layer; and
A gate electrode spaced apart from the semiconductor layer and at least partially overlapping the semiconductor layer; includes,
The semiconductor layer includes a channel portion and a conductor portion,
Some of the conductive parts are source regions, others are drain regions,
The light blocking layer overlaps the channel portion of the semiconductor layer and does not overlap the conductive portion,
Of the semiconductor layer, a region overlapping the light blocking layer is the channel portion, and a region not overlapping the light blocking layer is the conducting portion.
display device. According to claim 6,
The semiconductor layer includes an oxide semiconductor material, the display device. According to claim 6,
The display device according to claim 1 , wherein the gate electrode overlaps the channel portion of the semiconductor layer and also overlaps at least a part of the conductive portion. According to claim 8,
The conductive portion and the gate electrode overlapping each other form a capacitor. According to claim 6,
The semiconductor layer includes a first semiconductor layer on the substrate and a second semiconductor layer on the first semiconductor layer. According to claim 6,
The light emitting element is an organic light emitting diode, a display device. forming a light blocking layer on the substrate;
forming a buffer layer on the light blocking layer;
forming a semiconductor layer having an overlapping region and a non-overlapping region with the light blocking layer on the buffer layer;
Forming a gate electrode spaced apart from the semiconductor layer and at least partially overlapping the semiconductor layer; and
Conducting a region of the semiconductor layer that does not overlap with the light blocking layer by irradiating light to the substrate on the side of the light blocking layer;
A method for manufacturing a thin film transistor substrate. According to claim 12,
The method of manufacturing a thin film transistor substrate, wherein the semiconductor layer includes an oxide semiconductor material. According to claim 12,
The light irradiation is performed before or after the step of forming the gate electrode, a method of manufacturing a thin film transistor substrate. According to claim 12,
The method of manufacturing a thin film transistor substrate in which the light is ultraviolet light. According to claim 12,
The method of manufacturing a thin film transistor substrate, wherein the gate electrode overlaps with a region overlapping the light blocking layer and also overlaps at least a part of a region that does not overlap the light blocking layer in the semiconductor layer.

Images