KR20230034839A - Thin film transistor substrate and display apparatus comprising the same - Google Patents

Abstract

In accordance with one embodiment of the present invention, provided are a thin film transistor substrate and a display device including the same. The thin film transistor substrate includes a first thin film transistor and a second thin film transistor on a base substrate, wherein the first thin film transistor includes a first active layer on the base substrate and a first gate electrode spaced apart from the first active layer, the second thin film transistor includes a second active layer on the base substrate, a second gate electrode spaced apart from the second active layer, and an auxiliary gate electrode between the second active layer and the second gate electrode, the first active layer and the second active layer are integrated to be connected with each other, the auxiliary gate electrode is integrated with the first gate electrode to be spaced apart from the second active layer and the second gate electrode, and the second gate electrode covers the auxiliary gate electrode. Therefore, the present invention is capable of easily securing a capacitor area.

Description

Thin film transistor substrate and display device including the same {THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY APPARATUS COMPRISING THE SAME}

One embodiment of the present invention relates to a thin film transistor substrate and a display device including the same.

The importance of display devices is increasing with the development of multimedia, and recently, flat panel displays such as liquid crystal displays, plasma displays, and organic light emitting displays have been commercialized.

Thin film transistors having various functions are disposed in the flat panel display device. For example, an organic light emitting display device includes a driving transistor for driving a pixel and a switching transistor for controlling the driving transistor. In order to improve display quality and efficiently control light emission of pixels, various thin film transistors, such as transistors for controlling light emission and transistors for sensing functions of the transistors, may be disposed in the display device.

Recently, as display devices have become high quality and high resolution, thin film transistors are being integrated at a high density in display devices. As a result, since a large number of thin film transistors are disposed in a limited area, a capacitor area may not be sufficiently secured. Therefore, when a large number of thin film transistors are disposed in a display device, it is necessary to efficiently arrange the thin film transistors and wires connected thereto.

One embodiment of the present invention is to provide a thin film transistor substrate capable of efficiently arranging a large number of thin film transistors and wires connected thereto.

One embodiment of the present invention is to provide a thin film transistor substrate capable of smoothly exhibiting the function of a thin film transistor even when a signal wire and a gate electrode of the thin film transistor overlap each other.

Another embodiment of the present invention is to provide a display device including the thin film transistor substrate as described above.

One embodiment of the present invention is to provide a display device in which driving of a driving transistor can be smoothly controlled even when a light emitting control line for light emitting control and a gate electrode of a driving transistor overlap each other.

An embodiment of the present invention for achieving the above technical problem includes a first thin film transistor and a second thin film transistor on a base substrate, wherein the first thin film transistor includes a first active layer on the base substrate and the first thin film transistor. and a first gate electrode spaced apart from the active layer, and the second thin film transistor includes a second active layer on the base substrate, a second gate electrode spaced apart from the second active layer, and the second active layer and the second active layer. and an auxiliary gate electrode between gate electrodes, the first active layer and the second active layer are integrally formed and connected to each other, and the auxiliary gate electrode is integrally formed with the first gate electrode to form the second active layer. It is spaced apart from a layer and the second gate electrode, wherein the second gate electrode at least partially overlaps the auxiliary gate electrode.

The same voltage as that of the first gate electrode may be applied to the auxiliary gate electrode.

When the second thin film transistor is turned on, the first thin film transistor may be turned on.

When a second gate voltage is applied to the second gate electrode, the first gate voltage may be applied to the first gate electrode.

The second active layer includes a channel portion, a first connection portion contacting one side of the channel portion, and a second connection portion contacting the other side of the channel portion, wherein a portion of the channel portion overlaps the auxiliary gate electrode, and the channel portion overlaps with the auxiliary gate electrode. Another part of the portion may not overlap the auxiliary gate electrode.

The other part of the channel portion that does not overlap the auxiliary gate electrode may overlap the second gate electrode.

A portion of the channel portion toward the first connection portion may overlap the auxiliary gate electrode and may not overlap the second gate electrode.

A portion of the channel portion toward the second connection portion may overlap the auxiliary gate electrode and may not overlap the second gate electrode.

The first active layer and the second active layer may include IGZO (InGaZnO)-based oxide semiconductor material, IZO (InZnO)-based oxide semiconductor material, IGZTO (InGaZnSnO)-based oxide semiconductor material, ITZO (InSnZnO)-based oxide semiconductor material, FIZO (FeInZnO)-based oxide semiconductor material, ZnO-based oxide semiconductor material, SIZO (SiInZnO)-based oxide semiconductor material, ZnON (Zn-Oxynitride)-based oxide semiconductor material, GZO (GaZnO)-based oxide semiconductor material, IGO (InGaO)-based oxide semiconductor It may include at least one of a material and a GZTO (GaZnSnO)-based oxide semiconductor material.

The first active layer and the second active layer may each include a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer.

The thin film transistor substrate includes a first light-blocking layer on the base substrate and a second light-blocking layer on the first light-blocking layer, the first light-blocking layer and the second light-blocking layer being spaced apart from each other and overlapping each other; One of the light blocking layer and the second light blocking layer may be connected to the second active layer, and the other of the first light blocking layer and the second light blocking layer may be connected to the second gate electrode.

The first light blocking layer and the second light blocking layer may form a capacitor.

Another embodiment of the present invention provides a display device including the thin film transistor substrate.

The first thin film transistor may be a light emitting control transistor, and the second thin film transistor may be a driving transistor.

An emission control signal may be applied to the first gate electrode and the auxiliary gate electrode.

The first gate electrode and the auxiliary gate electrode may be part of an emission control line.

A storage capacitor may be formed by overlapping the first light blocking layer and the second light blocking layer.

The display device includes a driving transistor, a light emitting control transistor, and a switching transistor, and an active layer of the driving transistor and an active layer of the light emitting transistor are integrally formed, and may be distinguished from an active layer of the switching transistor.

The display device may further include a sensing transistor, and an active layer of the sensing transistor may be integrally formed with an active layer of the driving transistor and an active layer of the light emitting transistor, and may be distinguished from an active layer of the switching transistor.

According to one embodiment of the present invention, a large number of thin film transistors and wires connected thereto can be efficiently arranged, so that thin film transistors can be integrated at a high density. In particular, according to one embodiment of the present invention, even when the signal wiring and the gate electrode of the thin film transistor overlap, the function of the thin film transistor can be exhibited smoothly. Excellent space utilization. In addition, according to an embodiment of the present invention, a capacitor area can be easily secured.

In the display device according to an exemplary embodiment of the present invention, driving of the driving transistor can be smoothly controlled even when the emission control line and the gate electrode of the driving transistor overlap. Accordingly, the display device may have excellent display performance because it is easy to arrange elements in the display device and secure a space for the storage capacitor so that the driving voltage of the pixel can be stably charged and controlled.

1A is a plan view of a thin film transistor substrate according to an embodiment of the present invention.
Figure 1b is a cross-sectional view taken along II' of Figure 1a.
1C is a partially enlarged view of a channel portion, a second gate electrode, and an auxiliary gate electrode of a second active layer.
2 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
3A is a plan view of a thin film transistor substrate according to another exemplary embodiment of the present invention.
FIG. 3B is a cross-sectional view taken along line II-II' of FIG. 3A.
4 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
5 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
6 is a schematic diagram of a display device according to another exemplary embodiment of the present invention.
FIG. 7 is a circuit diagram of one pixel of FIG. 6 .
FIG. 8 is a plan view of the pixel of FIG. 7 .
9 is a cross-sectional view taken along line III-III' of FIG. 8 .
FIG. 10 is a cross-sectional view taken along line IV-IV' of FIG. 8 .

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various forms different from each other, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to inform those who have the scope of the invention. The invention is only defined by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, the present invention is not limited to those shown in the drawings. Like elements may be referred to by like reference numerals throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

When "includes", "has", "consists of", etc. mentioned in this specification is used, other parts may be added unless the expression "only" is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

For example, when the positional relationship of two parts is described as "on", "upper", "below", "beside", etc., the expression "immediately" or "directly" is used. Unless otherwise specified, one or more other parts may be located between the two parts.

The spatially relative terms "below, beneath", "lower", "above", "upper", etc., refer to one element or component as shown in the drawing. It can be used to easily describe the correlation between and other elements or components. Spatially relative terms should be understood as terms that include different orientations of elements in use or operation in addition to the directions shown in the figures. For example, when flipping elements shown in the figures, elements described as “below” or “beneath” other elements may be placed “above” the other elements. Thus, the exemplary term “below” may include directions of both below and above. Likewise, the exemplary terms "above" or "above" can include both directions of up and down.

In the case of a description of a temporal relationship, for example, "immediately" or "directly" when a temporal precedence relationship is described, such as "after", "following", "after", "before", etc. Unless the expression is used, non-continuous cases may also be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, "at least one of the first item, the second item, and the third item" means not only the first item, the second item, or the third item, respectively, but also two of the first item, the second item, and the third item. It may mean a combination of all items that can be presented from one or more.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship. may be

In adding reference numerals to components of each drawing describing the embodiments of the present invention, the same components may have the same numerals as much as possible even though they are displayed on different drawings.

In the embodiments of the present invention, the source electrode and the drain electrode are only distinguished for convenience of description, and the source electrode and the drain electrode may be interchanged. The source electrode may serve as the drain electrode, and the drain electrode may serve as the source electrode. Also, a source electrode of one embodiment may be a drain electrode in another embodiment, and a drain electrode of one embodiment may be a source electrode in another embodiment.

In some embodiments of the present invention, a source connection part and a source electrode are distinguished and a drain connection part and a drain electrode are distinguished for convenience of explanation, but the embodiments of the present invention are not limited thereto. The source connection part may be a source electrode, and the drain connection part may be a drain electrode. Also, the source connection part may be the drain electrode, and the drain region may be the source electrode.

1A is a plan view of a thin film transistor substrate 100 according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line II' of FIG. 1A.

The thin film transistor substrate 100 according to an embodiment of the present invention includes a first thin film transistor TFT1 and a second thin film transistor TFT2 on a base substrate 110 .

Referring to FIGS. 1A and 1B , the first thin film transistor TFT1 may include a first active layer 130 on a base substrate 110 and a first gate electrode 150 spaced apart from the first active layer 130 . can The second thin film transistor TFT includes a second active layer 230 on the base substrate 110, a second gate electrode 250 spaced apart from the second active layer 230, and a second active layer 230 and a second active layer 230. An auxiliary gate electrode 240 may be included between the gate electrodes 250 .

Hereinafter, each component of the thin film transistor substrate 100 according to an embodiment of the present invention will be described in detail.

Glass or plastic may be used as the base substrate 110 . As the plastic, a transparent plastic having a flexible property, such as polyimide, may be used. When polyimide is used as the base substrate 110, considering that a high-temperature deposition process is performed on the base substrate 110, heat-resistant polyimide that can withstand high temperatures may be used.

Light blocking layers 111 and 112 may be disposed on the base substrate 110 . The light blocking layers 111 and 112 may block light incident from the outside to protect the thin film transistors TFT1 and TFT2. The light blocking layers 111 and 112 may be omitted.

According to an embodiment of the present invention, the light blocking layers 111 and 112 may overlap at least one of the first thin film transistor TFT1 and the second thin film transistor TFT2. The light blocking layers 111 and 112 may, in particular, overlap the second thin film transistor TFT2.

Referring to FIGS. 1A and 1B , a first light blocking layer 111 may be disposed on a base substrate 110 and a first buffer layer 121 may be disposed on the first light blocking layer 111 . A second light blocking layer 112 may be disposed on the first buffer layer 121 , and a second buffer layer 122 may be disposed on the second light blocking layer 112 .

The buffer layers 121 and 122 may be made of an insulating material. For example, the buffer layers 121 and 122 may include at least one of insulating materials such as silicon oxide, silicon nitride, and metal-based oxide. The buffer layers 121 and 122 may have a single film structure or a multi-layer structure.

The buffer layers 121 and 122 may protect the active layers 130 and 230 by blocking air and moisture. In addition, the upper surface of the base substrate 110 on which the light blocking layers 111 and 112 are disposed may be uniform by the buffer layers 121 and 122 .

The first light blocking layer 111 and the second light blocking layer 112 may be spaced apart from each other and overlap each other. One of the first light blocking layer 111 and the second light blocking layer 112 is connected to the second active layer 230, and the other of the first light blocking layer 111 and the second light blocking layer 112 is 2 may be connected to the gate electrode 250 . Specifically, the first light blocking layer 111 may be connected to the second gate electrode 250 , and the second light blocking layer 112 may be connected to the second active layer 230 .

1A and 1B, the first light blocking layer 111 is connected to the second gate electrode 250 through the contact hole, and the second light blocking layer 112 is connected to the second active layer 230 through the contact hole. A configuration connected to two connection parts 230b is disclosed.

According to an embodiment of the present invention, the first light blocking layer 111 and the second light blocking layer 112 may form a capacitor (Cap).

Referring to FIG. 1B , the first active layer 130 and the second active layer 230 may be disposed on the second buffer layer 122 .

Referring to FIGS. 1A and 1B , the first active layer 130 and the second active layer 230 may be integrally formed and connected to each other.

According to an embodiment of the present invention, the first active layer 130 and the second active layer 230 may be formed of the same semiconductor material. The first active layer 130 and the second active layer 230 may include an oxide semiconductor material.

The first active layer 130 and the second active layer 230 may include, for example, GZO (InGaZnO)-based oxide semiconductor material, IZO (InZnO)-based oxide semiconductor material, IGZTO (InGaZnSnO)-based oxide semiconductor material, ITZO ( InSnZnO)-based oxide semiconductor material, FIZO (FeInZnO)-based oxide semiconductor material, ZnO-based oxide semiconductor material, SIZO (SiInZnO)-based oxide semiconductor material, ZnON (Zn-Oxynitride)-based oxide semiconductor material, GZO (GaZnO)-based oxide semiconductor material , IGO (InGaO)-based oxide semiconductor material and GZTO (GaZnSnO)-based oxide semiconductor material may include at least one.

However, one embodiment of the present invention is not limited thereto, and the first active layer 130 and the second active layer 230 may be formed by other semiconductor materials known in the art.

The first active layer 130 may include a channel portion 130n, a first connection portion 130a, and a second connection portion 130b. The first connection part 130a of the first active layer 130 may be connected to one side of the channel part 130n, and the second connection part 130b may be connected to the other side of the channel part 130n.

The second active layer 230 may include a channel portion 230n, a first connection portion 230a, and a second connection portion 230b. The first connection part 230a of the second active layer 230 may be connected to one side of the channel part 230n, and the second connection part 230b may be connected to the other side of the channel part 230n.

The first connection parts 130a and 230a and the second connection parts 130b and 230b may be formed by selectively conducting the first active layer 130 and the second active layer 230 .

Referring to FIG. 1B , the second connection portion 130b of the first active layer 130 and the first connection portion 230a of the second active layer 230 may be connected to each other. Since the first active layer 130 and the second active layer 230 are made of the same material, the second connection portion 130b of the first active layer 130 and the first connection portion of the second active layer 230 ( 230a) may not be clear.

The first connection parts 130a and 230a and the second connection parts 130b and 230b are distinguished for convenience of description, and their positions may be independently interchanged.

Referring to FIG. 1B , a first gate insulating layer 141 is disposed on the first active layer 130 and the second active layer 230 . The first gate insulating layer 141 may be disposed on the first active layer 130 and the second active layer 230 and on the second buffer layer 122 .

The first gate insulating layer 141 has insulating properties and protects the first active layer 130 and the second active layer 230 . The first gate insulating layer 141 may include at least one of silicon oxide, silicon nitride, and metal-based oxide. The first gate insulating layer 141 may have a single layer structure or a multi-layer structure.

A first gate electrode 150 and an auxiliary gate electrode 240 are disposed on the first gate insulating layer 141 . Referring to FIGS. 1A and 1B , the auxiliary gate electrode 240 may be integrally formed with the first gate electrode 150 . The auxiliary gate electrode 240 may be connected to the first gate electrode 150 .

According to an embodiment of the present invention, the same voltage as that of the first gate electrode 150 may be applied to the auxiliary gate electrode 240 . Specifically, when the first gate voltage is applied to the first gate electrode 150 , the first gate voltage may also be applied to the auxiliary gate electrode 240 .

According to an embodiment of the present invention, the first gate electrode 150 and the auxiliary gate electrode 240 may be formed by wires passing through the first active layer 130 and the second active layer 230 . For example, a portion overlapping the first active layer 130 among wires passing through the first active layer 130 and the second active layer 230 may become the first gate electrode 150 .

The first gate electrode 150 is spaced apart from the first active layer 130 and at least partially overlaps the first active layer 130 . The first gate electrode 150 overlaps the channel portion 130n of the first active layer 130 .

A portion overlapping the second active layer 230 among wires passing through upper portions of the first active layer 130 and the second active layer 230 may become the auxiliary gate electrode 240 . Referring to FIG. 1B , the auxiliary gate electrode 240 is spaced apart from the second active layer 230 and the second gate electrode 250 .

A second gate insulating layer 142 is disposed on the first gate electrode 150 and the auxiliary gate electrode 240 . The second gate insulating layer 142 may include at least one of silicon oxide, silicon nitride, and metal-based oxide. The second gate insulating film 142 may have a single film structure or a multi-layer structure.

Referring to FIG. 1B , the second gate insulating layer 142 may cover the entire upper area of the base substrate 110 .

The second gate electrode 250 is disposed on the second gate insulating layer 142 .

The second gate electrode 250 is spaced apart from the second active layer 230 and at least partially overlaps the second active layer 230 . The second gate electrode 250 overlaps the channel portion 230n of the second active layer 230 .

According to an embodiment of the present invention, an auxiliary gate electrode 240 is disposed between the second active layer 230 and the second gate electrode 250 .

According to an embodiment of the present invention, the second gate electrode 250 at least partially overlaps the auxiliary gate electrode 240 . The second gate electrode 250 may cover the auxiliary gate electrode 240 . Referring to FIGS. 1A and 1B , the second gate electrode 250 may cover the entirety of the auxiliary gate electrode 240 in plan view.

Referring to FIG. 1B , the second gate electrode 250 may completely cover the auxiliary gate electrode 240 in plan view. However, one embodiment of the present invention is not limited thereto, and the second gate electrode 250 may partially cover the auxiliary gate electrode 240 in plan view.

According to an embodiment of the present invention, the first connection parts 130a and 230a and the second connection parts 130b and 230b are formed by conductorization using the first gate electrode 150 and the second gate electrode 250 as masks. can be formed. For example, after forming the second gate electrode 250, the first active layer 130 and the second active layer 130 and the second active layer are formed by doping using the first gate electrode 150 and the second gate electrode 250 as a mask. Selective conductorization of layer 230 may be achieved. As a result, the first connection part 130a and the second connection part 130b of the first active layer 130 are formed, and the first connection part 230a and the second connection part 230b of the second active layer 230 can be formed

However, the conductorization method according to an embodiment of the present invention is not limited to doping, and conductorization may be performed by other methods known in the art. For example, the gate insulating films 141 and 142 may be made conductive by etching and plasma treatment.

An interlayer insulating layer 170 may be disposed on the second gate electrode 250 . The interlayer insulating film 170 is an insulating layer made of an insulating material. The interlayer insulating film 170 may be made of an organic material, an inorganic material, or a laminate of an organic material layer and an inorganic material layer.

A source electrode 161 of the first thin film transistor TFT1 and a drain electrode 262 of the second thin film transistor TFT2 may be disposed on the interlayer insulating layer 170 . The source electrode 161 of the first thin film transistor TFT1 may be connected to the first active layer 130 . The drain electrode 262 of the second thin film transistor TFT2 may be connected to the second active layer 230 .

However, an embodiment of the present invention is not limited thereto, and according to an embodiment of the present invention, indicator number “161” may be a drain electrode of the first thin film transistor TFT1. Also, the indicator number 262 may be a source electrode of the second thin film transistor TFT2.

The source electrode 161 of the first thin film transistor TFT1 and the drain electrode 262 of the second thin film transistor TFT2 are made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), or titanium, respectively. It may include at least one of (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. The source electrode 161 of the first thin film transistor TFT1 and the drain electrode 262 of the second thin film transistor TFT2 may each be formed of a single layer made of a metal or a metal alloy, or may be formed of two or more multi-layers. there is.

In general, there are many cases in which a plurality of thin film transistors are connected to each other and operated in an electronic device. In an electronic device to which the first thin film transistor TFT1 and the second thin film transistor TFT2 according to an embodiment of the present invention are applied, the first active layer 130 and the second active layer 230 are designed to be connected to each other. It can be. In this case, since the first active layer 130 and the second active layer 230 are connected to each other, a separate electrode or pad for connecting the first active layer 130 and the second active layer 230 is required. It is not necessary. Therefore, it is not necessary to form contact holes to connect the first active layer 130 and the second active layer 230 to each other.

According to an embodiment of the present invention, one of the first connection parts 130a and 230a and the second connection parts 130b and 230b may serve as a source region and the other may serve as a drain region. Without a separate electrode or a separate pad member, the first connection portions 130a and 230a or the second connection portions 130b and 230b may serve as a source electrode or a drain electrode, respectively.

1C is a partially enlarged view of the channel portion 230n, the second gate electrode 250 and the auxiliary gate electrode 240 of the second active layer 230 .

Referring to FIG. 1C , the auxiliary gate electrode 240 is disposed between the second active layer 230 and the second gate electrode 250 and may be covered by the second gate electrode 250 .

The length L2 of the second gate electrode 250 is greater than the length L1 of the auxiliary gate electrode 240 . The length L2 of the second gate electrode 250 may be substantially the same as the length of the channel portion 230n of the second active layer 230 .

A portion ar1 of the channel portion 230n of the second active layer 230 overlaps the auxiliary gate electrode 240, and the other portions ar2 and ar3 of the channel portion 230n of the second active layer 230 overlap. may not overlap with the auxiliary gate electrode 240 . Specifically, the channel portion 230n of the second active layer 230 overlaps the first region ar1 overlapping both the auxiliary gate electrode 240 and the second gate electrode 250 and the auxiliary gate electrode 240. It may include a second region ar2 and a third region ar3 overlapping the second gate electrode 250 without being removed. The second and third regions ar2 and ar3 of the channel portion 230n of the second active layer 230 do not overlap the auxiliary gate electrode 240 but overlap the second gate electrode 250 .

Referring to FIG. 1C , the second region ar2, which is a part of the channel portion 230n of the second active layer 230 toward the first connection portion 230a, does not overlap with the auxiliary gate electrode 240 and the second gate electrode overlaps with (250). In addition, the third region ar3, which is a part of the channel portion 230n of the second active layer 230 on the side of the second connection portion 230b, does not overlap with the auxiliary gate electrode 240 and does not overlap with the second gate electrode 250. overlap

The length of the second area ar2 and the length of the third area ar3 may be the same or different. One of the second area ar2 and the third area ar3 may have a greater length than the other.

The length of any one of the length of the second area ar2 and the length of the third area ar3 may be 0 (zero). Specifically, either the second area ar2 or the third area ar3 may not exist. In this case, the other one of the second area ar2 and the third area ar3 must exist.

Since the auxiliary gate electrode 240 is connected to the first gate electrode 150, when a turn-on voltage is applied to the first gate electrode 150, the same turn-on voltage is applied to the auxiliary gate electrode 150. It is applied to the gate electrode 240 as well.

Since the second region ar2 and the third region ar3 of the channel portion 230n of the second active layer 230 do not overlap the auxiliary gate electrode 240, the auxiliary gate electrode 240 is turned on. Even if the -On voltage is applied, if the turn-on voltage is not applied to the second gate electrode 250, the channel portion 230n of the second active layer 230 does not have current characteristics. Therefore, even if the auxiliary gate electrode 240 is disposed closer to the second active layer 230 than the second gate electrode 250, the auxiliary gate electrode 240 alone does not control driving of the second thin film transistor TFT2. can not do it.

Also, an electric field applied by the second gate electrode 250 may be covered by the auxiliary gate electrode 240 . Therefore, even if the turn-on voltage is applied to the second gate electrode 250, if the turn-on voltage is not applied to the auxiliary gate electrode 240, the channel portion of the second active layer 230 (230n) does not have current characteristics. Therefore, according to an embodiment of the present invention, when a turn-on voltage is applied to the second gate electrode 250 to drive the second thin film transistor TFT2, the auxiliary gate electrode 240 is turned on. (Turn-On) Voltage is applied. When a turn-on voltage is applied to the auxiliary gate electrode 240 , a turn-on voltage may be applied to the second gate electrode 250 .

According to an embodiment of the present invention, the first thin film transistor TFT1 is configured to be turned on when the second thin film transistor TFT2 is turned on. The second thin film transistor TFT2 is turned on when the first thin film transistor TFT1 is turned on.

Further, according to an embodiment of the present invention, when the second gate voltage is applied to the second gate electrode 250, the first gate voltage is applied to the first gate electrode 150. As a result, driving of the second thin film transistor TFT2 can be controlled by the second gate electrode 250 .

According to an embodiment of the present invention, when the first thin film transistor TFT1 is turned on, the second thin film transistor TFT2 does not always have to be turned on. On the other hand, in a period in which the second thin film transistor TFT2 is turned on, the first thin film transistor TFT1 maintains a turned on state. In addition, even when the first thin film transistor TFT1 is in a turn-on state and a turn-on voltage is applied to the auxiliary gate electrode 240, the second gate electrode 250 is turned off. The second thin film transistor TFT2 may be turned off by applying a turn-off voltage. Accordingly, it can be said that the turn-on and turn-off of the second thin film transistor TFT2 are controlled by the second gate electrode 250 .

2 is a cross-sectional view of a thin film transistor substrate 200 according to another embodiment of the present invention. Hereinafter, in order to avoid redundancy, descriptions of components already described are omitted.

Referring to FIG. 2 , the first gate insulating layer 141 and the second gate insulating layer 142 may be patterned. The first gate insulating layer 141 and the second gate insulating layer 142 may be patterned by etching or ashing.

For example, after the first gate electrode 150, the auxiliary gate electrode 240, and the second gate electrode 250 are formed, the first gate electrode 150 and the second gate electrode 250 are used as masks. The first gate insulating layer 141 and the second gate insulating layer 142 may be patterned. As a result, the first gate insulating film 141 remains under the first gate electrode 150, and the first gate insulating film 141 and the second gate insulating film 142 remain under the second gate electrode 250. can

FIG. 3A is a plan view of a thin film transistor substrate 300 according to another embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along line II-II′ of FIG. 3A.

3A and 3B, a first light blocking layer 111 is disposed on a base substrate 110, a first buffer layer 121 is disposed on the first light blocking layer 111, and a first buffer layer ( 121), a second light blocking layer 112 may be disposed. In addition, an auxiliary light blocking layer 115 may be disposed on the first buffer layer 121 .

Referring to FIGS. 3A and 3B , the first light blocking layer 111 is connected to the second gate electrode 250 of the second thin film transistor TFT2 through the contact hole, and the second light blocking layer 112 is connected to the contact hole. It can be connected to the second active layer 230 of the second thin film transistor TFT2 through .

The first light blocking layer 111 and the second light blocking layer 112 may be spaced apart and overlap each other to form a capacitor Cap.

Referring to FIGS. 3A and 3B , the auxiliary light blocking layer 115 may be connected to the gate electrode 115 of the first thin film transistor TFT1 through the connection electrode 117 . In this case, the auxiliary light blocking layer 115 may serve as a gate electrode of the first thin film transistor TFT1. As a result, the first thin film transistor TFT1 may have a double gate structure.

4 is a cross-sectional view of a thin film transistor substrate 400 according to another embodiment of the present invention.

Referring to FIG. 4 , an auxiliary gate electrode 240 may be disposed on one side of the channel portion 230n of the second active layer 230 . The second gate electrode 250 covers at least a portion of the auxiliary gate electrode 240 and may extend to the other side of the channel portion 230n of the second active layer 230 . The second gate electrode 250 may not completely cover the auxiliary gate electrode 240 .

According to another embodiment of the present invention, the channel portion 230n of the second active layer 230 may overlap at least one of the second gate electrode 250 and the auxiliary gate electrode 240 . At least a portion of the channel portion 230n of the second active layer 230 may overlap both the second gate electrode 250 and the auxiliary gate electrode 240 .

A portion of the channel portion 230n of the second active layer 230 toward the first connection portion 230a may overlap the auxiliary gate electrode 240 and not overlap the second gate electrode 250 . In addition, although not shown in FIG. 4 , a part of the channel portion 230n of the second active layer 230 toward the second connection portion 230b overlaps the auxiliary gate electrode 240 and the second gate electrode 250 may not overlap with

FIG. 4 may correspond to the case where the length of the second area ar2 in FIG. 1C is 0 (zero). As shown in FIG. 4 , even when the second gate electrode 250 and the auxiliary gate electrode 240 are disposed, the first thin film transistor TFT1 is turned on in the period in which the second thin film transistor TFT2 is turned on ( Since the turn-on state is maintained, driving of the second thin film transistor TFT2 can be controlled by the second gate electrode 250 .

5 is a cross-sectional view of a thin film transistor substrate 500 according to another embodiment of the present invention.

Referring to FIG. 5 , the first active layer 130 and the second active layer 230 may have a multilayer structure. According to another embodiment of the present invention, the first active layer 130 and the second active layer 230 are formed on the first oxide semiconductor layers 131 and 231 and the first oxide semiconductor layers 131 and 231 . 2 oxide semiconductor layers 132 and 232 may be included.

Since the first active layer 130 and the second active layer 230 can be made with the same composition, the first oxide semiconductor layer 131 and the second active layer 230 of the first active layer 130 ) of the first oxide semiconductor layer 231 may be the same. Also, the second oxide semiconductor layer 132 of the first active layer 130 and the second oxide semiconductor layer 232 of the second active layer 230 may be the same.

The first oxide semiconductor layers 131 and 231 may have greater mobility than the second oxide semiconductor layers 132 and 232 . Accordingly, the first oxide semiconductor layers 131 and 231 may serve as a main channel layer. The second oxide semiconductor layers 132 and 232 may serve as support layers.

The first oxide semiconductor layer 131.231 may be formed of an oxide semiconductor material having high mobility characteristics. The second oxide semiconductor layers 132 and 232 may be formed of an oxide semiconductor material having excellent film stability. However, an embodiment of the present invention is not limited thereto, and the first oxide semiconductor layers 131 and 231 may have excellent film stability and the second oxide semiconductor layers 132 and 232 may have high mobility characteristics. .

As shown in FIG. 5 , a structure in which the active layers 130 and 230 are formed by stacking two semiconductor layers is referred to as a bi-layer structure.

Although not shown, a third oxide semiconductor layer may be disposed on the second oxide semiconductor layers 132 and 232 .

Hereinafter, display devices to which the above-described thin film transistor substrates 100, 200, 300, 400, and 500 are applied will be described in detail.

6 is a schematic diagram of a display device 600 according to another embodiment of the present invention.

As shown in FIG. 6 , a display device 600 according to another embodiment of the present invention may include a display panel 310, a gate driver 320, a data driver 330, and a control unit 340. can

The display panel 310 includes gate lines GL and data lines DL, and a pixel P is disposed in an intersection area of the gate lines GL and data lines DL. An image is displayed by driving the pixel P. The gate lines GL, the data lines DL, and the pixel P may be disposed on the base substrate 110 .

The controller 340 controls the gate driver 320 and the data driver 330 .

The controller 340 generates a gate control signal (GCS) for controlling the gate driver 320 and a data control signal (DCS) for controlling the data driver 330 by using a signal supplied from an external system (not shown). outputs In addition, the controller 340 samples input image data input from an external system, rearranges them, and supplies the rearranged digital image data RGB to the data driver 330 .

The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. Also, the gate control signal GCS may include control signals for controlling the shift register.

The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

The data driver 330 supplies data voltages to the data lines DL of the display panel 310 . Specifically, the data driver 330 converts the image data RGB input from the controller 340 into an analog data voltage and supplies the data voltage to the data lines DL.

According to an embodiment of the present invention, the gate driver 320 may be mounted on the display panel 310 . As such, a structure in which the gate driver 320 is directly mounted on the display panel 310 is referred to as a gate in panel (GIP) structure.

The gate driver 320 may include a shift register 350 .

The shift register 350 sequentially supplies gate pulses to the gate lines GL for one frame using the start signal and the gate clock transmitted from the controller 340 . Here, one frame refers to a period during which one image is output through the display panel 310 . The gate pulse has a turn-on voltage capable of turning on a switching element (thin film transistor) disposed in the pixel P.

In addition, the shift register 350 supplies a gate-off signal capable of turning off the switching element to the gate line GL during the remaining period in which the gate pulse is not supplied during one frame. Hereinafter, the gate pulse and the gate off signal are generically referred to as a scan signal (SS or Scan).

7 is a circuit diagram of one pixel P of FIG. 6, FIG. 8 is a plan view of the pixel P of FIG. 7, and FIG. 9 is a cross-sectional view taken along line III-III′ of FIG. 8. FIG. is a cross-sectional view taken along line IV-IV' in FIG. 8 .

The circuit diagram of FIG. 7 is an equivalent circuit diagram of the pixel P of the display device 600 including an organic light emitting diode (OLED) as the display element 710 .

According to another embodiment of the present invention, the pixel P of the display device 6000 includes an organic light emitting diode (OLED) as the display element 710 and a pixel driving circuit (PDC) that drives the display element 710. includes The display element 710 is connected to the pixel driving circuit PDC.

The pixel driving circuit PDC may include thin film transistors TR1 , TR2 , TR3 , and TR4 .

Specifically, the pixel driving circuit PDC of FIG. 7 includes a first thin film transistor TR1 as a light emission control transistor, a second thin film transistor TR2 as a driving transistor, a third thin film transistor TR3 as a sensing transistor, and a switching transistor. A fourth thin film transistor TR4 may be included.

According to another embodiment of the present invention, the pixel driving circuit PDC includes the first thin film transistor TFT1 and the second thin film transistor TFT2 of the thin film transistor substrates 100, 200, 300, 400, and 500 described above. ) may be included.

For example, the first thin film transistor TFT1 of the thin film transistor substrates 100 , 200 , 300 , 400 , and 500 described above may be applied as the light emitting control transistor TR1 . As the driving transistor, the second thin film transistor TR2 , the second thin film transistor TFT2 of the thin film transistor substrates 100 , 200 , 300 , 400 , and 500 described above may be applied.

In the pixel P, signal lines DL, EL, GL, PL, SCL, and RL for supplying driving signals to the pixel driving circuit PDC are disposed.

The data voltage Vdata is supplied to the data line DL, the scan signal SS is supplied to the gate line GL, and the driving voltage Vdd for driving the pixel is supplied to the driving power line PL. The reference voltage Vref is supplied to the reference line RL, and the sensing control signal SCS is supplied to the sensing control line SCL. In addition, the emission control signal EM is supplied to the emission control line EL.

The first thin film transistor TR1 serves as a light emission control transistor for controlling the light emission timing of the second thin film transistor TR2. The first thin film transistor TR1 transmits the driving voltage Vdd to the second thin film transistor TR2 or blocks the driving voltage Vdd according to the emission control signal EM. When the first thin film transistor TR1 is turned on, current is supplied to the second thin film transistor TR2 and light is output from the display element 710 .

The fourth thin film transistor TR4 as a switching transistor is connected to the gate line GL and the data line DL. The second thin film transistor TR2 as a driving transistor controls the amount of current output to the display element 710 according to the data voltage Vdata transmitted through the fourth thin film transistor TR4. The third thin film transistor TR3 as a sensing transistor senses the characteristics of the second thin film transistor TR2.

The storage capacitor Cst is positioned between the gate electrode of the second thin film transistor TR1 and the display element 710 .

Specifically, the fourth thin film transistor TR4 is turned on by the scan signal SS supplied to the gate line GL, and transmits the data voltage Vdata supplied to the data line DL to the second thin film transistor TR2. to the gate electrode of

The third thin film transistor TR3 is connected to the reference line RL, turned on or off by the sensing control signal SCS, and detects the characteristics of the second thin film transistor TR2 as a driving transistor during a sensing period.

The fourth thin film transistor TR4 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS supplied through the gate line GL.

The data line DL provides the data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls application of the data voltage Vdata.

The driving power line PL provides a driving voltage Vdd to the display element 710, and the second thin film transistor TR2 controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving the organic light emitting diode (OLED) as the display element 710 .

When the fourth thin film transistor TR4 is turned on by the scan signal SS applied from the gate driver 320 through the gate line GL, the data voltage Vdata supplied through the data line DL is displayed. It is supplied to the gate electrode of the second thin film transistor TR2 connected to the element 710 . The data voltage Vdata is charged in the storage capacitor Cst formed between the gate electrode and the source electrode of the second thin film transistor TR2.

The amount of current supplied to the organic light emitting diode (OLED), which is the display element 710, through the second thin film transistor TR2 is controlled according to the data voltage Vdata. Accordingly, the amount of light output from the display element 710 is controlled. Gradation can be controlled.

The pixel driving circuit PDC according to another embodiment of the present invention may be formed in various structures other than the structure described above. The pixel driving circuit PDC may include, for example, five or more thin film transistors.

Referring to FIGS. 8 , 9 and 10 , the first thin film transistor TR1 , the second thin film transistor TR2 , the third thin film transistor TR3 , and the fourth thin film transistor TR4 are formed on the base substrate 110 . is placed on

The base substrate 110 may be made of glass or plastic. As the base substrate 110, a plastic having a flexible property, for example, polyimide (PI) may be used.

Referring to FIGS. 9 and 10 , a first light blocking layer 111 is disposed on the base substrate 110 . In addition, data lines DL may be disposed on the base substrate 110 .

A first buffer layer 121 may be disposed on the first light blocking layer 111 . A second light blocking layer 112 may be disposed on the first buffer layer 121 , and a second buffer layer 122 may be disposed on the second light blocking layer 112 .

Active layers A1 , A2 , A3 , and A4 are disposed on the second buffer layer 122 .

8 and 9 , the first active layer A1 of the first thin film transistor TR1, the second active layer A2 of the second thin film transistor TR2, and the third active layer A1 of the second thin film transistor TR2 are formed on the second buffer layer 122. The third active layer A3 of the thin film transistor TR3 may be integrally formed. The first active layer A1, the second active layer A2, and the third active layer A3 formed integrally may form a first block.

A portion of the first active layer A1 is conductive and may serve as a drain electrode D1 of the first thin film transistor TR1.

A part of the second active layer A2 is conductive to serve as the drain electrode D2 of the second thin film transistor TR2, and the other part is conductive to serve as the source electrode S2 of the second thin film transistor TR2. ) can play a role.

A portion of the third active layer A1 is conductive and may serve as a drain electrode D3 of the third thin film transistor TR3.

Referring to FIGS. 8 and 9 , the second active layer A2 of the second thin film transistor TR2 may be connected to the second light blocking layer 112 through the second contact hole H2. The second light blocking layer 112 may be connected to the source electrode S2 of the second thin film transistor TR2.

Referring to FIGS. 8 and 10 , the fourth active layer A4 of the fourth thin film transistor TR4 is separately formed on the second buffer layer 122 . The fourth active layer A4 may constitute a second block distinct from the first active layer A1, the second active layer A2, and the third active layer A3.

A part of the fourth active layer A4 is conductive to serve as the drain electrode D4 of the fourth thin film transistor TR4, and the other part is conductive to serve as the source electrode S4 of the fourth thin film transistor TR4. ) can play a role.

Referring to FIGS. 8, 9, and 10 , the first active layer A1 of the first thin film transistor TR1 as a light emission control transistor and the second active layer A2 of the second thin film transistor TR2 as a driving transistor are formed. may be made integrally. The first active layer A1 of the first thin film transistor TR1, which is a light emitting control transistor, and the second active layer A2 of the second thin film transistor TR2, which is a driving transistor, are the components of the fourth thin film transistor TR4, which is a switching transistor. It may be distinguished from the fourth active layer A4.

In addition, the third active layer A3 of the third thin film transistor TR3 which is a sensing transistor includes the first active layer A1 of the first thin film transistor TR1 which is an emission control transistor and the second thin film transistor TR2 which is a driving transistor. ) may be integrally formed with the second active layer A2. The third active layer A3 of the third thin film transistor TR3 which is a sensing transistor may be distinguished from the fourth active layer A4 of the fourth thin film transistor TR4 which is a switching transistor.

Referring to FIGS. 8 and 10 , the fourth active layer A4 of the fourth thin film transistor TR4 may be connected to the first light blocking layer 111 through the sixth contact hole H6. Also, the fourth active layer A4 of the fourth thin film transistor TR4 may be connected to the data line through the seventh contact hole H7.

A first gate insulating layer 141 is disposed on the active layers A1 , A2 , A3 , and A4 .

An emission control line EL, a sensing control line SCL, and a gate line GL are disposed on the first gate insulating layer 141 .

A portion of the emission control line EL overlapping the first active layer A1 becomes the first gate electrode G1 of the first thin film transistor TR1. In addition, another portion of the emission control line EL overlapping the second active layer A becomes the auxiliary gate electrode 240 .

According to another embodiment of the present invention, the first gate electrode G1 and the auxiliary gate electrode 240 may be part of the emission control line EL. Accordingly, the emission control signal EM may be applied to the first gate electrode G1 and the auxiliary gate electrode 240 .

A portion of the sensing control line SCL overlapping the third active layer A3 becomes the third gate electrode G3 of the third thin film transistor TR3.

8 and 10 , a portion of the gate line GL overlapping the fourth active layer A4 becomes the fourth gate electrode G4 of the fourth thin film transistor TR4.

A second gate insulating layer 142 is disposed on the emission control line EL, the sensing control line SCL, and the gate line GL.

The reference line RL and the second gate electrode G2 of the second thin film transistor TR2 are disposed on the second gate insulating layer 142 . In addition, a pad electrode 165 is disposed on the second gate insulating layer 142 .

The reference line RL connects the third contact hole H3 to the third active layer A3 of the third thin film transistor TR3. The reference line RL may serve as a source electrode S3 of the third thin film transistor TR3.

Referring to FIG. 10 , the second gate electrode G2 of the second thin film transistor TR2 may be connected to the first light blocking layer 111 through the fourth contact hole H4. As a result, the second gate electrode G2 may be connected to the fourth thin film transistor TR4 through the first light blocking layer 111 .

The data voltage Vdata supplied through the data line DL is supplied to the second gate electrode G2 of the second thin film transistor TR2 via the fourth thin film transistor TR4 and the first light blocking layer 111. It can be.

The first light blocking layer 111 connected to the second gate electrode G2 may become the first capacitor electrode CE1 of the storage capacitor Cst.

The second light blocking layer 112 connected to the source electrode S2 of the second thin film transistor TR2 may serve as the second capacitor electrode CE2 of the storage capacitor Cst.

As a result, the storage capacitor Cst may be formed by overlapping the first capacitor electrode CE1 and the second capacitor electrode CE2 .

The first light-blocking layer 111 on which the thin film transistors TR1, TR2, TR3, and TR4 are disposed below becomes the first capacitor electrode CE1, and the second light-blocking layer 112 serves as the second capacitor electrode CE2. Since this can be the case, a large-area storage capacitor Cst can be formed regardless of the area of the thin film transistors TR1 , TR2 , TR3 , and TR4 .

Referring to FIG. 10 , the pad electrode 165 is connected to the second light blocking layer 112 through the fifth contact hole H5. As a result, the pad electrode 165 may be connected to the source electrode S2 of the second thin film transistor TR2 and the storage capacitor Cst.

An interlayer insulating layer 170 is disposed on the reference line RL, the second gate electrode G2 and the pad electrode 165 .

A driving power line PL is disposed on the interlayer insulating layer 170 .

The driving power line PL may be connected to the first active layer A1 of the first thin film transistor TR1 through the first contact hole H1. The driving power line PL may serve as a source electrode S1 of the first thin film transistor TR1.

The driving voltage Vdd may be transmitted to the first thin film transistor TR1 through the driving power line PL.

A planarization layer 175 is disposed on the driving power line PL. The planarization layer 175 planarizes upper portions of the thin film transistors TR1 , TR2 , TR3 , and TR4 and protects the thin film transistors TR1 , TR2 , TR3 , and TR4 .

The first electrode 711 of the display element 710 is disposed on the planarization layer 175 . Referring to FIG. 10 , the first electrode 711 of the display element 710 is connected to the pad electrode 165 through the eighth contact hole H8. As a result, the first electrode 711 of the display element 710 may be connected to the source electrode S2 of the second thin film transistor TR2 and the storage capacitor Cst.

A bank layer 750 is disposed on the edge of the first electrode 711 of the display element 710 . The bank layer 750 defines a light emitting area of the display element 710 .

An organic emission layer 712 is disposed on the first electrode 711 , and a second electrode 713 is disposed on the organic emission layer 712 . Thus, the display element 710 is completed. The display element 710 shown in FIG. 12 is an organic light emitting diode (OLED). Accordingly, the display device 600 according to an exemplary embodiment of the present invention is an organic light emitting display device.

The present invention described above is not limited by the above-described embodiments and the accompanying drawings, and it is in the technical field to which the present invention belongs that various substitutions, modifications, and changes are possible within the scope without departing from the technical details of the present invention. It will be clear to those skilled in the art. Therefore, the scope of the present invention is indicated by the claims to be described later, and all changes or modifications derived from the meaning, scope and equivalent concepts of the claims should be construed as being included in the scope of the present invention.

110: base board
111: first light blocking layer 112: second light blocking layer
121: first buffer layer 122: second buffer layer
130: first active layer 230: second active layer
141: first gate insulating film 142: second gate insulating film
150: first gate electrode 250: second gate electrode
161: source electrode 262: drain electrode
710: display element 711: first electrode
712: organic light emitting layer 713: second electrode
TFT1: first thin film transistor TFT2: second thin film transistor

Claims (19)

A first thin film transistor and a second thin film transistor on a base substrate,
The first thin film transistor,
a first active layer on the base substrate; and
Including; a first gate electrode spaced apart from the first active layer,
The second thin film transistor,
a second active layer on the base substrate;
a second gate electrode spaced apart from the second active layer; and
An auxiliary gate electrode between the second active layer and the second gate electrode;
The first active layer and the second active layer are integrally formed and connected to each other;
The auxiliary gate electrode is formed integrally with the first gate electrode and is spaced apart from the second active layer and the second gate electrode;
The second gate electrode at least partially overlaps the auxiliary gate electrode, the thin film transistor substrate. According to claim 1,
The thin film transistor substrate, wherein the same voltage as that of the first gate electrode is applied to the auxiliary gate electrode. According to claim 1,
The thin film transistor substrate configured to turn on the first thin film transistor when the second thin film transistor is turned on. According to claim 1,
The thin film transistor substrate configured to apply a first gate voltage to the first gate electrode when a second gate voltage is applied to the second gate electrode. According to claim 1,
The second active layer,
channel unit;
a first connection part contacting one side of the channel part; and
A second connection part contacting the other side of the channel part; includes,
A portion of the channel portion overlaps the auxiliary gate electrode, and another portion of the channel portion does not overlap the auxiliary gate electrode. According to claim 5,
The thin film transistor substrate of claim 1 , wherein the other portion of the channel portion that does not overlap with the auxiliary gate electrode overlaps with the second gate electrode. According to claim 5,
A portion of the channel portion toward the first connection portion overlaps the auxiliary gate electrode and does not overlap the second gate electrode. According to claim 5,
A portion of the channel portion toward the second connection portion overlaps the auxiliary gate electrode and does not overlap the second gate electrode. According to claim 1,
The first active layer and the second active layer may include IGZO (InGaZnO)-based oxide semiconductor material, IZO (InZnO)-based oxide semiconductor material, IGZTO (InGaZnSnO)-based oxide semiconductor material, ITZO (InSnZnO)-based oxide semiconductor material, FIZO (FeInZnO)-based oxide semiconductor material, ZnO-based oxide semiconductor material, SIZO (SiInZnO)-based oxide semiconductor material, ZnON (Zn-Oxynitride)-based oxide semiconductor material, GZO (GaZnO)-based oxide semiconductor material, IGO (InGaO)-based oxide semiconductor A thin film transistor substrate comprising at least one of a material and a GZTO (GaZnSnO)-based oxide semiconductor material. According to claim 1,
The first active layer and the second active layer, respectively,
a first oxide semiconductor layer; and
A second oxide semiconductor layer on the first oxide semiconductor layer; including,
thin film transistor substrate. According to claim 1,
a first light blocking layer on the base substrate; and
A second light blocking layer on the first light blocking layer;
The first light blocking layer and the second light blocking layer are spaced apart from each other and overlap,
one of the first light blocking layer and the second light blocking layer is connected to the second active layer;
The thin film transistor substrate of claim 1 , wherein another one of the first light blocking layer and the second light blocking layer is connected to the second gate electrode. According to claim 11,
The thin film transistor of claim 1 , wherein the first light blocking layer and the second light blocking layer form a capacitor. A display device comprising the thin film transistor substrate of any one of claims 1 to 12. According to claim 13,
The first thin film transistor is a light emitting control transistor,
The second thin film transistor is a driving transistor, the display device. According to claim 13,
A light emitting control signal is applied to the first gate electrode and the auxiliary gate electrode. According to claim 13,
The first gate electrode and the auxiliary gate electrode are part of an emission control line. According to claim 13,
A storage capacitor is formed by overlapping the first light blocking layer and the second light blocking layer. According to claim 13,
Including a driving transistor, a light emission control transistor and a switching transistor,
An active layer of the driving transistor and an active layer of the light emitting transistor are integrally formed,
An active layer of the driving transistor and an active layer of the light emitting transistor are separated from an active layer of the switching transistor. According to claim 18,
Further comprising a sensing transistor,
The active layer of the sensing transistor is integrally formed with the active layer of the driving transistor and the active layer of the light emitting transistor;
The active layer of the sensing transistor is separated from the active layer of the switching transistor, the display device.

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