KR20230034838A - Thin film transistor substrate and display apparatus comprising the same - Google Patents

Abstract

In accordance with one embodiment of the present invention, provided are a thin film transistor substrate and a display device including the same. The thin film transistor substrate includes a thin film transistor on a base substrate and a capacitor connected to the thin film transistor, the thin film transistor includes an active layer and a gate electrode on the base substrate, the capacitor includes a first capacitor electrode disposed on the same layer as the active layer and a second capacitor electrode disposed on the same layer as the gate electrode and overlapped with the first capacitor electrode, the first capacitor electrode includes an active material layer made of the same material as the active layer and a metal-containing layer disposed on the active material layer and containing metal, and the metal-containing layer includes a different type of metal from the active material layer. Therefore, the present invention is capable of improving the driving stability of a capacitor and a thin film transistor.

Description

Thin film transistor substrate and display device including the same {THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY APPARATUS COMPRISING THE SAME}

One embodiment of the present invention relates to a thin film transistor substrate and a display device including the same.

Since a thin film transistor can be manufactured on a glass substrate or a plastic substrate, a switching element or driving element of a display device such as a liquid crystal display device or an organic light emitting device. is widely used as

Based on the material constituting the active layer, the thin film transistor is an amorphous silicon thin film transistor in which amorphous silicon is used as an active layer, a polycrystalline silicon thin film transistor in which polycrystalline silicon is used as an active layer, and an oxide semiconductor used as an active layer. It can be classified as an oxide semiconductor thin film transistor.

Among them, an oxide semiconductor thin film transistor (TFT) has high mobility and can have a large resistance change according to the content of oxygen, so it has the advantage of easily obtaining desired physical properties. In addition, since the oxide constituting the active layer can be formed at a relatively low temperature during the manufacturing process of the oxide semiconductor thin film transistor, the manufacturing cost is low. Oxide semiconductors are transparent due to the nature of oxides, and thus are advantageous for realizing transparent displays. However, oxide semiconductor thin film transistors have disadvantages in that stability and electron mobility are lower than those of polycrystalline silicon thin film transistors.

Recently, as high-quality and high-resolution display devices have been developed, it is necessary for thin film transistors and storage capacitors (Cst) disposed in the display devices to have excellent stability. A method for making the thin film transistor and the storage capacitor (Cst) have excellent stability, for example, a method for making the oxide semiconductor layer included in the thin film transistor and the storage capacitor (Cst) have excellent resistance to hydrogen (H) there is

One embodiment of the present invention is to provide a method for improving the stability of a capacitor and a thin film transistor.

One embodiment of the present invention is to provide a capacitor and a thin film transistor having excellent stability.

One embodiment of the present invention, in particular, to provide a capacitor and a thin film transistor having excellent resistance to hydrogen (H).

One embodiment of the present invention is to provide a thin film transistor substrate including a capacitor and a thin film transistor having excellent stability.

One embodiment of the present invention is to provide a display device including the thin film transistor substrate.

An embodiment of the present invention for achieving the above-mentioned technical problem includes a thin film transistor on a base substrate and a capacitor connected to the thin film transistor, wherein the thin film transistor is spaced apart from the active layer on the base substrate and the active layer to and a gate electrode overlapping at least part of an active layer, wherein the capacitor includes a first capacitor electrode disposed on the same layer as the active layer and a second capacitor disposed on the same layer as the gate electrode and overlapping the first capacitor electrode. an electrode, wherein the first capacitor electrode includes an active material layer made of the same material as the active layer and a metal-containing layer disposed on the active material layer and containing a metal, wherein the metal-containing layer comprises the active material layer It provides a thin film transistor substrate comprising a different type of metal.

The second capacitor electrode may be made of the same material as the gate electrode.

The active layer may be connected to any one of the first capacitor electrode and the second capacitor electrode.

The active layer may be connected to the first capacitor electrode, and the gate electrode may be connected to the second capacitor electrode.

The active layer may be connected to the second capacitor electrode.

The capacitor may further include a third capacitor electrode disposed between the base substrate and the first capacitor electrode.

The thin film transistor substrate may further include a light blocking layer disposed between the base substrate and the active layer, and the light blocking layer may be made of the same material as the third capacitor electrode.

The metal-containing layer may include a metal layer on the active material layer and a metal oxide layer on the metal layer.

Each of the active layer and the active material layer may include an oxide semiconductor material.

The active layer and the active material layer may include a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer.

The metal-containing layer includes titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), rubidium (Rb), cesium (Cs), magnesium (Mg), It may include at least one selected from calcium (Ca), strontium (Sr), lanthanum (La), and palladium (Pd).

The active layer includes a channel portion, a first connection portion connected to one side of the channel portion, and a second connection portion connected to the other side of the channel portion, and a reducing material layer is disposed on the first connection portion and the second connection portion, wherein the The reducing material layer may have the same composition as the metal-containing layer.

The reducible material layer on the second connection part may be integrally formed with the metal-containing layer.

The active layer may be integrally formed with the active material layer of the first capacitor electrode.

The active layer may include a channel portion, a first connection portion connected to one side of the channel portion, and a second connection portion connected to the other side of the channel portion, and the first connection portion and the second connection portion may have a composition different from that of the active material layer. there is.

The first connection part and the second connection part may include a dopant for ion doping.

The gate electrode may be integrally formed with the second capacitor electrode.

Another embodiment of the present invention provides a display device including the thin film transistor substrate.

The thin film transistor may be a driving transistor.

The thin film transistor may be a switching transistor.

The on capacitor may be a storage capacitor formed between the gate electrode of the thin film transistor and an active layer of the thin film transistor.

In one embodiment of the present invention, the capacitor electrode and the active layer are protected by the metal-containing layer, so that the capacitor and the thin film transistor can have excellent stability.

According to an embodiment of the present invention, since the oxide semiconductor layer is protected by the metal-containing layer, stability of a capacitor including a capacitor electrode including the oxide semiconductor layer and the metal-containing layer may be improved.

In addition, according to an embodiment of the present invention, a thin film transistor including an oxide semiconductor layer as an active layer may have excellent stability because a portion of the oxide semiconductor layer is protected by the metal-containing layer.

According to an embodiment of the present invention, the metal-containing layer containing a metal oxide serves to trap or block hydrogen, so that driving characteristics of capacitors and thin film transistors do not vary, so that driving stability of capacitors and thin film transistors can be improved. there is.

As described above, a display device including a hydrogen-stable capacitor and a thin film transistor can have excellent stability without a change in display quality.

In addition to the effects mentioned above, other features and advantages of the present invention will be described below, or will be clearly understood by those skilled in the art from such description and description.

1A is a plan view of a thin film transistor substrate according to an embodiment of the present invention.
Figure 1b is a cross-sectional view taken along II' of Figure 1a.
2a and 2b are cross-sectional views of a thin film transistor substrate according to another exemplary embodiment of the present invention.
3 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
4 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
5 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
6 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
7 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
8 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
9A is a plan view of a thin film transistor substrate according to another exemplary embodiment of the present invention.
FIG. 9B is a cross-sectional view taken along line II-II' of FIG. 9A.
10 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
11 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
12 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
13 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
14a to 14i are manufacturing process diagrams of a thin film transistor substrate according to another embodiment of the present invention.
15 is a schematic diagram of a display device according to another exemplary embodiment of the present invention.
FIG. 16 is a circuit diagram of one pixel of FIG. 15 .
FIG. 17 is a plan view of the pixel of FIG. 16 .
FIG. 18 is a cross-sectional view taken along line III-III' of FIG. 17 .
19 is a circuit diagram of one pixel of a display device according to another exemplary embodiment of the present invention.
20 is a circuit diagram of one pixel of a display device according to another exemplary embodiment of the present invention.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various forms different from each other, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to inform those who have the scope of the invention. The invention is only defined by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, the present invention is not limited to those shown in the drawings. Like elements may be referred to by like reference numerals throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

When "includes", "has", "consists of", etc. mentioned in this specification is used, other parts may be added unless the expression "only" is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

For example, when the positional relationship of two parts is described as "on", "upper", "below", "beside", etc., the expression "immediately" or "directly" is used. Unless otherwise specified, one or more other parts may be located between the two parts.

The spatially relative terms "below, beneath", "lower", "above", "upper", etc., refer to one element or component as shown in the drawing. It can be used to easily describe the correlation between and other elements or components. Spatially relative terms should be understood as terms that include different orientations of elements in use or operation in addition to the directions shown in the figures. For example, when flipping elements shown in the figures, elements described as “below” or “beneath” other elements may be placed “above” the other elements. Thus, the exemplary term “below” may include directions of both below and above. Likewise, the exemplary terms "above" or "above" can include both directions of up and down.

In the case of a description of a temporal relationship, for example, "immediately" or "directly" when a temporal precedence relationship is described, such as "after", "following", "after", "before", etc. Unless the expression is used, non-continuous cases may also be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, "at least one of the first item, the second item, and the third item" means not only the first item, the second item, or the third item, respectively, but also two of the first item, the second item, and the third item. It may mean a combination of all items that can be presented from one or more.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship. may be

In adding reference numerals to components of each drawing describing the embodiments of the present invention, the same components may have the same numerals as much as possible even though they are displayed on different drawings.

In the embodiments of the present invention, the source electrode and the drain electrode are only distinguished for convenience of description, and the source electrode and the drain electrode may be interchanged. The source electrode may serve as the drain electrode, and the drain electrode may serve as the source electrode. Also, a source electrode of one embodiment may be a drain electrode in another embodiment, and a drain electrode of one embodiment may be a source electrode in another embodiment.

In some embodiments of the present invention, a source connection part and a source electrode are distinguished and a drain connection part and a drain electrode are distinguished for convenience of explanation, but the embodiments of the present invention are not limited thereto. The source connection part may be a source electrode, and the drain connection part may be a drain electrode. Also, the source connection part may be the drain electrode, and the drain region may be the source electrode.

1A is a plan view of a thin film transistor substrate 100 according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line II' of FIG. 1A.

The thin film transistor substrate 100 according to an embodiment of the present invention includes a thin film transistor (TFT) on the base substrate 110 and a capacitor (Cap) connected to the thin film transistor (TFT).

Glass or plastic may be used as the base substrate 110 . As the plastic, a transparent plastic having a flexible property, such as polyimide, may be used. When polyimide is used as the base substrate 110, considering that a high-temperature deposition process is performed on the base substrate 110, heat-resistant polyimide that can withstand high temperatures may be used.

Light blocking layers 115 and 116 may be disposed on the base substrate 110 .

The light blocking layers 115 and 116 may block light incident from the outside to protect the thin film transistor (TFT).

The light blocking layers 115 and 116 may be made of a material having light blocking properties. The light blocking layers 115 and 116 may include an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), or neodymium (Nd). ), at least one of titanium (Ti) and iron (Fe). According to one embodiment of the present invention, the light blocking layers 115 and 116 may have electrical conductivity.

The light blocking layers 115 and 116 may be electrically connected to any one of the source electrode 161 and the drain electrode 162 of the thin film transistor (TFT). Also, the light blocking layers 115 and 116 may be electrically connected to the gate electrode 150 .

Referring to FIGS. 1A and 1B , the light blocking layer 115 under the thin film transistor TFT may be connected to the source electrode 161 of the thin film transistor TFT. The light blocking layer 116 disposed on the side of the capacitor Cap may be one electrode of the capacitor Cap. Referring to FIG. 1B , the light blocking layer 116 disposed on the side of the capacitor Cap may serve as the third capacitor electrode CE3.

A buffer layer 120 is disposed on the light blocking layers 115 and 116 . The buffer layer 120 may be made of an insulating material. For example, the buffer layer 120 may include at least one of insulating materials such as silicon oxide, silicon nitride, and metal-based oxide. The buffer layer 120 may have a single film structure or a multi-layer structure.

The buffer layer 120 may protect the active layer 130 by blocking air and moisture. In addition, the upper surface of the base substrate 110 on which the light blocking layers 115 and 116 are disposed can be made uniform by the buffer layer 120 .

Referring to FIG. 1B , a thin film transistor (TFT) may be disposed on the buffer layer 120 . According to an embodiment of the present invention, the thin film transistor (TFT) includes an active layer 130 on a base substrate 110 and a gate electrode 150 that is spaced apart from the active layer 130 and at least partially overlaps the active layer 130. includes

Referring to FIG. 1B , the active layer 130 of the thin film transistor (TFT) may be disposed on the buffer layer 120 .

According to an embodiment of the present invention, the active layer 130 may be formed of a semiconductor material. The active layer 130 may include, for example, an oxide semiconductor material.

Oxide semiconductor materials include, for example, IZO (InZnO)-based oxide semiconductor materials, IGO (InGaO)-based oxide semiconductor materials, ITO (InSnO)-based oxide semiconductor materials, IGZO (InGaZnO)-based oxide semiconductor materials, and IGZTO (InGaZnSnO)-based oxide semiconductor materials. Oxide semiconductor material, GZTO (GaZnSnO)-based oxide semiconductor material, GZO (GaZnO)-based oxide semiconductor material, ITZO (InSnZnO)-based oxide semiconductor material, FIZO (FeInZnO)-based oxide semiconductor material, Ge-ITO-based oxide semiconductor material, and Ge- It may include at least one of ITZO-based oxide semiconductor materials. However, one embodiment of the present invention is not limited thereto, and the active layer 130 may be made of other oxide semiconductor materials known in the art.

The active layer 130 may include a channel portion 130n, a first connection portion 130a, and a second connection portion 130b. The first connection part 130a is connected to one side of the channel part 130n, and the second connection part 130b is connected to the other side of the channel part 130n.

The channel portion 130n overlaps the gate electrode 150 .

The first connection portion 130a and the second connection portion 130b may be formed by selectively conducting the active layer 130 made of a semiconductor material. For example, the active layer 130 may be selectively made conductive by doping using the gate electrode 150 as a mask. As a result, the first connection portion 130a and the second connection portion 130b may be formed. Specifically, the active layer 130 may be selectively made conductive by ion doping. As a dopant for ion doping, boron (B), phosphorus (P), fluorine (F), hydrogen (H), or ions thereof may be used.

The first connection portion 130a and the second connection portion 130b have superior electrical conductivity compared to the channel portion 130n. Accordingly, each of the first connection portion 130a and the second connection portion 130b may serve as a wire.

Referring to FIG. 1B , a first capacitor electrode CE1 may be disposed on the buffer layer 120 . The first capacitor electrode CE1 may be disposed on the same layer as the active layer 130 .

The first capacitor electrode CE1 may be electrically connected to the active layer 130 . However, an embodiment of the present invention is not limited thereto, and the first capacitor electrode CE1 may be connected to the gate electrode 150 .

The first capacitor electrode CE1 may include an active material layer 230 and a metal-containing layer 240 .

The active material layer 230 may be made of the same material as the active layer 130 . The active layer 130 and the active material layer 230 may be made of the same oxide semiconductor material. The active layer 130 and the active material layer 230 may be integrally formed.

The metal-containing layer 240 is disposed on the active material layer 230 and includes a metal. A metal included in the metal-containing layer 240 may be different from a metal included in the active material layer 230 . According to an embodiment of the present invention, the metal-containing layer 240 may include a different type of metal from that of the active material layer 230 .

The metal-containing layer 240 may include a metal having excellent reactivity with hydrogen (H). A metal included in the metal-containing layer 240 may have reducibility. Specifically, while the metal included in the metal-containing layer 240 is oxidized, other layers or other elements may be reduced.

According to an embodiment of the present invention, the metal-containing layer 240 is a metal, titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), At least one selected from rubidium (Rb), cesium (Cs), magnesium (Mg), calcium (Ca), strontium (Sr), lanthanum (La), and palladium (Pd) may be included.

In the metal-containing layer 240, the metal may be oxidized and exist in a metal oxide state or may be non-oxidized and exist in a metal element state.

The metal-containing layer 240 may include, for example, titanium (Ti) as a metal. It is known that titanium (Ti) reacts more easily with hydrogen when it is in an oxidized state of titanium oxide (TiOx, 0<x≤2) than when it is in an unoxidized titanium (Ti) atomic state. The reaction energy relationship between titanium (Ti) and titanium oxide (TiOx) and hydrogen is shown in Table 1, for example.

reaction formula Formation Energy (eV) TiH ₂ -0.584 TiH -0.438 Ti ₆ H ₂ O ₁₃ -3.188 Ti ₃ H ₂ O ₇ -2.954

In Table 1, "formation energy" means Gibb's free energy.

Referring to Table 1, it can be seen that titanium (Ti) has a lower reaction energy with hydrogen when it is in the titanium oxide (TiOx) state than when it is in the monoatomic state, and as a result, it can easily react with hydrogen. there is.

According to an embodiment of the present invention, the metal-containing layer 240 may include a metal oxide and may easily react with hydrogen (H). As a result, the metal-containing layer 240 can collect hydrogen (H) and prevent the hydrogen (H) from having an unnecessary effect on the active layer 130 of the thin film transistor (TFT). According to an embodiment of the present invention, the metal-containing layer 240 may serve as a hydrogen (H) trapping layer or a hydrogen (H) absorbing layer to protect the active layer 130 of the thin film transistor (TFT). More specifically, the metal-containing layer 240 may protect the channel portion 130n of the active layer 130 .

According to an embodiment of the present invention, the metal-containing layer 240 includes metal oxide but may have electrical conductivity. Therefore, the metal-containing layer 240 may serve as a conductive material layer.

According to one embodiment of the present invention, the metal-containing layer 240 may have electrical conductivity. For example, the metal-containing layer 240 may have a sheet resistance of 10,000 Ω/□ or less. More specifically, the metal-containing layer 240 may have a sheet resistance of 5,000 Ω/□ or less, may have a sheet resistance of 1500 Ω/□ or less, may have a sheet resistance of 1,300 Ω/□ or less, and may have a sheet resistance of 1050 Ω/□ or less. It may have the following sheet resistance. The metal-containing layer 240 may have, for example, a sheet resistance of 500 to 5,000 Ω/□, a sheet resistance of 1,000 to 5,000 Ω/□, and a sheet resistance of 1,000 to 1,500 Ω/□, It may have a sheet resistance of 1,000 to 1,300 Ω/□, may have a sheet resistance of 950 to 1050 Ω/□, and may have a sheet resistance of 500 to 1,500 Ω/□.

A gate insulating layer 140 is disposed on the active layer 130 and the first capacitor electrode CE1. The gate insulating layer 140 may include at least one of silicon oxide, silicon nitride, and metal-based oxide. The gate insulating film 140 may have a single film structure or a multi-layer structure. The gate insulating layer 140 protects the channel portion 130n.

Referring to FIG. 1B , the gate insulating layer 140 may be integrally formed on the base substrate 110 . For example, the gate insulating layer 140 may cover both the upper portion of the active layer 130 and the first capacitor electrode CE1. However, an embodiment of the present invention is not limited thereto, and the gate insulating film 140 may be patterned (see FIG. 2 ).

The gate electrode 150 is disposed on the gate insulating layer 140 . The gate electrode 150 is spaced apart from the active layer 130 and at least partially overlaps the active layer 130 . At least a portion of the gate electrode 150 overlaps the channel portion 130n of the active layer 130 .

Also, referring to FIG. 1B , a second capacitor electrode CE2 may be disposed on the gate insulating layer 140 . The second capacitor electrode CE2 may be disposed on the same layer as the gate electrode 150 . The second capacitor electrode CE2 may be made of the same material as the gate electrode 150 . The gate electrode 150 and the second capacitor electrode CE2 may be formed together.

The gate electrode 150 and the second capacitor electrode CE2 are each made of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, copper (Cu), or copper. It may include at least one of a copper-based metal such as an alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). . The gate electrode 150 and the second capacitor electrode CE2 may each have a multilayer structure including at least two conductive layers having different physical properties.

The second capacitor electrode CE2 overlaps the first capacitor electrode CE1. A first capacitor C1 may be formed by the first capacitor electrode CE1 and the second capacitor electrode CE2. The first capacitor C1 may constitute a capacitor Cap according to an embodiment of the present invention.

Referring to FIGS. 1A and 1B , the second capacitor electrode CE2 may be connected to the light blocking layer 116 disposed under the first capacitor electrode CE1 through a contact hole. Accordingly, the same voltage as that of the second capacitor electrode CE2 may be applied to the light blocking layer 116 .

The light blocking layer 116 connected to the second capacitor electrode CE2 may serve as the third capacitor electrode CE3. Referring to FIG. 1B , the capacitor Cap may include a third capacitor electrode CE3 disposed between the base substrate 110 and the first capacitor electrode CE1.

The third capacitor electrode CE3 overlaps the first capacitor electrode CE1. A second capacitor C2 may be formed by the first capacitor electrode CE1 and the third capacitor electrode CE3. The second capacitor C2 may constitute a capacitor Cap according to an embodiment of the present invention. According to an embodiment of the present invention, the capacitor Cap may include a first capacitor C1 and a second capacitor C2.

The light blocking layer 115 disposed between the base substrate 110 and the active layer 130 is disposed on the same layer as the third capacitor electrode CE3. The light blocking layer 115 disposed between the base substrate 110 and the active layer 130 may be made of the same material as the third capacitor electrode CE3, and the light blocking layer 115 may be formed of the same material as the third capacitor electrode CE3. can be formed together.

An interlayer insulating layer 170 is disposed on the gate electrode 150 and the second capacitor electrode CE2. The interlayer insulating layer 170 may include at least one of silicon oxide, silicon nitride, and metal-based oxide. The interlayer insulating film 170 may have a single film structure or a multilayer film structure.

A source electrode 161 and a drain electrode 162 may be disposed on the interlayer insulating layer 170 . The source electrode 161 and the drain electrode 162 are spaced apart from each other and connected to the active layer 130 , respectively. The source electrode 161 and the drain electrode 162 may be made of a conductive material.

The source electrode 161 and the drain electrode 162 are only distinguished for convenience and may be interchanged.

Referring to FIG. 1B , the source electrode 161 and the drain electrode 162 are each connected to the active layer 130 through a contact hole. In addition, the source electrode 161 may be connected to the light blocking layer 115 under the active layer 130 through a contact hole. Alternatively, the drain electrode 162 may be connected to the light blocking layer 115 under the active layer 130 through a contact hole, and the gate electrode 150 may be connected to the light blocking layer 115 under the active layer 130. there is.

According to an embodiment of the present invention, the capacitor Cap may be connected to the thin film transistor TFT. Specifically, the active layer 130 of the thin film transistor TFT may be connected to either the first capacitor electrode CE1 or the second capacitor electrode CE2.

1A and 1B, the active layer 130 is connected to the first capacitor electrode CE1. Specifically, the active layer 130 and the first capacitor electrode CE1 may be connected to each other through the drain electrode 162 . However, an embodiment of the present invention is not limited thereto, and the active layer 130 and the first capacitor electrode CE1 may be connected to each other through the source electrode 161 .

Referring to FIG. 1A , the gate electrode 150 may be connected to the second capacitor electrode CE2. Specifically, the gate electrode 150 and the second capacitor electrode CE2 may be connected to each other by the connection electrode 155 .

However, one embodiment of the present invention is not limited thereto. The active layer 130 may be connected to the second capacitor electrode CE2 instead of the first capacitor electrode CE1.

According to an embodiment of the present invention, the capacitor Cap connected to the thin film transistor TFT may serve as a storage capacitor Cst to charge a voltage for controlling light emission of the pixel.

2A and 2B are cross-sectional views of thin film transistor substrates 201 and 202 according to another embodiment of the present invention, respectively. Hereinafter, in order to avoid redundancy, descriptions of components already described are omitted.

Referring to FIG. 2A , the active layer 130 may be connected to the second capacitor electrode CE2 of the capacitor Cap. The active layer 130 and the second capacitor electrode CE2 may be connected to each other by the drain electrode 162 . Referring to FIGS. 1B and 2A , the active layer 130 may be connected to the first capacitor electrode CE1 or the second capacitor electrode CE2 of the capacitor Cap. Also in other embodiments described below, the active layer 130 may be connected to the first capacitor electrode CE1 or the second capacitor electrode CE2.

Referring to FIG. 2B , the gate insulating layer 140 may be patterned. Specifically, the gate insulating layer 140 may be patterned in a shape corresponding to the gate electrode 150 and the second capacitor electrode CE2. In other embodiments described below, the gate insulating layer 140 may also be patterned.

In the process of patterning the gate insulating layer 140 , the active layer 130 may be selectively made into a conductor to form the first connection portion 130a and the second connection portion 130b.

3 is a cross-sectional view of a thin film transistor substrate 300 according to another embodiment of the present invention.

Referring to FIG. 3 , the metal-containing layer 240 may include a metal layer 241 on the active material layer 230 and a metal oxide layer 242 on the metal layer 241 . The metal oxide layer 242 has a higher oxygen concentration than the metal layer 241 .

According to an embodiment of the present invention, a portion of the metal-containing layer 240 made of a metal that is not substantially oxidized or hardly oxidized may be referred to as the metal layer 241 . After the metal-containing layer 240 is formed using metal, the metal layer 241 and the metal oxide layer 242 may be separately formed by heat treatment or oxygen (O ₂ ) plasma treatment on the metal-containing layer 240. there is.

According to an embodiment of the present invention, the metal layer 241 may be made of only metal, but may also contain a small amount of oxygen. A portion of the metal-containing layer 240 having an oxygen concentration of 10 atoms (at%) or less relative to the total number of atoms may be referred to as the metal layer 241 . Alternatively, the metal layer 241 may have an oxygen concentration of 5 atoms (at%) or less.

The metal layer 241 may have reducibility. The metal layer 241 may reduce the active material layer 230 . As a result, the active material layer 230 is reduced, so that the active material layer 230 may have electrical conductivity close to that of a conductor.

The metal oxide layer 242 can easily react with hydrogen. As a result, the metal oxide layer 242 may serve as a hydrogen scavenging layer or a hydrogen blocking layer. The metal oxide layer 242 may prevent hydrogen (H) from unnecessarily affecting the active layer 130 of the thin film transistor (TFT).

4 is a cross-sectional view of a thin film transistor substrate 400 according to another embodiment of the present invention.

Referring to FIG. 4 , the active layer 130 of the thin film transistor (TFT) may include a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 on the first oxide semiconductor layer 131 .

Also, referring to FIG. 4 , the active material layer 230 of the first capacitor electrode CE1 also includes the first oxide semiconductor layer 231 and the second oxide semiconductor layer 232 on the first oxide semiconductor layer 231 . can include

According to another embodiment of the present invention, the active layer 130 and the active material layer 230 may be made together by the same process using the same material. Therefore, the first oxide semiconductor layer 131 of the active layer 130 and the first oxide semiconductor layer 231 of the active material layer 230 may have the same composition. Also, the second oxide semiconductor layer 132 of the active layer 130 and the second oxide semiconductor layer 232 of the active material layer 230 may have the same composition.

The first oxide semiconductor layers 131 and 231 and the second oxide semiconductor layers 132 and 232 may include the same semiconductor material or different semiconductor materials.

The first oxide semiconductor layers 131 and 231 support the second oxide semiconductor layers 132 and 232 . Therefore, the first oxide semiconductor layers 131 and 231 are also referred to as "supporting layers".

A structure in which the active layer 130 and the active material layer 230 are composed of two layers is also referred to as a bi-layer structure. However, another embodiment of the present invention is not limited thereto, and the active layer 130 and the active material layer 230 may further include a third oxide semiconductor layer.

The stacked structure of the active layer 130 and the active material layer 230 shown in FIG. 4 may also be applied to other thin film transistors described herein.

5 is a cross-sectional view of a thin film transistor substrate 500 according to another embodiment of the present invention.

Referring to FIG. 5 , reducible material layers 135 and 136 may be disposed on the first connection portion 130a and the second connection portion 130b. The reducing material layers 135 and 136 may have the same composition as the metal-containing layer 240 . The reducible material layers 135 and 136 may be made of the same material as the metal-containing layer 240 through the same process. Accordingly, the reducing material layers 135 and 136 and the metal-containing layer 240 may be made of the same material and may have the same material composition.

Referring to FIG. 5 , a first reducing material layer 135 may be disposed on the first connection part 130a and a second reducing material layer 136 may be disposed on the second connection part 130b.

Like the metal-containing layer 240, the reducible material layers 135 and 136 include titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), rubidium ( Rb), cesium (Cs), magnesium (Mg), calcium (Ca), strontium (Sr), lanthanum (La), and palladium (Pd).

The reducible material layers 135 and 136 may include a metal oxide and may easily react with hydrogen (H). As a result, the reducible material layers 135 and 136 can prevent hydrogen (H) from having an unnecessary effect on the channel portion 130n of the active layer 130 .

In addition, the active layer 130 may be selectively conducted by the reducible material layers 135 and 136 . According to an embodiment of the present invention, regions of the active layer 130 contacting the reducible material layers 135 and 136 may be conductive to form the first connection portion 130a and the second connection portion 130b, respectively. there is.

Specifically, portions of the active layer 130 in contact with the reducing material layers 135 and 136 may be reduced to form the first connection portion 130a and the second connection portion 130b.

6 is a cross-sectional view of a thin film transistor substrate 600 according to another embodiment of the present invention.

Referring to FIG. 6 , the gate insulating layer 140 may be patterned. Specifically, the gate insulating layer 140 may be patterned in a shape corresponding to the gate electrode 150 and the second capacitor electrode CE2.

Referring to FIG. 6 , the active layer 130 may be connected to the first capacitor electrode CE1 of the capacitor Cap. The active layer 130 and the first capacitor electrode CE1 may be connected to each other by the drain electrode 162 . However, another embodiment of the present invention is not limited thereto, and the active layer 130 may be connected to the second capacitor electrode CE2.

7 is a cross-sectional view of a thin film transistor substrate 700 according to another embodiment of the present invention.

Referring to FIG. 7 , the reducible material layers 135 and 136 may include metal layers 135a and 136a and metal oxide layers 135b and 136b on the metal layers 135a and 136a.

The metal oxide layers 135b and 136b have a higher oxygen concentration than the metal layers 135a and 136a. The metal layers 135a and 136a may have reducibility. The metal layers 135a and 136a may reduce the active layer 130 . As a result, the active layer 230 is reduced, and the active layer 130 can be selectively made into a conductor.

According to another embodiment of the present invention, a region of the active layer 130 in contact with the metal layers 135a and 136a may be conductive to form the first connection portion 130a and the second connection portion 130b. .

The metal-containing layer 240 may include a metal layer 241 on the active material layer 230 and a metal oxide layer 242 on the metal layer 241 . The metal oxide layer 242 has a higher oxygen concentration than the metal layer 241 .

The reducing material layers 135 and 136 and the metal-containing layer 240 may be made together by the same method using the same material.

8 is a cross-sectional view of a thin film transistor substrate 800 according to another embodiment of the present invention.

Referring to FIG. 8 , the active layer 130 of the thin film transistor (TFT) may include a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 on the first oxide semiconductor layer 131 . Reducible material layers 135 and 136 may be disposed on the second oxide semiconductor layer 132 .

Referring to FIG. 8 , the active material layer 230 of the first capacitor electrode CE1 may also include a first oxide semiconductor layer 231 and a second oxide semiconductor layer 232 on the first oxide semiconductor layer 231 . can

9A is a plan view of a thin film transistor substrate 900 according to another embodiment of the present invention, and FIG. 9B is a cross-sectional view taken along line II-II′ of FIG. 9A.

Referring to FIGS. 9A and 9B , the active layer 130 of the thin film transistor TFT may be integrally formed with the active material layer 230 of the first capacitor electrode CE1 . According to another embodiment of the present invention, the active layer 130 of the thin film transistor TFT and the active material layer 230 of the first capacitor electrode CE1 may be formed in one pattern.

A region of the active layer 130 and the active material layer 230 excluding the channel portion 130n may be conductive. As a result, the active layer 130 and the active material layer 230 can be electrically connected without a separate connection wire.

Referring to FIGS. 9A and 9B , the metal-containing layer 240 may be disposed only on the upper portion of the active material layer 230 of the first capacitor electrode CE1 .

Also, referring to FIG. 9A , the gate electrode 150 may be integrally formed with the second capacitor electrode CE2. According to another embodiment of the present invention, the gate electrode 150 of the thin film transistor TFT and the second capacitor electrode CE2 may be formed in one pattern. As a result, the gate electrode 150 may be connected to the second capacitor electrode CE2 without the connection electrode 155 .

Referring to FIGS. 9A and 9B , the light blocking layer 116 may be integrally formed under the thin film transistor (TFT) and under the capacitor (Cap). One light blocking layer 116 may be disposed under the thin film transistor (TFT) and under the capacitor (Cap).

The light blocking layer 116 may be connected to the second capacitor electrode CE2. As a result, the light blocking layer 6 may be electrically connected to the gate electrode 150 .

A portion of the light blocking layer 116 disposed below the capacitor Cap may serve as the third capacitor electrode CE3. The same voltage as that of the second capacitor electrode CE2 may be applied to the third capacitor electrode CE3.

According to another embodiment of the present invention, the first connection portion 130a and the second connection portion 130b may be made conductive by ion doping using a dopant. As a dopant for ion doping, boron (B), phosphorus (P), fluorine (F), hydrogen (H), or ions thereof may be used. Accordingly, the first connection portion 130a and the second connection portion 130b may include a dopant for ion doping. On the other hand, since the active material layer 230 is shielded by the metal-containing layer 240, it may not include a dopant used for ion doping. As such, even if formed by the active layer 130 and the active material layer 230, as a result of ion doping, the first connection portion 130a and the second connection portion 130b and the active material layer 230 have different compositions. can

10 is a cross-sectional view of a thin film transistor substrate 1000 according to another embodiment of the present invention.

Referring to FIG. 10 , the gate insulating layer 140 may be patterned. Specifically, the gate insulating layer 140 may be patterned in a shape corresponding to the gate electrode 150 and the second capacitor electrode CE2.

In the process of patterning the gate insulating layer 140 , the active layer 130 may be selectively made into a conductor to form the first connection portion 130a and the second connection portion 130b.

Referring to FIG. 10 , the active layer 130 and the active material layer 230 may be integrally formed.

11 is a cross-sectional view of a thin film transistor substrate 1100 according to another embodiment of the present invention.

Referring to FIG. 11 , reducible material layers 135 and 136 are disposed on the first connection part 130a and the second connection part 130b of the thin film transistor TFT, and the active material layer of the first capacitor electrode CE1. A metal containing layer 240 may be disposed on 230 .

The reducible material layers 135 and 136 may be made of the same material as the metal-containing layer 240 through the same process.

The reducible material layer 136 on the second connection portion 130b may be integrally formed with the metal-containing layer 240 . The reducible material layer 136 may be extended to become the metal-containing layer 240 . Alternatively, a portion of the metal-containing layer 240 may become the reducible material layer 136 on the second connection portion 130b.

12 is a cross-sectional view of a thin film transistor substrate 1200 according to another embodiment of the present invention.

Referring to FIG. 12 , the active layer 130 of the thin film transistor (TFT) may include a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 on the first oxide semiconductor layer 131 . In addition, the active material layer 230 of the first capacitor electrode CE1 may also include a first oxide semiconductor layer 231 and a second oxide semiconductor layer 232 on the first oxide semiconductor layer 231 .

Referring to FIG. 12 , the first oxide semiconductor layer 131 of the active layer 130 and the first oxide semiconductor layer 231 of the active material layer 230 may be integrally formed. In addition, the second oxide semiconductor layer 132 of the active layer 130 and the second oxide semiconductor layer 232 of the active material layer 230 may be integrally formed.

13 is a cross-sectional view of a thin film transistor substrate 1300 according to another embodiment of the present invention.

Referring to FIG. 13 , the reducible material layers 135 and 136 may include metal layers 135a and 136a and metal oxide layers 135b and 136b on the metal layers 135a and 136a.

The metal-containing layer 240 may also include a metal layer 241 and a metal oxide layer 242 on the metal layer 241 .

The reducing material layers 135 and 136 and the metal-containing layer 240 may be made together by the same method using the same material.

The metal layer 136a and the metal oxide layer 136b constituting the reducible material layer 136 on the second connection portion 130b are the metal layer 241 and the metal oxide layer 242 constituting the metal-containing layer 240, respectively. can be made integrally.

Hereinafter, a method of manufacturing a thin film transistor substrate 300 according to another embodiment of the present invention will be described with reference to FIGS. 14A to 14I.

14a to 14i are manufacturing process diagrams of the thin film transistor substrate 300 according to another embodiment of the present invention.

Referring to FIG. 14A , light blocking layers 115 and 116 are formed on a base substrate 110 , and a buffer layer 120 is formed on the light blocking layers 115 and 116 .

Referring to FIG. 14B , an oxide semiconductor material layer 130m and a metal material layer 240m are formed on the buffer layer 120 .

Referring to FIG. 14C , photo resistor patterns 271 and 272 are formed on the metal material layer 240m. By exposure using a half phone mask, a first photoresist pattern 271 and a second photoresist pattern 272 having different thicknesses may be formed.

Referring to FIG. 14D , the active layer 130 of the thin film transistor TFT and the first capacitor electrode CE1 of the capacitor Cap are formed by etching using the photoresistor patterns 271 and 272 .

Under the first photoresistor pattern 271 having a small thickness, the metal material layer 240m is removed to form the active layer 130 .

The oxide semiconductor material layer 130m and the metal material layer 240m are not removed under the second photoresistor pattern 272 having a large thickness, so that the first capacitor electrode CE1 is formed. The active material layer 230 is formed by the oxide semiconductor material layer 130m, and the metal-containing layer 240 is formed by the metal material layer 240m.

Referring to FIG. 14E, heat treatment is performed. Heat may be performed on the entire upper portion of the base substrate 110 . An upper portion of the metal-containing layer 240 may be oxidized by heat treatment. Heat treatment may be performed at a temperature of, for example, 100 to 500 °C. More specifically, the heat treatment may be performed at a temperature of 100 to 400 ° C, 200 to 500 ° C, 100 to 300 ° C, or 200 to 300 ° C. .

Referring to FIG. 14F , the metal-containing layer 240 may be separated into a metal layer 241 and a metal oxide layer 242 by heat treatment. The metal oxide layer 242 has a higher oxygen concentration than the metal layer 241 .

However, another embodiment of the present invention is not limited thereto, and the upper portion of the metal-containing layer 240 may be oxidized by plasma treatment. For example, by oxygen (O ₂ ) plasma treatment, the metal-containing layer 240, the metal layer 241, and the metal oxide layer 242 may be separately formed.

Referring to FIG. 14G , the gate insulating layer 140 is formed on the active layer 130 and the first capacitor electrode CE1, and the gate electrode 150 and the second capacitor electrode CE2 are formed on the gate insulating layer 140. can be formed. The gate electrode 150 and the second capacitor electrode CE2 may be formed together.

In addition, the second capacitor electrode CE2 and the light blocking layer 116 disposed below the first capacitor electrode CE1 may be connected to each other through the contact hole. The light blocking layer 116 connected to the second capacitor electrode CE2 may serve as the third capacitor electrode CE3.

As a result, the first capacitor C1 is formed by overlapping the first capacitor electrode CE1 and the second capacitor electrode CE2, and the overlapping of the first capacitor electrode CE1 and the third capacitor electrode CE3 As a result, the second capacitor C2 may be formed. According to an embodiment of the present invention, the capacitor Cap may include a first capacitor C1 and a second capacitor C2.

Also, referring to FIG. 14G , the active layer 130 may be selectively made conductive by doping using the gate electrode 150 as a mask. Specifically, the active layer 130 may be selectively made conductive by ion doping. As a dopant for ion doping, boron (B), phosphorus (P), fluorine (F), hydrogen (H), or ions thereof may be used.

As a result, as shown in FIG. 14H , a first connection portion 130a and a second connection portion 130b may be formed.

Referring to FIG. 14I , an interlayer insulating film 170 is formed on the gate electrode 150 and the second capacitor electrode CE2, and a source electrode 161 and a drain electrode 162 are formed on the interlayer insulating film 170. do.

Referring to FIG. 14I , the source electrode 161 and the drain electrode 162 are each connected to the active layer 130 through a contact hole. In addition, the source electrode 161 may be connected to the light blocking layer 115 under the active layer 130 through a contact hole.

In addition, the active layer 130 and the first capacitor electrode CE1 may be connected to each other through the drain electrode 162 .

As a result, according to another embodiment of the present invention, a thin film transistor substrate 300 including a thin film transistor (TFT) and a capacitor (Cap) may be formed.

Hereinafter, display devices to which the above-described thin film transistor substrates 100, 201, 202, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, and 1300 are applied will be described in detail.

15 is a schematic diagram of a display device 1400 according to another embodiment of the present invention.

The display device 1400 according to another embodiment of the present invention may include a display panel 310, a gate driver 320, a data driver 330, and a control unit 340.

Gate lines GL and data lines DL are disposed on the display panel 310 , and pixels P are disposed at intersections of the gate lines GL and data lines DL. An image is displayed by driving the pixel P.

The controller 340 controls the gate driver 320 and the data driver 330 .

The controller 340 generates a gate control signal (GCS) for controlling the gate driver 320 and a data control signal (DCS) for controlling the data driver 330 by using a signal supplied from an external system (not shown). outputs In addition, the controller 340 samples input image data input from an external system, rearranges them, and supplies the rearranged digital image data RGB to the data driver 330 .

The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. Also, the gate control signal GCS may include control signals for controlling the shift register.

The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

The data driver 330 supplies data voltages to the data lines DL of the display panel 310 . Specifically, the data driver 330 converts the image data RGB input from the controller 340 into an analog data voltage and supplies the data voltage to the data lines DL.

The gate driver 320 may include a shift register 350 .

The shift register 350 sequentially supplies gate pulses to the gate lines GL for one frame using the start signal and the gate clock transmitted from the controller 340 . Here, one frame refers to a period during which one image is output through the display panel 310 . The gate pulse has a turn-on voltage capable of turning on a switching element (thin film transistor) disposed in the pixel P.

In addition, the shift register 350 supplies a gate-off signal capable of turning off the switching element to the gate line GL during the remaining period in which the gate pulse is not supplied during one frame. Hereinafter, the gate pulse and the gate off signal are generically referred to as a scan signal (SS or Scan).

According to an embodiment of the present invention, the gate driver 320 may be mounted on the display panel 310 . As such, a structure in which the gate driver 320 is directly mounted on the display panel 310 is referred to as a gate in panel (GIP) structure.

FIG. 16 is a circuit diagram of one pixel P of FIG. 15 , FIG. 17 is a plan view of the pixel P of FIG. 16 , and FIG. 18 is a cross-sectional view taken along line III-III′ of FIG. 17 .

The circuit diagram of FIG. 16 is an equivalent circuit diagram of the pixel P of the display device 1400 including an organic light emitting diode (OLED) as the display element 710 .

The pixel P includes a display element 710 and a pixel driver PDC that drives the display element 710 .

The pixel driver PDC of FIG. 16 includes a first thin film transistor TR1 as a switching transistor and a second thin film transistor TR2 as a driving transistor.

The first thin film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS supplied through the gate line GL.

The data line DL provides the data voltage Vdata to the pixel driver PDC, and the first thin film transistor TR1 controls application of the data voltage Vdata.

The driving power line PL provides a driving voltage Vdd to the display element 710, and the second thin film transistor TR2 controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving the organic light emitting diode (OLED) as the display element 710 .

When the first thin film transistor TR1 is turned on by the scan signal SS applied from the gate driver 320 through the gate line GL, the data voltage Vdata supplied through the data line DL is displayed. It is supplied to the gate electrode G2 of the second thin film transistor TR2 connected to the element 710 . The data voltage Vdata is charged in the storage capacitor Cst formed between the gate electrode G2 and the source electrode S2 of the second thin film transistor TR2.

The amount of current supplied to the organic light emitting diode (OLED), which is the display element 710, through the second thin film transistor TR2 is controlled according to the data voltage Vdata. Accordingly, the amount of light output from the display element 710 is controlled. Gradation can be controlled.

Referring to FIGS. 17 and 18 , the first thin film transistor TR1 , the second thin film transistor TR2 , and the storage capacitor Cst are disposed on the base substrate 110 .

The thin film transistors (TFTs) of the above-described thin film transistor substrates (100, 201, 202, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300) are the first of the display device 1400. It may be applied to at least one of the thin film transistor TR1 and the second thin film transistor TR2. The capacitors Cap of the above-described thin film transistor substrates 100, 201, 202, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, and 1300 are capacitors Cst of the display device 1400. ) can be applied.

The base substrate 110 may be made of glass or plastic. As the base substrate 110, a plastic having a flexible property, for example, polyimide (PI) may be used.

Referring to FIGS. 17 and 18 , light blocking layers 115 and 116 may be disposed on the base substrate 110 .

The light blocking layers 115 and 116 may have light blocking properties. The light blocking layers 115 and 116 may protect the active layers A1 and A2 by blocking light incident from the outside.

A buffer layer 120 is disposed on the light blocking layers 115 and 116 . The buffer layer 120 is made of an insulating material and protects the active layers A1 and A2 from moisture or oxygen introduced from the outside.

The active layer A1 of the first thin film transistor TR1 and the active layer A2 of the second thin film transistor TR2 are disposed on the buffer layer 120 . The active layers A1 and A2 may include, for example, an oxide semiconductor material.

In addition, a first capacitor electrode CE1 is disposed on the buffer layer 120 . The first capacitor electrode CE1 includes an active material layer 230 and a metal-containing layer 240 . The active material layer 230 may be made of the same material as the active layer A2 of the second thin film transistor TR2. The active layer A2 of the second thin film transistor TR2 and the active material layer 230 may be integrally formed.

A gate insulating layer 140 is disposed on the active layers A1 and A2 and the first capacitor electrode CE1.

Gate electrodes G1 and G2 are disposed on the gate insulating layer 140 .

In addition, the drain electrode D1 of the first thin film transistor TR1 may be disposed on the gate insulating layer 140 . The drain electrode D1 of the first thin film transistor TR1 may be connected to the active layer A1 of the first thin film transistor TR1 through the second contact hole H2.

The drain electrode D1 of the first thin film transistor TR1 may be made of the same material as the gate electrodes G1 and G2.

A second capacitor electrode CE2 is disposed on the gate insulating layer 140 . The second capacitor electrode CE2 may be integrally formed with the drain electrode D1 of the first thin film transistor TR1. The drain electrode D1 of the first thin film transistor TR1 may be extended to become the second capacitor electrode CE2.

Also, the second capacitor electrode CE2 may be integrally formed with the gate electrode G2 of the second thin film transistor TR2. The second capacitor electrode CE2 may be extended to become a gate electrode G2 of the second thin film transistor TR2.

According to another embodiment of the present invention, the drain electrode D1 of the first thin film transistor TR1, the second capacitor electrode CE2, and the gate electrode G2 of the two thin film transistors TR2 may be integrally formed. there is.

The second capacitor electrode CE2 may be connected to the light blocking layer 116 disposed below the first capacitor electrode CE1 through the third contact hole H3. The light blocking layer 116 connected to the second capacitor electrode CE2 may serve as the third capacitor electrode CE3.

The first capacitor C2 is formed by the first capacitor electrode CE1 and the second capacitor electrode CE2, and the second capacitor C2 is formed by the first capacitor electrode CE1 and the third capacitor electrode CE3. can be formed. As a result, the storage capacitor Cst may be formed. The storage capacitor Cst may include a first capacitor C1 and a second capacitor C2.

An interlayer insulating layer 170 is disposed on the gate electrodes G1 and G2, the drain electrode D1 of the first thin film transistor TR1, and the second capacitor electrode CE2. The interlayer insulating film 170 may have a single film structure or a multilayer film structure.

The data line DL, the driving power line PL, the source electrodes S1 and S2, and the drain electrode D2 of the second thin film transistor TR2 may be disposed on the interlayer insulating layer 170 .

The source electrode S1 of the first thin film transistor TR1 may be integrally formed with the data line DL. A portion of the data line DL may be extended to become a source electrode S1 of the first thin film transistor TR1.

The source electrode S1 of the first thin film transistor TR1 may be connected to the active layer A1 of the first thin film transistor TR1 through the first contact hole H1.

The drain electrode D2 of the second thin film transistor TR2 may be integrally formed with the driving power line PL. A portion of the driving power line PL may be extended to become a drain electrode D2 of the second thin film transistor TR2.

The drain electrode D2 of the second thin film transistor TR2 may be connected to the active layer A2 of the second thin film transistor TR2 through the fifth contact hole H5.

The source electrode S2 of the second thin film transistor TR2 may be connected to the active layer A2 of the second thin film transistor TR2 through the fourth contact hole H4.

A planarization layer 175 is disposed on the data line DL, the driving power line PL, the source electrodes S1 and S2, and the drain electrode D2 of the second thin film transistor TR2. The planarization layer 175 planarizes upper portions of the first thin film transistor TR1 and the second thin film transistor TR2 and protects the first thin film transistor TR1 and the second thin film transistor TR2.

The first electrode 711 of the display element 710 is disposed on the planarization layer 175 . The first electrode 711 of the display element 710 may be connected to the source electrode S2 of the second thin film transistor TR2 through the sixth contact hole H6 formed in the planarization layer 175 .

A bank layer 750 is disposed on the edge of the first electrode 711 . The bank layer 750 defines a light emitting area of the display element 710 .

An organic emission layer 712 is disposed on the first electrode 711 , and a second electrode 713 is disposed on the organic emission layer 712 . Thus, the display element 710 is completed. The display element 710 shown in FIG. 18 is an organic light emitting diode (OLED). Accordingly, the display device 100 according to an exemplary embodiment of the present invention is an organic light emitting display device.

19 is a circuit diagram of one pixel P of a display device 1500 according to another embodiment of the present invention.

19 is an equivalent circuit diagram of a pixel P of an organic light emitting display device.

A pixel P of the display device 1000 shown in FIG. 19 includes an organic light emitting diode (OLED) as a display element 710 and a pixel driver PDC that drives the display element 710 . The display element 710 is connected to the pixel driver (PDC).

In the pixel P, signal lines DL, GL, PL, RL, and SCL for supplying signals to the pixel driver PDC are disposed.

The data voltage Vdata is supplied to the data line DL, the scan signal SS is supplied to the gate line GL, and the driving voltage Vdd for driving the pixel is supplied to the driving power line PL. The reference voltage Vref is supplied to the reference line RL, and the sensing control signal SCS is supplied to the sensing control line SCL.

The pixel driver PDC may include, for example, a first thin film transistor TR1 (switching transistor) connected to the gate line GL and the data line DL, and the data voltage transmitted through the first thin film transistor TR1 ( A second thin film transistor TR2 (driving transistor) controlling the amount of current output to the display element 710 according to Vdata and a third thin film transistor TR3 for sensing characteristics of the second thin film transistor TR2. (sensing transistor).

The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL and applies the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin film transistor TR2. send to

The storage capacitor Cst is positioned between the gate electrode of the second thin film transistor TR2 and the display element 710 .

The third thin film transistor TR3 is connected to the first node n1 between the second thin film transistor TR2 and the display element 710 and the reference line RL, and is turned on or turned on by the sensing control signal SCS. It is turned off, and the characteristic of the second thin film transistor TR2 serving as a driving transistor is sensed during the sensing period.

The second node n2 connected to the gate electrode of the second thin film transistor TR2 is connected to the first thin film transistor TR1. A storage capacitor Cst is formed between the second node n2 and the first node n1.

When the first thin film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin film transistor TR2. The data voltage Vdata is charged in the storage capacitor Cst formed between the gate electrode and the source electrode of the second thin film transistor TR2.

When the second thin film transistor TR2 is turned on, current is supplied to the display element 710 through the second thin film transistor TR2 by the driving voltage Vdd for driving the pixel, and the light is emitted from the display element 710. is output

20 is a circuit diagram of one pixel of the display device 1600 according to another embodiment of the present invention.

A pixel P of the display device 1100 shown in FIG. 20 includes an organic light emitting diode (OLED) as a display element 710 and a pixel driver PDC that drives the display element 710 . The display element 710 is connected to the pixel driver (PDC).

The pixel driver PDC includes thin film transistors TR1 , TR2 , TR3 , and TR4 .

In the pixel P, signal lines DL, EL, GL, PL, SCL, and RL for supplying driving signals to the pixel driver PDC are disposed.

Compared to the pixel P of FIG. 19 , the pixel P of FIG. 20 further includes an emission control line EL. The emission control signal EM is supplied to the emission control line EL.

Compared to the pixel driving unit PDC of FIG. 19 , the pixel driving unit PDC of FIG. 20 further includes a fourth thin film transistor TR4 which is an emission control transistor for controlling the emission timing of the second thin film transistor TR2. include

The storage capacitor Cst is positioned between the gate electrode of the second thin film transistor TR2 and the display element 710 .

The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL and applies the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin film transistor TR2. send to

The third thin film transistor TR3 is connected to the reference line RL, turned on or off by the sensing control signal SCS, and detects the characteristics of the second thin film transistor TR2 as a driving transistor during a sensing period.

The fourth thin film transistor TR4 transmits the driving voltage Vdd to the second thin film transistor TR2 or blocks the driving voltage Vdd according to the emission control signal EM. When the fourth thin film transistor TR4 is turned on, current is supplied to the second thin film transistor TR2 and light is output from the display element 710 .

The pixel driver PDC according to another embodiment of the present invention may be formed in various structures other than the structure described above. The pixel driver PDC may include, for example, five or more thin film transistors.

The present invention described above is not limited by the above-described embodiments and the accompanying drawings, and it is in the technical field to which the present invention belongs that various substitutions, modifications, and changes are possible within the scope of the technical details of the present invention. It will be clear to those skilled in the art. Therefore, the scope of the present invention is indicated by the claims to be described later, and all changes or modifications derived from the meaning, scope and equivalent concepts of the claims should be construed as being included in the scope of the present invention.

110: base substrate 120: buffer layer
115, 116: light blocking layer 130: active layer
130n: channel unit 131: first connection unit
132: second connection part 140: gate insulating film
150: gate electrode 230: active material layer
240: metal-containing layer 710: display element
CE1: first capacitor electrode CE2: second capacitor electrode
CE3: third capacitor electrode

Claims (21)

thin film transistors on the base substrate; and
A capacitor connected to the thin film transistor; includes,
The thin film transistor,
an active layer on the base substrate; and
A gate electrode spaced apart from the active layer and at least partially overlapping the active layer; includes;
the capacitor,
a first capacitor electrode disposed on the same layer as the active layer; and
A second capacitor electrode disposed on the same layer as the gate electrode and overlapping the first capacitor electrode;
The first capacitor electrode,
an active material layer made of the same material as the active layer; and
A metal-containing layer disposed on the active material layer and including a metal;
The thin film transistor substrate of claim 1 , wherein the metal-containing layer includes a different type of metal than the active material layer. According to claim 1,
The second capacitor electrode is made of the same material as the gate electrode, the thin film transistor substrate. According to claim 1,
The active layer is connected to any one of the first capacitor electrode and the second capacitor electrode, the thin film transistor substrate. According to claim 1,
The active layer is connected to the first capacitor electrode,
The gate electrode is connected to the second capacitor electrode, the thin film transistor substrate. According to claim 1,
The active layer is connected to the second capacitor electrode, the thin film transistor substrate. According to claim 1,
The capacitor further comprises a third capacitor electrode disposed between the base substrate and the first capacitor electrode. According to claim 6,
Further comprising a light blocking layer disposed between the base substrate and the active layer,
The light blocking layer is made of the same material as the third capacitor electrode, the thin film transistor substrate. According to claim 1,
The metal-containing layer,
a metal layer on the active material layer; and
A metal oxide layer on the metal layer; including,
thin film transistor substrate. According to claim 1,
The thin film transistor substrate of claim 1 , wherein each of the active layer and the active material layer includes an oxide semiconductor material. According to claim 1,
The active layer and the active material layer,
a first oxide semiconductor layer; and
a second oxide semiconductor layer on the first oxide semiconductor layer;
Including, thin film transistor substrate. According to claim 1,
The metal-containing layer includes titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), rubidium (Rb), cesium (Cs), magnesium (Mg), A thin film transistor substrate comprising at least one selected from calcium (Ca), strontium (Sr), lanthanum (La), and palladium (Pd). According to claim 1,
The active layer includes a channel portion, a first connection portion connected to one side of the channel portion, and a second connection portion connected to the other side of the channel portion;
A reducing material layer is disposed on the first connection part and the second connection part,
The thin film transistor substrate of claim 1, wherein the reducible material layer has the same composition as the metal-containing layer. According to claim 12,
The thin film transistor substrate of claim 1 , wherein the reducible material layer on the second connection portion is integrally formed with the metal-containing layer. According to claim 1,
The thin film transistor substrate of claim 1 , wherein the active layer is integrally formed with the active material layer of the first capacitor electrode. According to claim 14,
The active layer includes a channel portion, a first connection portion connected to one side of the channel portion, and a second connection portion connected to the other side of the channel portion;
The thin film transistor substrate of claim 1 , wherein the first connection portion and the second connection portion have a composition different from that of the active material layer. According to claim 15,
The first connection part and the second connection part include a dopant for ion doping, the thin film transistor substrate. According to claim 1,
The thin film transistor substrate, wherein the gate electrode is integrally formed with the second capacitor electrode. A display device comprising the thin film transistor substrate of any one of claims 1 to 17. According to claim 18,
The thin film transistor is a driving transistor, the display device. According to claim 18,
The thin film transistor is a switching transistor, the display device. According to claim 18,
The capacitor is a storage capacitor formed between the gate electrode of the thin film transistor and an active layer of the thin film transistor.

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