KR20150119921A - 제한된 기록 내구성을 갖는 캐시들에 대한 세트-간 웨어-레벨링 - Google Patents

제한된 기록 내구성을 갖는 캐시들에 대한 세트-간 웨어-레벨링 Download PDF

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KR20150119921A
KR20150119921A KR1020157025301A KR20157025301A KR20150119921A KR 20150119921 A KR20150119921 A KR 20150119921A KR 1020157025301 A KR1020157025301 A KR 1020157025301A KR 20157025301 A KR20157025301 A KR 20157025301A KR 20150119921 A KR20150119921 A KR 20150119921A
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South Korea
Prior art keywords
cache
sets
memory
swap
leveling
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KR1020157025301A
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English (en)
Korean (ko)
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시앙유 동
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퀄컴 인코포레이티드
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Publication of KR20150119921A publication Critical patent/KR20150119921A/ko
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7211—Wear leveling

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
KR1020157025301A 2013-02-21 2014-02-12 제한된 기록 내구성을 갖는 캐시들에 대한 세트-간 웨어-레벨링 Abandoned KR20150119921A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/772,400 2013-02-21
US13/772,400 US9348743B2 (en) 2013-02-21 2013-02-21 Inter-set wear-leveling for caches with limited write endurance
PCT/US2014/015994 WO2014130317A1 (en) 2013-02-21 2014-02-12 Inter-set wear-leveling for caches with limited write endurance

Publications (1)

Publication Number Publication Date
KR20150119921A true KR20150119921A (ko) 2015-10-26

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KR1020157025301A Abandoned KR20150119921A (ko) 2013-02-21 2014-02-12 제한된 기록 내구성을 갖는 캐시들에 대한 세트-간 웨어-레벨링

Country Status (6)

Country Link
US (1) US9348743B2 (enExample)
EP (1) EP2959390A1 (enExample)
JP (1) JP2016507847A (enExample)
KR (1) KR20150119921A (enExample)
CN (1) CN105009093A (enExample)
WO (1) WO2014130317A1 (enExample)

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US10083120B2 (en) 2016-06-27 2018-09-25 SK Hynix Inc. Memory system, and address mapping method and access method thereof

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US9239679B2 (en) * 2013-12-19 2016-01-19 Avago Technologies General Ip (Singapore) Pte. Ltd. System for efficient caching of swap I/O and/or similar I/O pattern(s)
US9053790B1 (en) * 2014-07-01 2015-06-09 Sandisk Technologies Inc. Counter for write operations at a data storage device
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US10127157B2 (en) * 2014-10-06 2018-11-13 SK Hynix Inc. Sizing a cache while taking into account a total bytes written requirement
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US10445232B2 (en) 2015-07-14 2019-10-15 Western Digital Technologies, Inc. Determining control states for address mapping in non-volatile memories
US9921969B2 (en) 2015-07-14 2018-03-20 Western Digital Technologies, Inc. Generation of random address mapping in non-volatile memories using local and global interleaving
US10445251B2 (en) 2015-07-14 2019-10-15 Western Digital Technologies, Inc. Wear leveling in non-volatile memories
US10452560B2 (en) 2015-07-14 2019-10-22 Western Digital Technologies, Inc. Wear leveling in non-volatile memories
US10248571B2 (en) * 2016-08-11 2019-04-02 Hewlett Packard Enterprise Development Lp Saving position of a wear level rotation
US10101964B2 (en) 2016-09-20 2018-10-16 Advanced Micro Devices, Inc. Ring buffer including a preload buffer
US10503649B2 (en) * 2016-11-28 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit and address mapping method for cache memory
US10475519B2 (en) 2018-03-23 2019-11-12 Micron Technology, Inc. Methods for detecting and mitigating memory media degradation and memory devices employing the same
CN108920386B (zh) * 2018-07-20 2020-06-26 中兴通讯股份有限公司 面向非易失性内存的磨损均衡及访问方法、设备和存储介质
US11537307B2 (en) 2018-08-23 2022-12-27 Micron Technology, Inc. Hybrid wear leveling for in-place data replacement media
US10761739B2 (en) 2018-08-23 2020-09-01 Micron Technology, Inc. Multi-level wear leveling for non-volatile memory
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US11194582B2 (en) 2019-07-31 2021-12-07 Micron Technology, Inc. Cache systems for main and speculative threads of processors
US12223172B2 (en) * 2022-12-28 2025-02-11 SK hynix NAND Product Solutions Corporation Systems, methods, and media for controlling background wear leveling in solid-state drives

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10083120B2 (en) 2016-06-27 2018-09-25 SK Hynix Inc. Memory system, and address mapping method and access method thereof

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Publication number Publication date
EP2959390A1 (en) 2015-12-30
CN105009093A (zh) 2015-10-28
US9348743B2 (en) 2016-05-24
JP2016507847A (ja) 2016-03-10
WO2014130317A1 (en) 2014-08-28
US20140237160A1 (en) 2014-08-21

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