KR20150108487A

KR20150108487A - Method for improving Ruggedness of N-source of Power MOSFET

Info

Publication number: KR20150108487A
Application number: KR1020140031192A
Authority: KR
Inventors: 박용포; 정은식
Original assignee: 메이플세미컨덕터(주)
Priority date: 2014-03-17
Filing date: 2014-03-17
Publication date: 2015-09-30

Abstract

An embodiment of the present invention relates to a method of manufacturing an N-source for improving the ruggedness of a power MOSFET. The method includes forming gates in a semiconductor substrate, implanting second conductive impurities into the semiconductor substrate Forming a second conductive type first body, forming a first conductive type source region on a surface of the semiconductor substrate adjacent to the gate, forming an interlayer insulating film on the semiconductor substrate on which the source region is formed Forming a contact hole or a trench between adjacent trench gates by sequentially etching the interlayer insulating film and the semiconductor substrate and implanting a second conductive type impurity on the surface of the semiconductor substrate exposed by the contact hole or trench, Forming a second body of a second conductivity type; forming a second body of a second conductivity type; An N-source preparation method can be provided.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an N-source manufacturing method for improving the ruggedness of a power MOSFET,

The present invention relates to a method for manufacturing an N-source for improving the ruggedness of a Power MOSFET.

For a MOS gate type transistor such as a power MOS field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT), it should have sufficient ruggedness. Here, the robustness can be defined as indicating the degree of resistance to the avalanche current.

Particularly, when the MOS gate type transistor is used in connection with a load having an inductor, the degree of rigidity acts as an important factor for the stability of the device. Uncamp ed inductive switching (UIS) can occur in such a situation, and a large amount of current may suddenly flow inside the MOS gate type transistor, possibly leading to failure of the device .

More specifically, when the current flowing through the inductor is suddenly turned off, a counter electromotive force (counter EMF) is generated, and this counter electromotive force can generate a very high potential at both ends of the MOS gate type transistor which is a switching device. As such, the potential developed across the MOS gate transistor may exceed the rated breakdown of the transistor, resulting in catastrophic failure.

Current semiconductor device manufacturing techniques require high integration. In order to increase the integration of such semiconductor devices, for example, much efforts have been made to reduce the gate width of MOS FETs (MOSFETs). As the line width of the gate of the semiconductor device is reduced, the length of the channel of the semiconductor device is also shortened at the same time. Called short channel effect in which the threshold voltage of the transistor is rapidly lowered as the channel length is shortened is a problem. In order to improve the show channel effect, a trench MOSFET has been attracting attention because a channel is formed by forming a recess in a silicon substrate to manufacture a transistor.

When the MOSFET is switched from the on state to the off state, a voltage higher than the rated voltage of the drive voltage is instantaneously applied to the MOSFET, causing unwanted electron charges to flow through the MOSFET. This is called transient current. If such a transient current is not properly removed, the MOSFET breaks down.

Therefore, one of the ways to effectively extract the transient current injected into the MOSFET instantaneously while the MOSFET is off is to lower the body resistance of the semiconductor substrate.

That is, it is possible to improve the UCL (Unclamped Inductive Switching) characteristic by lowering the body resistance by increasing the body implant dose for forming the body. However, since the threshold voltage (Vth) of the MOSFET is reduced by the implant process for lowering the body resistance, The switching speed and the power consumption of the MOSFET device can be increased.

Korean Patent Publication No. 10-2004-0083732

An object of the present invention is to provide a MOSFET manufacturing method capable of improving UIS characteristics without changing a threshold voltage.

One embodiment in accordance with the present invention is directed to a method of manufacturing a semiconductor device, comprising: forming gates in a semiconductor substrate; implanting a second conductive impurity into the semiconductor substrate in which the gates are formed to form a first body of the second conductivity type; Forming a first conductive type source region on a surface of a semiconductor substrate on which the source region is formed, forming an interlayer insulating film on the semiconductor substrate on which the source region is formed, etching the interlayer insulating film and the semiconductor substrate sequentially, Forming a second conductive type second body by implanting a second conductive type impurity on the surface of the semiconductor substrate exposed by the contact hole or trench, forming a contact hole or trench, Source manufacturing method for improvement of the N-source.

In one embodiment, the method of fabricating a trench MOSFET may further include forming a spacer in the contact hole or trench sidewall, wherein the forming of the contact hole or trench may include penetrating the interlayer dielectric and the source region Thereby forming a contact hole or a trench exposing a part of the second conductive type first body.

In another embodiment, the concentration of the second body of the second conductivity type is greater than the concentration of the second conductive type body, and the step of forming the first body of the second conductivity type comprises: And the depth of the first body region is smaller than the depth of the trench gate.

Another embodiment in accordance with the present invention is directed to a method of manufacturing a semiconductor device, comprising: forming gates in a semiconductor substrate; implanting a second conductive impurity into the semiconductor substrate in which the gates are formed to form a first body of the second conductivity type; Forming a first conductive type source region on a surface of a semiconductor substrate on which the source region is formed, forming an interlayer insulating film on the semiconductor substrate on which the source region is formed, etching the interlayer insulating film and the semiconductor substrate sequentially, Forming a second conductive type second body by implanting a second conductive type impurity on the surface of the semiconductor substrate exposed by the contact hole or trench, forming a contact hole or trench, It is possible to provide a power MOSFET manufactured by an N-source manufacturing method for improvement.

In one embodiment, the Power MOSFET may be formed with a spacer at the contact hole or at the sidewall of the trench, and the Power MOSFET may penetrate the interlayer insulating film and the source region to form a part of the second conductive type first body Exposed contact holes or trenches may be formed.

In one embodiment, the concentration of the second body of the second conductivity type is greater than the concentration of the second conductive type body, and the power MOSFET has a depth of the second conductivity type first body region, Lt; / RTI >

The N-source fabrication method for improving the ruggedness of the power MOSFET according to an embodiment of the present invention can minimize the risk to the limit of the photo equipment and the risk to the photo miss-alignment.

The N-source manufacturing method for improving the ruggedness of the power MOSFET according to another embodiment of the present invention can minimize the length of the N-source and improve the UIS capability.

Figures 1a and 1b show the vertical structure of a typical trench MOSFET.
2A to 2D show a method of manufacturing a trench MOSFET according to an embodiment of the present invention.
FIGS. 3A and 3B are cross-sectional views illustrating a conventional power MOSFET manufactured according to a conventional method and an N-source manufacturing method for improving the ruggedness of the power MOSFET according to the present invention.
FIGS. 4A and 4B are cross-sectional views illustrating a conventional power MOSFET manufactured according to a conventional method and an N-source manufacturing method for improving the ruggedness of the power MOSFET according to the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions of the present invention, and these may be changed according to the intention of the user, the operator, or the like.

The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art to which the present invention pertains. Only. Therefore, the definition should be based on the contents throughout this specification.

In the past few decades, the rapid growth of semiconductor technology has created many types of transistor devices, many of which have the current through the old terminals of these devices controlled by the signals supplied to the third terminal. These transistors are bipolar transistors, which include an emitter that forms the first conduction type, a base that forms the second conduction type, and a collector that forms the first conduction type. At least one amorphous silicon (a-Si) bipolar transistor has been studied on pages 714-715 of the Japanese Journal of Applied Physics (1984.9) mentioned above.

The technology has created a number of field effect transistors (FETs). In typical FETs, the current or FET's conduction channel in the activeregion is formed by carriers with only one polarity, so the number of carriers with different polarities in the current will work anyway It is meaningless. This FET is a junction field effect transistor (JFET) or a JFET, which changes the depletion layer of a reverse biased P-n junction formed between the gate electrode and the current conduction channel. The conductivity of the channel is adjusted by changing the percentage of the depleted channel as the voltage is applied to the gate.

A similar device, called a metal-semiconductor FET (metal-semiconductor FET) or MESFET, has a gate electrode made of metal that forms a Schottky barrier, such as a semiconductor material of a conduction channel.

In another well-known type of FET, the gate electrode is separated from the semiconductor channel by an insulator. Perhaps the best known isolation gate transistor is a metal-oxide-semiconductor FET or MOSFET, which is separated from the semiconductor channel by a silicon oxide insulator.

Also of relevance to the background of the present invention are these early field effect transistors (FETs), in which the semiconductor material connected between the two current path electrodes, even if there is no field provided by the control electrode It is sufficiently conductive to allow current to flow. These transistors include the JFETs and MESFETs described above wherein the depletion region formed by the contact of the semiconductor channel region of the transistor, such as the gate electrode of the transistor, can be expanded or narrowed by applying a control voltage to the gate electrode.

A more or less similar device is a depletion-mode MOS transistor.

This transistor is different from the JFET and MEFET just described because the gate electrode is electrically isolated from the semiconductor channel. However, since the semiconductor channel requires an applied voltage to the gate electrode to move the Fermi level of the channel in order to deplete the channel of the majority carriers in the absence of a voltage applied to the gate electrode, Or " off "to < / RTI > conduction and also to make the semiconductor material non-conductive, so this transistor is similar to the device described above.

The MOSFETs described above can also operate in an enhancement mode where the minority carriers of the channel are induced in the doped substrate between the source and the drain, A voltage is applied to the gate to allow the minority carriers to flow in the substrate as the voltage is applied to the source and drain. Enhancement mode MOSFETs are found in a wide range of applications and are, for example, building blocks when CMOS devices are made.

Various transistor structures with gate or grid electrodes inside the transistor between the two current carrying electrodes have also been published for the past 30 years. In US Pat. No. 3,385,731, PK Weimer (1968) discloses an organic electroluminescent device comprising an upper electrode and a lower electrode on the upper and lower sides of a semiconductor body, together with current carrying electrodes of metal, A thin film transistor having a gate electrode.

S.Teszner and R. Gicquel, "Gridistor - New Field Effect Device" Proc. In IEEE 524, pp. 1502-1513 (1964), several epitaxial grown multichannel FETs with embedded grids were disclosed, and the drain current characteristic curves for the drain voltage Both negative (negative) and positive (positive) gate voltages were provided.

This grid is composed of a diffused semiconductor type, and this grid is diffused, masked, and continuous in "Multichannel field effect transistor theory and experiment", R. Zuleeg Solid state Electronecs Vol. 10, pp. 559-576 (1967) This is in contrast to semiconductors which discussed experimental and theoretical results on unipolar multichannel FETs with a vertical channel layout compressed from a crystalline substrate using epitaxial growth. Others in C. O. Bozler, Int. A transistor having a base electrode sandwiched between " fabrication of a transparent base transistor and microuave execution "of IEEE Technical Digest, pp. 384-387 (1979) of the Electron Device Meeting was described. This is somewhat similar to the MESFET described above in its basic concept. This is a vertical structure with a crystalline n + gallium arsenide substrate on top of the emitter contact, an n-type crystalline gallium arsenide layer on the substrate, and a thin metal layer depicting tungsten over the n-type layer. This tungsten layer forms a Schottky barrier with n-type gallium arsenide.

Is patterned using X-ray lithography to create highly detailed slits that are exposed to portions of the tungsten n-type layer. It is then used to make an n-type crystalline arsenic layer of a metal-patterned epitaxial and over-growth pattern to continue the conduction path formed by the n-type gallium arsenide below the metal layer. Where the collector contact is placed on top of the n-type layer. The use of X-ray lithography allows the space between the tungsten film slits to be sufficiently narrow so that the Schottky barrier formed by the contact area between tungsten and n-type gallium arsenide expands through the slits of the metal film To form a dislocation barrier.

This barrier greatly reduces the current flowing between the emitter and collector of the device. However, applying a positive voltage to the metal layer can greatly reduce the width and strength of the extended Schottky barrier through the slits, which greatly increases the conductivity between the emitter and the collector. Thus, the channel conductivity between the emitter and the collector can be largely modulated by applying a voltage to the tungsten layer, which acts as a kind of gate electrode.

A number of J. Nishazawa et al. Disclose another FET having an epitaxial growth gate and a grid in "a field effect transistor for an analytical transistor (electrostatic induction transistor)" of the IEEE report, . In one variant, the vertically arranged channel between the source and the drain is pinch off by applying a negative bias to the gate.

On the other hand, the vertical channel is pinch-off without applying any gate bias voltage. In US Pat. No. 4,466,173, BJ Baliga (1984) describes that all crystalline FETs with a buried grid etch planar epitaxial planes to etch deep grooves and to fill them with silicon of opposite conductivity, Growth has been reported to be formed using.

The above-mentioned Nishizawa reference also discloses a thyristor made using the principles of the electrostatic induction transistor (SIT), which is a line and mesh type embedded in the n-type semiconductor portion of the diode, And a forward-biased diode provided with a gate. A large number of DE Houston is described in the IEEE report, ED-23 page 905-911 (1976), in "field terminated diodes", which are somewhat similar to two diister devices: FTD and field controlled thyristor ). These three terminal devices are characterized by having a p + anode, an n-base and an n + cathode.

The FCT includes a p-type grid embedded in the n-base.

The FDT includes a p-type grid adjacent to the n-base.

Both devices are fabricated in crystalline form using standard photolithography, diffusion and epitaxial techniques. When these devices are in the on condition, the anode and cathode junctions are forward biased and the grid contacts are open. Holes and electrons are injected into the n-base region between the anode and the cathode, thereby lowering the resistivity here because the state-voltage drop is low.

To turn these devices off, a reverse bias is applied to the grid relative to the cathode. The current flowing from the anode to the cathode flows through the grid, since the grid is an effective collector of current holes. However, this FTD can not completely shut off the current because a resistance drop occurs along the length of the fingers that limit the amount of current that can be carried by the grid. if

If the applied grid bias is large enough, the n-type material adjacent to the grid will heal the free carriers, thus depletion regions meet under the cathode to create a potential barrier. The poten- tial well thus created is a barrier that prevents electrons from being injected into the cathode. Without holes in the electrons, holes can not be injected into the anode, so the device is kept in a forward blocking state.

BJ Baliga, in "Grid Dependence Dependent on Vertical Field Controlled Thyristor (FCT) Characteristics", Solid State Electronics, Vol. 22, pp. 237-239 (1979), increases the grid depth of these devices, (diffierential blocking gain) increases exponentially, and thus the turn-off time is significantly reduced.

The unijunction transistor is a 3-terminal device with a high-impedance OFF state and a low-impedance ON state. It has two base resistor contacts that both contact one emitter junction and the body of the n-type semiconductor material. Emitter junctions are normally reverse-biased and when they are forward-biased, holes are injected into the semiconductor body, thus increasing the barrier conductivity between the emitter junction and the larger negative base This turns the device on.

The above-described thyristor devices, such as single junction transistors using current in at least a portion of the active area of the device, are comprised of a large amount of bipolar carriers that can significantly affect. However, these thyristor devices only operate in a depletion mode. I.e. the electric field applied by the grid or gate, contributes only to a reduction in the overall current flow from when no electric field is applied.

The above-described transistor devices have proven useful for a variety of purposes, which is also evidenced by the tremendous growth of the semiconductor industry in recent years. However, most of the above-described transistor technologies are related to weaknesses. For example, the vast majority of transistors that are produced today are formed of crystalline semiconductor materials, and so this can generally only be formed on crystalline substrates. Current crystalline substrates are limited in size to around 6 inches in diameter, which considerably limits the use of crystalline transistors in very large area integrated circuits.

Thus, the fabrication of large area flat panel displays or large scale integrated electronic circuits has become desirable. Most of the transistors described above are crystalline devices and have been discussed and discussed in solid state electronics literature. Therefore, they suffer from these and other limitations.

For example, the above-mentioned permeable base transistor is not only limited in its fabrication on a crystalline substrate, but also has a relatively complicated, slow, and high-temperature process for forming a crystalline conduction channel between and above metal fingers formed on the gate electrode RTI ID = 0.0 > epitaxial growth < / RTI >

Efforts have been made to fabricate transistors of non-crystalline semiconductor materials, such as amorphous silicon alloys. The term "amorphous " refers to an alloy or material having a long-range disorder, although it may have a short intermediate order or even occasionally include some crystalline particles, It is also referred to as micro crystalline matrial. These transistors consist of normally thinned films of conductors, insulators and amorphous semiconductor materials, and are therefore often referred to as thin-film transistors or TFTs. These TFTs

The gate is isolated from the conduction channel between the two current path electrodes and the voltage must be applied to the gate to move the Fermi level in the conduction channel sufficiently to normally conduct the nonconduction channel. The assignee of the present invention has contributed to the technical development of TFTs. See, for example, U.S. Patent Nos. 4,543,320 and 4,547,789, British Patent 2,067,353, and European Patent Application Serial No. 0166261, published January 2, 1986.

These U.S. patent references are more interesting, among other things, by disclosing planar TFTs made of vertical transistors with amorphous silicon alloy conduction channels and amorphous silicon alloys.

Although the TFTs previously published by the assignee and others of the present invention have significant advantages that are not required for the use of crystalline substrates or epitaxial growth, they can be used in many applications, including speed, current carrying capacity, overall efficiency, reliability, There is a desire to improve manufacturing, and this is the main reason for creating the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Figures 1a and 1b show the vertical structure of a typical trench MOSFET. 1A and 1B, when a MOSFET is switched from an on state to an off state, a voltage higher than the rated voltage of the drive voltage is instantaneously applied to the MOSFET to cause an undesired electron charge, Pass through the MOSFET. This is called transient current. If such a transient current is not properly removed, the MOSFET breaks down.

2A to 2D show a method of manufacturing a trench MOSFET according to an embodiment of the present invention.

First, as shown in FIG. 2A, a trench gate 320 is formed in a first conductive type (e.g., N type) semiconductor substrate 310. The trench type gate 320 can be formed as follows.

A first oxide film (not shown) is formed on the semiconductor substrate 310. A photolithography process is performed on the first oxide film to form a photoresist pattern. The first oxide film is etched using the photoresist pattern as an etch mask to form an oxide hard mask which exposes a part of the semiconductor substrate on which the trench gate is to be formed and then the photoresist pattern is subjected to an ashing process Remove.

Next, a reactive ion etching process using a hard mask as an etch mask is performed to form a trench (not shown) by etching a part of the semiconductor substrate, and then the hard mask is removed. Next, a gate oxide film (not shown) is grown on the inner surface of the trench by a thermal oxidation method. Then, the gate poly is gapped by using a CVD (chemicla vapor deposition) method in the trench in which the gate oxide film is formed.

The second conductive type first body region 315 is formed by implanting a second conductive type impurity (for example, P type) into the semiconductor substrate on which the trench type gate 320 is formed. At this time, the depth of the second conductive type first body region 315 formed in the semiconductor substrate 310 may be shallower than the depth of the trench type gate 320.

The trench type gate 320 may be formed after the first conductive type first body 315 is formed first. That is, the implant process is performed first, and an etching process, a gate oxide film forming process, and a gate polygap fill process are performed on the semiconductor substrate on which the second conductive type first body 315 is formed to form the trench gate 320 .

Next, as shown in FIG. 2B, a first conductive impurity is implanted into the semiconductor substrate 310 having the second conductive type first body 315 and the trench type gate 320, The first conductive type source region 325 is formed on the surface of the adjacent semiconductor substrate 310. [

Next, as shown in FIG. 2C, interlayer insulating films 330 and 335 are formed on the semiconductor substrate 310 on which the source region 325 is formed. At this time, the interlayer insulating layer 330 may have a structure in which at least one of an oxide layer 330 and a BPSG (Boro-Phospho Silicate Glass) 335 is stacked.

Subsequently, a photoresist pattern (not shown) is formed on the interlayer insulating film 330 and the interlayer insulating films 330 and 335 and the semiconductor substrate 310 are etched using the photoresist pattern as a mask to penetrate the interlayer insulating film, A contact hole or trench is formed to expose a part of the semiconductor substrate 310 between the semiconductor substrate 310 and the semiconductor substrate 310. The photoresist pattern is removed through an ashing process.

For example, the interlayer insulating films 330 and 335 and the semiconductor substrate 310 are etched to form contact holes or trenches that penetrate the interlayer insulating films 330 and 335 and the source regions to expose a portion of the second conductive type first body, Can be formed.

And spacers 340 at the contact holes or trenches and sidewalls. For example, an etch back process may be performed after depositing an insulating film (e.g., an oxide film or a nitride film) on the interlayer insulating film on which the contact hole or trench is formed, thereby forming the spacer 340 on the contact hole or the trench side wall. The formation of the spacers 340 reduces the surface of the semiconductor substrate 310 exposed by the contact holes or trenches.

Next, as shown in FIG. 2D, a second conductive type impurity is implanted into the exposed surface of the semiconductor substrate 310 using the spacer 340 as a mask to form a first conductive type impurity having a concentration different from that of the second conductive type first body The second conductive type second body 350 is formed.

For example, when the second conductive type impurity is implanted into the second conductive type first body 325 exposed using the spacer 340 as a mask, the second conductive type impurity is implanted into the second conductive type first body 325 having a concentration larger than that of the second conductive type first body. The second body 350 can be formed.

As shown in FIG. 2D, when the spacer 340 is formed after the formation of the contact hole or the trench, the size of the spacer 340 is variously adjusted during the ion implantation for forming the second conductive type second body 350, The impurity concentration of the A region can be freely adjusted

Also, unlike the above description, the step of forming the spacer may be omitted, and the second conductive type second body may be formed by implanting the second conductive type impurity.

When the body doping is uniformly injected into the channel region of the MOSFET, the doping level in the entire body region is uniform.

In this case, when the body ion implantation concentration is increased to improve the UIS characteristics, the UIS characteristics can be improved in the A region, but the B region is also affected and the threshold voltage of the MOSFET is increased.

Therefore, in the method of manufacturing a trench MOSFET according to an embodiment of the present invention, a body doping profile is unevenly formed by multi-step ion implantation of a body doping method, thereby not affecting a threshold voltage of a channel region , The UIS characteristics can be improved.

FIGS. 3A and 3B are cross-sectional views illustrating a conventional power MOSFET manufactured according to a conventional method and an N-source manufacturing method for improving the ruggedness of the power MOSFET according to the present invention.

Referring to FIGS. 3A and 3B, in order to improve the UIS performance of a conventional power discrete element, a short N-type source is used. The length of the N-source is formed using a 0.5 um to 1.5 um design, which is the limit of the photo equipment. The method proposed in this patent is to provide a minimum distance by performing isotropic etching during poly etching instead of designing the distance of Poly N source to 0um. The advantage of this patent is that it minimizes the risk to the limit of the photo equipment and the risk to the photo miss-alignment, and also minimizes the length of the N-source, thereby improving the UIS capability.

FIGS. 4A and 4B are cross-sectional views illustrating a conventional power MOSFET manufactured according to a conventional method and an N-source manufacturing method for improving the ruggedness of the power MOSFET according to the present invention.

Referring to Figure 4A, Aniso. Cl2, C2F6 and He gas were used in the polyetching. This has the advantage that there is little CD change. However, the etch throughput is not good, a lot of polycorns are generated, and the oxide dry etching or Descum process is required before the polyetching.

Also, if the angle control of the poly-etch is not available, Vth scattering can be caused by the difference in the Rp value of the ion species in the tail part of the ion implantation.

Referring to FIG. 4A, Iso. O2 and SF6 gas were used for polyetching. This results in good etch through out and low polycorn generation.

However, CD changes are sensitive. That is, the sensitivity is ISO> Negaiso> Aniso.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be understood that the invention may be varied and varied without departing from the scope of the invention.

310: substrate
315: First body
320: trench gate
325: source region
330: Interlayer insulating film
335: Interlayer insulating film
340: Spacer
350: Second body

Claims

Forming gates in a semiconductor substrate;
Implanting a second conductive impurity into the semiconductor substrate having the gates formed therein to form a first body of the second conductivity type;
Forming a first conductive type source region on a surface of a semiconductor substrate adjacent to the gate;
Forming an interlayer insulating film on the semiconductor substrate on which the source region is formed;
Sequentially etching the interlayer insulating film and the semiconductor substrate to form contact holes or trenches between adjacent trenches; And
Implanting a second conductive impurity on the surface of the semiconductor substrate exposed by the contact hole or trench to form the second conductive type second body;
A method for fabricating an N-source for improving the ruggedness of a power MOSFET comprising:

The method according to claim 1,
The method of manufacturing a trench MOSFET,
Forming a spacer in the contact hole or trench sidewall;
Wherein the step of forming the N-source comprises the steps of:

The method according to claim 1,
Wherein forming the contact hole or trench comprises:
And forming a contact hole or trench through the interlayer insulating film and the source region to expose a portion of the second conductive type first body.

The method according to claim 1,
Wherein the concentration of the second body of the second conductivity type is greater than the concentration of the second body of the second conductivity type.

The method according to claim 1,
Wherein forming the first body of the second conductivity type comprises:
Wherein a depth of the second conductive type first body region is smaller than a depth of the trench type gate, and the second conductive type first body region is formed in the semiconductor substrate so that the depth of the second conductive type first body region is smaller than the depth of the trench type gate.

Forming gates in a semiconductor substrate;
Implanting a second conductive impurity into the semiconductor substrate having the gates formed therein to form a first body of the second conductivity type;
Forming a first conductive type source region on a surface of a semiconductor substrate adjacent to the gate;
Forming an interlayer insulating film on the semiconductor substrate on which the source region is formed;
Sequentially etching the interlayer insulating film and the semiconductor substrate to form contact holes or trenches between adjacent trenches; And
Implanting a second conductive impurity on the surface of the semiconductor substrate exposed by the contact hole or trench to form the second conductive type second body;
A power MOSFET fabricated by N-source fabrication method to improve the ruggedness of Power MOSFET.

The method according to claim 6,
The power MOSFET includes:
And a spacer is formed on the contact hole or the trench sidewall.

The method according to claim 6,
The Power MOSFET
And a contact hole or trench is formed through the interlayer insulating film and the source region to expose a part of the second conductive type first body.

The method according to claim 6,
Wherein the concentration of the second body of the second conductivity type is greater than the concentration of the second body of the second conductivity type.

The method according to claim 6,
The Power MOSFET
And a depth of the second conductive type first body region is smaller than a depth of the trench type gate.