JP2003158265A - Field-effect transistor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field-effect transistor having low ON resistance and a high breakdown voltage and to provide its manufacturing method. SOLUTION: A field-effect transistor is equipped with an N<-> -type epitaxial region 21 which is lower in impurity concentration than an N<+> -type SiC substrate 11 and provided to it, an N<+> -type channel region 100 which is formed in a prescribed region of the surface layer of the epitaxial region 21, as deep as prescribed, and not degraded, a degraded P<++> -type source region 110 which is formed in a prescribed region of the surface layer of the epitaxial region 21 connected to the channel region 100, and as deep as prescribed, a gate insulating film 51 formed on the surface of the channel region 100, and a gate electrode 61 formed on the gate insulating film 51.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor using a wide band gap semiconductor such as silicon carbide and a method for manufacturing the same, and more particularly to a technique for reducing on-resistance.

[0002]

2. Description of the Related Art Silicon carbide (hereinafter referred to as SiC) has a wide band gap, and the maximum dielectric breakdown electric field is one digit larger than that of silicon (hereinafter referred to as Si). Furthermore,
The natural oxide of SiC is SiO ₂ , and a thermal oxide film can be easily formed on the surface of silicon carbide by the same method as for Si.

Therefore, it is expected that SiC will be a very excellent material when used as a high-speed / high-voltage switching element, particularly a high-power uni / bipolar element, used in an electric vehicle, for example.

As such a power semiconductor device, there are generally used two types of structures of a power FET having a MOS structure, particularly a groove gate type MOSFET and a planar type MOSFET. The trench gate type MOSFET structure is
Since the on-resistance can be reduced and the channel density can be increased with a smaller surface area than that of the planar MOSFET, a groove gate type MO is required for an element using Si.
The SFET structure had excellent characteristics.

However, the trench gate type power MO made of SiC is used.
When an SFET is manufactured, since the dielectric breakdown electric field of SiC is larger than Si by an order of magnitude, the electric field is concentrated on the gate insulating film at the bottom of the groove to reach the insulating electric field, and the element is destroyed before the semiconductor reaches the insulating electric field. Occurs. Further, the side wall of the groove formed by dry etching, that is, the channel formation surface is damaged by ion etching, which causes a problem that the MOS interface characteristics are deteriorated and the channel resistance is increased (Japanese Patent Application No. Hei 10 (1999) -135242). -308510 gazette).

Therefore, the planar MOSFET structure has an S
It is regaining attention as an iC power transistor element. FIG. 10 shows a conventional SiC planar type MOS.
FIG. 3 is a cross-sectional view showing the structure of an FET, showing high-concentration N ⁺ type SiC
On the wide band gap semiconductor substrate 10 made of
^An epitaxial region 20 made of -type SiC is formed.

Then, a P ⁻ type base region 30 and an N ⁺ type source region 40 are formed in a predetermined region in the surface layer portion of the epitaxial region 20. In addition, N ^- type SiC
A gate electrode 60 is arranged on the epitaxial region 20 via a gate insulating film 50.
Are covered with an interlayer insulating film 70. The source electrode 80 is formed so as to be in contact with the P ⁻ type base region 30 and the N ⁺ type source region 40, and the N ⁺ type SiC substrate 1 is also formed.
A drain electrode 90 is formed on the back surface of 0.

FIG. 11 shows this planar MOSFET.
2A and 2B are explanatory diagrams schematically showing the flow of current, in which FIG. 4A shows the state when the switch is off and FIG.

As shown in FIG. 1B, the drain electrode 9
With a voltage applied between 0 and the source electrode 80,
When a positive voltage is applied to the gate electrode 60, an inverted channel region 150 is formed in the surface layer of the P ⁻ type base region 30 facing the gate electrode 60, and electrons flow from the drain electrode 90 to the source electrode 80. It becomes possible.

As shown in FIG. 1A, the drain electrode 90 and the source electrode 80 are electrically insulated by removing the voltage applied to the gate electrode 60. This will show the switching function. At this time, the breakdown voltage of the element is the P ⁻ type base region 3
The avalanche breakdown (avalanche breakdown) of the PN junction between 0 and the N ⁻ type epitaxial region 20 determines the electric field applied to the gate insulating film by the depletion layer extending from the PN junction (see reference numeral 160 in FIG. 11A). Since it is shielded, the drain breakdown voltage is high.

[0011]

However, as shown in FIG.
It is known that in the SiC planar type MOSFET as shown in FIG. 5, an incomplete crystal structure, that is, a large amount of interface states exists at the interface between the gate insulating film 50 and the inversion type channel region 150 (VV Afanasev, M. Bassler, G.
Pensl and M. Schulz, Phys, Stat. Sol. (A) 162 (19
97) 321.).

Therefore, a large amount of interface states exist in the inversion type channel in the surface layer of the channel region 150 formed by applying a voltage to the gate electrode 60, and these act as electron traps, thereby increasing the channel mobility. However, there is a problem that the on-resistance of the SiC planar MOSFET increases as a result.

The present invention has been made to solve such a conventional problem, and an object thereof is to provide a high withstand voltage field effect transistor having a low on-resistance. In particular, it is an object of the present invention to provide a normally-off voltage drive type, wide-gap semiconductor device, and a high withstand voltage field effect transistor having a low on-state resistance and a channel region having an extremely small resistance.

[0014]

To achieve the above object, the invention according to claim 1 provides a field effect transistor having a wide bandgap semiconductor substrate made of a semiconductor having a wider bandgap than silicon. A semiconductor epitaxial layer of the first conductivity type formed on a semiconductor substrate and having an impurity concentration lower than that of the wide band gap semiconductor substrate, and a degenerate layer having a predetermined depth formed in a predetermined region of a surface layer portion of the semiconductor epitaxial layer. Not a first conductivity type channel region, a degenerate second conductivity type source region having a predetermined depth, which is formed in a predetermined region of a surface layer portion of the semiconductor epitaxial layer so as to be connected to the channel region, and A gate insulating film formed on the surface of the channel region and a gate formed on the gate insulating film Characterized in that and a pole.

According to a second aspect of the present invention, in a field effect transistor having a wide bandgap semiconductor substrate made of a semiconductor having a wider bandgap than silicon, the field effect transistor is formed on the wide bandgap semiconductor substrate, and the wide bandgap semiconductor substrate is formed. Lower impurity concentration,
A first conductivity type semiconductor epitaxial layer, a groove formed in a predetermined region of a surface layer portion of the semiconductor epitaxial layer and having a predetermined depth, and a predetermined region of the semiconductor epitaxial layer formed along the groove and having a predetermined depth. A non-degenerate first conductivity type channel region having a depth, and a degenerate second region having a predetermined depth formed in a predetermined region of a surface layer portion of the semiconductor epitaxial layer so as to be connected to the channel region. A source region of conductivity type, a gate insulating film formed at least on the surface of the channel region in the groove, and a gate electrode formed inside the gate insulating film in the groove. And

According to a third aspect of the present invention, in the non-degenerate first conductivity type channel region, when a positive voltage is applied to the gate electrode, the electron concentration in the surface layer of the channel region is very high. The impurity concentration is such that a degenerate state is realized.

The invention according to claim 4 is characterized in that the second-conductivity-type low-concentration source region is formed so as to be connected to the degenerated second-conductivity-type source region.

The invention according to claim 5 is characterized in that a drain electrode is formed on the back surface of the wide band gap semiconductor substrate.

According to a sixth aspect of the present invention, the wide band gap semiconductor substrate is made of a silicon carbide semiconductor.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a field effect transistor having a wide bandgap semiconductor substrate made of a semiconductor having a bandgap wider than that of silicon.
The step 1a of forming a semiconductor epitaxial layer of the first conductivity type having an impurity concentration lower than that of the wide band gap semiconductor substrate, and a predetermined region of a surface layer portion of the semiconductor epitaxial layer having a predetermined depth and not degenerate. A second step of forming a first conductivity type channel region;
A third step of forming a degenerate second conductivity type source region having a predetermined depth in a predetermined region of the surface layer portion of the semiconductor epitaxial layer so as to be connected to the channel region, and on the surface of the channel region. It is characterized by comprising a step 4a of forming a gate insulating film and a step 5a of forming a gate electrode on the gate insulating film.

According to an eighth aspect of the present invention, there is provided a method of manufacturing a field effect transistor having a wide bandgap semiconductor substrate made of a semiconductor having a bandgap wider than that of silicon.
1b step of forming a first conductivity type semiconductor epitaxial layer having an impurity concentration lower than that of the wide band gap semiconductor substrate, and a second conductivity having a predetermined depth in a predetermined region of a surface layer portion of the semiconductor epitaxial layer. A second step of forming a low-concentration source region of a first type, and a non-degenerate first conductivity type having a predetermined depth in a predetermined region of the semiconductor epitaxial layer so as to be connected to the low-concentration source region. A third step of forming a channel region; a fourth step of forming a degenerate second conductivity type source region in a surface layer portion of the semiconductor epitaxial layer; and a step of forming a surface layer portion of the semiconductor epitaxial layer in the surface layer portion. A fifth step of forming a groove having a predetermined depth in a portion where the channel region of the first conductivity type which is not degenerated is formed, and at least before A sixth step of forming a gate insulating film on the surface of the channel region of the first conductivity type in the groove, and a seventh step of forming a gate electrode inside the gate insulating film in the groove. It is characterized by that.

[0022]

According to the invention described in claim 1, by applying a positive voltage to the gate electrode, a high concentration of electrons is induced in the surface layer of the first conductivity type channel region and the degeneracy of the electron concentration is very large. And the P ⁺ / N ⁺ in the semiconductor surface layer
By utilizing the tunnel phenomenon at the junction, a large tunnel current due to the tunnel effect can flow between the drain and source. Since the magnitude of the tunnel current depends on the concentration of electrons induced in the surface layer of the first conductivity type channel region, the drain current can be controlled by the voltage applied to the gate electrode.

Further, this tunnel current is caused by the oxide film / Si.
The influence from the C interface is small, and since it is equivalent to the diffusion current due to the injection of a normal PN junction, it is possible to dramatically reduce the channel resistance as compared with the inversion type channel. Further, since the breakdown voltage of the device can be designed to be determined by the avalanche breakdown of the PN junction between the second conductivity type source region and the first conductivity type semiconductor epitaxial layer, the breakdown resistance can be increased.

As described above, according to the first aspect of the invention, it is possible to obtain a normally-off voltage drive type high-breakdown-voltage field-effect transistor having a low on-state resistance with a very small resistance in the channel region.

According to the invention of claim 2, in addition to the effect described in claim 1, the groove gate type structure is provided.
Furthermore, the on-resistance can be reduced with a smaller surface area, and a high channel density can be achieved.

According to the third aspect of the invention, when the voltage is not applied to the gate electrode while the voltage is applied between the drain electrode and the source electrode, the electrons of the channel region of the first conductivity type are formed. Since the concentration is not high enough (not degenerate) to allow the tunnel current to flow in the second conductivity type source region, the first conductivity type channel region and the second conductivity type source region are reverse biased. Therefore, no current flows between the source and drain.

On the other hand, when a positive voltage is applied to the gate electrode, a high concentration of electrons is induced in the surface layer of the first conductivity type channel region to realize a degenerated state in which the electron concentration is very large, and a drain-source is formed. A large tunnel current due to the tunnel effect can be passed. Further, since the magnitude of the tunnel current depends on the concentration of electrons induced in the surface layer of the first conductivity type channel region, the drain current can be controlled by the voltage applied to the gate electrode.

As described above, according to the invention of claim 3, the switching function of the field effect transistor is
This can be effectively performed by the voltage applied to the S gate.

According to the fourth aspect of the invention, the second conductivity type low-concentration source region is provided so as to be connected to the degenerated second conductivity type source region. It can be designed to be determined by the avalanche breakdown of the PN junction between the low-concentration source region of the two-conductivity type and the semiconductor epitaxial layer of the first-conductivity type, and the breakdown resistance can be further increased.

According to the fifth aspect of the present invention, since the power transistor having the vertical structure can be manufactured, the on-resistance can be reduced with a smaller surface area as compared with the horizontal structure.

According to the sixth aspect of the present invention, since the wide band gap semiconductor substrate made of SiC whose maximum breakdown electric field is one digit larger than that of silicon is used, it has excellent electrical breakdown voltage characteristics. It becomes easy to increase the breakdown voltage.

According to the seventh aspect of the invention, a planar field effect transistor can be easily manufactured.

According to the method of the invention described in claim 8, a gate groove type field effect transistor can be easily manufactured.

[0034]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the present embodiment, the MIS field effect transistor in which the polysilicon electrode is formed on the gate insulating film is described as an example, but it is also possible to use the MESFET type in which Schottky metal is used for the gate electrode.

In the following, the first conductivity type is N type,
The P-type will be described as an example of the second conductivity type. Furthermore, it goes without saying that modifications are included without departing from the spirit of the present invention.

[First Embodiment; Planar Type Power Tunnel Field Effect Transistor (1)] FIG. 1 shows a unit cell of a SiC planar type power tunnel field effect transistor according to a first embodiment of the present invention. FIG.

As shown in the figure, N serving as a drain region is formed.
^The N ⁻ type epitaxial region 21 is formed on the ⁺ type SiC substrate 11.
Of the N ^- type epitaxial region 21 in the stacked wafers (that is, the impurity density is high so that the Fermi level is in the valence band).
A P ⁺⁺ type source region 110 is formed.

Similarly, a non-degenerate N ⁺ type channel region 10 is formed in a predetermined region of the N ⁻ type epitaxial region 21.
0 is formed. In addition, the N ⁺ type channel region 100
On the surface of the gate electrode 61 via the gate insulating film 51.
And the gate electrode 61 is covered with an interlayer insulating film 71. Here, the N ⁺ channel region 100 is the channel region 100 when a positive voltage is applied to the gate electrode 61.
The surface layer is designed to have a large impurity concentration such that a degenerated state in which the electron concentration is very large is realized.

A source electrode 81 is formed on the P ⁺⁺ type source region 110, and a drain electrode 91 is formed on the back surface of the N ⁺ type SiC substrate 11.

Next, an example of a method of manufacturing the SiC planar power tunnel field effect transistor according to this embodiment will be described with reference to the sectional views shown in FIGS. 2 (a) to 2 (c) and 3 (d) to 3 (f). It will be explained with reference to FIG.

First, in the step of FIG. 2A, N ⁺ type Si is used.
On the C substrate 11, for example, an impurity concentration of 1E14 to 1E
An N ⁻ type SiC epitaxial region 21 having a thickness of 18 / cm ³ and a thickness of 1 to 100 μm is formed (step 1a).

Next, in the step of FIG. 3B, the N ⁻ type SiC epitaxial region 21 is formed by using the mask material 130.
In a predetermined region of, for example, phosphorus ions are multi-steply implanted at a high temperature of 100 to 1000 ° C. at an acceleration voltage of 100 to 3 MeV,
An N ⁺ type (non-degenerate) channel region 100 is formed (step 2a). At this time, the total dose amount is, for example, 1E14 to 1E16 / cm ² . As the N-type impurity, nitrogen, arsenic, or the like may be used in addition to phosphorus.

In the step of FIG. 2C, the mask material 131 is removed.
For example, at a high temperature of 100 to 1000 ° C.
Multi-stage implantation of um ions at an acceleration voltage of 100-5 MeV
Then P ⁺⁺Form a mold (degenerate) source region 110
(Step 3a). At this time, the total dose is
For example, 1E14-1E17 / cm²Is. With P-type impurities
In addition to aluminum, use boron, gallium, etc.
May be.

In this example, the N ⁺ type channel region 10 is used.
Phosphorus ion implantation for forming 0 was performed first, but P ⁺⁺
It is also possible to perform the aluminum ion implantation for forming the type source region 110 first and then perform the phosphorus ion implantation for forming the N ⁺ type channel region 100.

Next, in the step of FIG. 3D, for example,
Heat treatment is performed at 1000 to 1800 ° C. to activate the implanted impurities.

In the step of FIG. 3E, the gate insulating film 51 is formed on the surface of the epitaxial region 21 including the upper surface of the N ⁺ type channel region 100 by thermal oxidation at 900 to 1300 ° C. (fourth a). Step). afterwards,
The gate electrode 61 is formed of, for example, polysilicon (step 5a).

In the step of FIG. 3F, a metal film is deposited on the back surface of the SiC substrate 11 as the drain electrode 91. Also,
After forming the interlayer insulating film 71, a contact hole is opened and a source electrode 81 is formed on the P ⁺⁺ type source region 110. And it heat-processes at about 600-1400 degreeC, for example, and it is set as an ohmic electrode. By such a procedure, the field effect transistor shown in FIG. 1 is completed.

FIG. 4 is an explanatory view schematically showing the flow of electrons in the above field effect transistor.
The operation of this field effect transistor will be described with reference to FIG.

FIG. 4A shows a state in which the field effect transistor is off, in which the gate electrode 6 is in a state in which a voltage is applied between the drain electrode 91 and the source electrode 81.
N ⁺ type channel region 1 when no voltage is applied to 1
Since the electron concentration of 00 is not high enough (not degenerated) to allow the tunnel current to flow in the P ⁺⁺ type source region 110, the channel region 100 and the source region 110 are not.
Is reverse biased by the voltage applied to the drain electrode 91, and no current flows between the source and drain.

At this time, the breakdown voltage of the device is determined by the PN between the P ^{+ +} type source region 110 and the N ⁻ type epitaxial region 21.
The drain breakdown voltage is high because the electric field applied to the gate insulating film, which is determined by the avalanche breakdown of the junction, is shielded by the depletion layer extending from the PN junction.

On the other hand, as shown in FIG. 4B, when a positive voltage is applied to the gate electrode 61, a high concentration of electrons is induced in the surface layer of the N ⁺ type channel region 100, and the electron concentration is very large. The degenerated region 170 is formed, and the width of the depletion layer formed at the PN junction boundary between the degenerated region 170 and the P ^{+ +} type source region 110 is about 10 nm. Since electrons can pass through this depletion layer by a tunnel phenomenon, from the channel region 100 to the source region 110,
A large tunnel current due to the tunnel effect can be passed.

As a result, it is possible to obtain a normally-off voltage drive type field-effect transistor having a low on-resistance and a very low resistance in the channel region.

In particular by applying the method of the invention,
By applying a positive voltage to the gate electrode 61, a tunneling phenomenon at the P ⁺ / N ⁺ junction in the semiconductor surface layer can be used, and a large tunneling current due to the tunnel effect can flow between the drain and the source. The magnitude of the tunnel current is N
^The drain current can be controlled by the voltage applied to the gate electrode 61 because it depends on the concentration of electrons induced in the surface layer of the ⁺ type channel region 100.

Further, this tunnel current is caused by the oxide film / Si
There is little influence from the C interface, and the normal PN junction
Inversion type channel because it is equivalent to the diffusion current due to
Can dramatically reduce the channel resistance compared to
It Furthermore, the breakdown voltage of the device is P ⁺⁺A mold source region 110,
N^-Of the PN junction with the epitaxial layer 21
Can be designed to be determined by the Lanche breakdown
Therefore, the breakdown voltage can be increased and the drain breakdown voltage is high.
Yes.

[Second Embodiment: Gate Trench Type Power Tunnel Field Effect Transistor] FIG. 5 is a sectional view of a unit cell of an SiC gate groove type power tunnel field effect transistor according to a second embodiment of the present invention. . As shown in the figure, on the N ⁺ type SiC substrate 12 which will be the drain region,
In the wafer in which the N ⁻ type epitaxial region 22 is laminated, the groove 140 is formed in a predetermined region on one main surface of the epitaxial region 22. Then, along this groove 140, the non-degenerate N ⁺ type channel region 101 is formed.

Further, in a predetermined region of the epitaxial region 22, the P ^{+ +} type source region 111 degenerated (that is, the impurity density is increased so that the Fermi level is in the valence band) is the N ⁺ type. It is formed so as to be connected to the channel region 101. Further, the gate insulating film 5 is formed in the groove 140.
A gate electrode 62 is embedded through the gate electrode 62, and the gate electrode 62 is covered with an interlayer insulating film 72. A source electrode 82 is formed on the P ⁺⁺ type source region 111. The drain electrode 92 is formed on the back surface of the N ⁺ type SiC substrate 12.
Are formed.

Next, an example of a method of manufacturing the SiC gate groove type power tunnel field effect transistor according to the present embodiment is shown in cross-sectional views of FIGS. 6 (a) to 6 (c) and 7 (d) to 7 (f). Will be described with reference to.

First, in the step of FIG. 6A, N ⁺ type Si is used.
On the C substrate 12, for example, the impurity concentration is 1E14 to 1
An N ⁻ -type SiC epitaxial region 22 having E18 / cm ³ and a thickness of 1 to 100 μm is formed (step 1b).

In the step of FIG. 6B, the mask material 132 is used to accelerate boron ions in a predetermined region of the N ^-- type SiC epitaxial region 22 at a high temperature of 100 to 1000 ° C. for 100 to 5 MeV. and multi-stage injection in voltage, P ^-
A mold (low concentration) source region 120 is formed (step 2b). The total dose amount is, for example, 1E13 to 1E16 /
cm ² . As the P-type impurity, aluminum, gallium, or the like may be used in addition to boron.

In the step of FIG. 6C, the mask material 133 is used to apply phosphorus ions to a predetermined region of the N ^-- type SiC epitaxial region 22 at a high temperature of 100 to 1000 ° C. and an acceleration voltage of 100 to 3 MeV. Multi-stage implantation is performed to form an N ⁺ type (non-degenerate) channel region 101 (third b)
Step). The total dose amount is, for example, 1E14 to 1E1.
6 / cm ² . As N-type impurities, besides phosphorus, nitrogen,
Arsenic or the like may be used.

In the step of FIG. 7D, for example, 100 to 1
Aluminum ion 100 ~ 3Me at high temperature of 000 ℃
Multi-stage injection is performed with an acceleration voltage of V to form a P ⁺⁺ type (degenerate) source region 111 (step 4b). The total dose amount is, for example, 1E14 to 1E17 / cm ² .
As the P-type impurity, boron, gallium, or the like may be used in addition to aluminum.

Thereafter, heat treatment is performed at, for example, 1000 to 1800 ° C. to activate the implanted impurities.

In this example, the P ^-- type source region 12 is used.
0 → N ⁺ type channel region 101 → P ⁺⁺ type source region 11
However, the formation order of the regions is not limited to this.

In the step of FIG. 7E, a mask material 134 is used to form a predetermined region on one main surface of the P ⁺⁺ source region 111.
The N ⁻ -type S penetrates the N ⁺ -type channel region 101 in the depth direction.
A groove 140 having a depth of, for example, 0.1 to 5 μm is formed so as to reach the iC epitaxial region 22 (step 5b). The bottom surface of the groove 140 may be a curved surface, or the cross-sectional shape of the groove may be a shape without a bottom surface like a V-shaped groove.

In the step of FIG. 7F, the gate insulating film 52 is formed on the surface of the groove 140 by thermal oxidation at 900 to 1300 ° C. (step 6b). Next, the gate electrode 62 is formed of, for example, polysilicon (seventh b).
Step). Thereafter, although not particularly shown, a metal film is deposited on the back surface of the SiC substrate 12 as the drain electrode 92.
Further, after forming the interlayer insulating film 72, a contact hole is opened, and the source electrode 82 is formed on the P ⁺⁺ type source region 111.
(See FIG. 5). And, for example, 600 to 14
Heat treatment is performed at about 00 ° C. to form an ohmic electrode. In this way, the field effect transistor shown in FIG. 5 is completed.

Next, the operation of this field effect transistor will be described. 8A and 8B are explanatory diagrams schematically showing the flow of electrons in the field effect transistor according to the second embodiment. FIG. 8A shows a state when the transistor is off, and FIG. 8B shows a state when the transistor is on. . When a voltage is applied between the drain electrode 92 and the source electrode 82 and no voltage is applied to the gate electrode 62, as shown in FIG. 8A, the electron concentration of the N ⁺ type channel region 101 is increased. Is a P ⁺⁺ type source area 11
1 is not high enough to allow a tunnel current to flow (not degenerate), the channel region 101 and the source region 111 are reverse-biased by the voltage applied to the drain electrode 92, and the source and drain are No current flows.

At this time, the breakdown voltage of the device is determined by the avalanche breakdown of the PN junction between the P ⁻ type source region 120 and the N ⁻ type epitaxial region 22. In particular, since the electric field applied to the gate insulating film at the bottom of the groove is shielded by the depletion layer extending from the PN junction, the drain breakdown voltage is high.

On the other hand, a positive voltage is applied to the gate electrode 62.
Then, as shown in FIG. ⁺Mold channel region 1
Electrons of high concentration are induced in the surface layer of 01
A large degenerate region 171 is formed in the
Area 171 and P⁺⁺PN junction boundary between mold source regions 111
The width of the depletion layer that can be formed is as thin as about 10 nm.
The electrons can tunnel through the depletion layer.
Therefore, from the channel region 101 to the source region 111
And a large tunnel current due to the tunnel effect
You can

As a result, it is possible to obtain a normally-off voltage-driven type field-effect transistor having a low on-resistance and a very low resistance in the channel region. In particular,
According to the present invention, by applying a positive voltage to the gate electrode 62, a tunneling phenomenon at the P ⁺ / N ⁺ junction in the semiconductor surface layer can be used to cause a large tunneling current to flow between the drain and the source due to the tunneling effect. .

Since the magnitude of the tunnel current depends on the concentration of electrons induced in the surface layer of the N ⁺ type channel region 101, the drain current can be controlled by the voltage applied to the gate electrode 62. Furthermore, this tunnel current is
The influence from the iC interface is small, and since it is equivalent to the diffusion current due to the injection of a normal PN junction, it is possible to dramatically reduce the channel resistance as compared with the inversion type channel.

The withstand voltage of the element is the P ⁻ type source region 1
Since it can be designed so as to be determined by the avalanche breakdown of the PN junction between the N 20 and the N ⁻ type epitaxial layer 22, the breakdown withstand amount can be increased and the drain breakdown voltage is high.

Further, by adopting such a trench gate type structure, it is possible to achieve a low on-resistance and a high channel density with a smaller surface area as compared with the first embodiment.

[Third Embodiment: Planar Power Tunnel Field Effect Transistor (Part 2)] FIG. 9 is a sectional view of a unit cell of a SiC planar power tunnel field effect transistor according to a third embodiment of the present invention. Is. Structurally, the difference from the first embodiment shown in FIG. 1 is that
That is, the P ⁻ type (low concentration) source region 121 is arranged below the P ⁺⁺ type source region. This P ^- type source region 1
By providing 21, the breakdown voltage of the device can be designed to be determined by the avalanche breakdown of the PN junction between the P ⁻ type source region 121 and the N ⁻ type epitaxial layer 23. It can be made larger compared to the field effect transistor shown.

Silicon carbide (SiC) has 3C-S
There are numerous polytypes such as iC, 4H-SiC, 6H-SiC, and 15R-SiC, but if the silicon carbide used as the semiconductor substrate in the present invention is SiC,
Structure with 3C-SiC on Si, 6H-SiC or 4H
A structure in which 3C-SiC is present on -SiC may be used.

In this embodiment, the drain electrode is N
^{Although the} description has been given of the field-effect transistor having the vertical structure arranged on the back surface of the ⁺ type SiC substrate, the drain electrode may have a horizontal structure in which it is formed on the same surface as the surface on which the source electrode is provided.

Further, in each of the above-mentioned embodiments, SiC is used as a semiconductor having a wider band gap than Si (silicon).
Although (silicon carbide) is described as an example, the present invention is not limited to this, and a material such as GaN or diamond can be used.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a field effect transistor according to a first embodiment of the present invention.

FIGS. 2A to 2C are first explanatory diagrams showing a manufacturing process of the field effect transistor according to the first embodiment. FIGS.

3 (d) to (f) are second explanatory views showing the manufacturing process of the field effect transistor according to the first embodiment.

FIG. 4 is an explanatory diagram schematically showing a current flow of the field effect transistor according to the first embodiment, in which (a) shows an off state and (b) shows an on state.

FIG. 5 is a sectional view showing a configuration of a field effect transistor according to a second embodiment of the present invention.

FIGS. 6A to 6C are first explanatory views showing a manufacturing process of the field effect transistor according to the second embodiment.

7 (d) to 7 (f) are second explanatory views showing the manufacturing process of the field effect transistor according to the second embodiment.

8A and 8B are explanatory diagrams schematically showing the flow of current in the field effect transistor according to the second embodiment, where FIG. 8A shows a state when the transistor is off and FIG. 8B shows a state when the transistor is on.

FIG. 9 is a sectional view showing a configuration of a field effect transistor according to a third embodiment of the present invention.

FIG. 10 is a cross-sectional view showing the structure of a conventional SiC planar MOSFET.

FIG. 11 is an explanatory view schematically showing a current flow in a conventional SiC planar MOSFET, in which (a) shows an off state and (b) shows an on state.

[Explanation of symbols]

10, 11, 12, 13 N ⁺ type SiC substrate 20, 21, 22, 23 N ⁻ type SiC epitaxial region 30 P ⁻ type base region 40 N ⁺ type base region 50, 51, 52, 53 Gate insulating film 60, 61 , 62, 63 gate electrodes 70, 71, 72, 73 interlayer insulating films 80, 81, 82, 83 source electrodes 90, 91, 92, 93 drain electrodes 100, 101, 102 N ⁺ type (not degenerate) channel region 110, 111, 112 P ⁺⁺ type (degenerate) source region 120, 121 P ⁻ type (low concentration) source region 130, 131, 132, 133, 134 Mask material 140 Groove 150 Channel region 160, 161, 162 Depletion layer 170,171 N ⁺⁺ (degenerate) region

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/78 654 H01L 29/78 301B 301J 301V

Claims (8)

[Claims] 1. A field effect transistor having a wide bandgap semiconductor substrate made of a semiconductor having a bandgap wider than that of silicon. A field effect transistor formed on the wide bandgap semiconductor substrate and having an impurity concentration lower than that of the wide bandgap semiconductor substrate. One conductivity type semiconductor epitaxial layer, a non-degenerate first conductivity type channel region formed in a predetermined region of a surface layer portion of the semiconductor epitaxial layer and having a predetermined depth, and a predetermined surface layer portion of the semiconductor epitaxial layer. A degenerate second conductivity type source region formed to connect to the channel region in a region and having a predetermined depth, a gate insulating film formed on the surface of the channel region, and on the gate insulating film. A field effect transistor, comprising: the formed gate electrode. 2. A field effect transistor having a wide bandgap semiconductor substrate made of a semiconductor having a wider bandgap than silicon, wherein the impurity concentration of the impurity formed on the wide bandgap semiconductor substrate is lower than that of the wide bandgap semiconductor substrate. A semiconductor epitaxial layer of the first conductivity type, a groove formed in a predetermined region of a surface layer portion of the semiconductor epitaxial layer, having a predetermined depth, and a predetermined region of the semiconductor epitaxial layer along the groove, a predetermined A non-degenerate first conductivity type channel region having a depth, and a degenerate second region having a predetermined depth formed in a predetermined region of a surface layer portion of the semiconductor epitaxial layer so as to be connected to the channel region. A conductive type source region and at least a surface of the channel region in the trench. A gate insulating film, field effect transistors, characterized in that it and a gate electrode formed on the inside of the gate insulating film in the trench. 3. The non-degenerate first conductivity type channel region, when a positive voltage is applied to the gate electrode,
3. The field effect transistor according to claim 1, wherein the channel region surface layer has an impurity concentration such that a degenerate state in which the electron concentration is very high is realized. 4. The low-concentration source region of the second conductivity type is formed so as to be connected to the degenerate source region of the second conductivity type. The field effect transistor according to item 1. 5. The field effect transistor according to claim 1, wherein a drain electrode is formed on the back surface of the wide band gap semiconductor substrate. 6. The field effect transistor according to claim 1, wherein a silicon carbide semiconductor is used as the wide band gap semiconductor substrate. 7. A method of manufacturing a field effect transistor having a wide bandgap semiconductor substrate made of a semiconductor having a bandgap wider than that of silicon, wherein the impurity concentration on the wide bandgap semiconductor substrate is lower than that of the wide bandgap semiconductor substrate. A first step of forming a semiconductor epitaxial layer of the first conductivity type, and forming a non-degenerate first conductivity type channel region having a predetermined depth in a predetermined region of a surface layer portion of the semiconductor epitaxial layer. 2a, and a 3a step of forming a degenerate second conductivity type source region having a predetermined depth in a predetermined region of a surface layer portion of the semiconductor epitaxial layer so as to be connected to the channel region, Fourth, forming a gate insulating film on the surface of the channel region
and a step 5a of forming a gate electrode on the gate insulating film, the method of manufacturing a field effect transistor. 8. A method for manufacturing a field effect transistor having a wide bandgap semiconductor substrate made of a semiconductor having a bandgap wider than that of silicon, wherein the impurity concentration on the wide bandgap semiconductor substrate is lower than that of the wide bandgap semiconductor substrate. 1b of forming a first conductivity type semiconductor epitaxial layer, and 2b of forming a second conductivity type low concentration source region having a predetermined depth in a predetermined region of the surface layer portion of the semiconductor epitaxial layer. And b) forming a non-degenerate first conductivity type channel region having a predetermined depth in a predetermined region of the semiconductor epitaxial layer so as to be connected to the low-concentration source region.
4b of forming a degenerate second conductivity type source region in the surface layer portion of the semiconductor epitaxial layer, and the non-degenerated first conductivity of the surface layer portion of the semiconductor epitaxial layer. A step 5b of forming a groove having a predetermined depth in the region where the channel region of the first conductivity type is formed, and a step 6b of forming a gate insulating film at least on the surface of the channel region of the first conductivity type in the groove. And a step 7b of forming a gate electrode inside the gate insulating film in the groove, the manufacturing method of a field effect transistor.