KR20150099396A - bit interleaver and bit de-interleaver - Google Patents

Abstract

The present invention relates to a bit interleaver and a bit de-interleaver. The present invention relates to a device for at least one of bit interleaving and bit de-interleaving, a system thereof, and a method thereof. For example, the embodiments of the present invention provide a bit interleaving physical layer (L1) signaling device for a current generation or next generation digital broadcasting system like a system developed by at least one of a digital video broadcasting (DVB) and an advanced television systems committee (ATSC), a system thereof, and a method thereof. The purpose of the present invention is to provide the bit interleaving and bit de-interleaving method, the apparatus thereof, and the system thereof, capable of improving performance and maintaining a relatively simple structure.

Description

[0001] DESCRIPTION [0002] BIT INTERLEAVER AND BIT DE-INTERLEAVER [

The present invention relates to an apparatus, system and method for at least one of bit interleaving and bit de-interleaving. For example, embodiments of the present invention may be applied to a bit interleaving physical layer for current and next generation digital broadcast systems, such as systems developed by at least one of the Digital Video Broadcasting (DVB) Project and the Advanced Television Systems Committee (ATSC) (L1) signaling apparatus, system, and method.

Digital broadcasting technology provides users with various types of digital contents such as video and audio data. A number of standards have been developed for this purpose, including a series of ATSC 1.0 and ATSC 2.0 standards developed by the ATSC Association. ATSC digital television (hereinafter also referred to as "DTV") standards introduced in various documents including A / 52 and A / 53 available at http://www.atsc.org/ include the United States, Canada and Korea Has been adopted for terrestrial broadcasting in various countries.

Recently, ATSC is launching a new standard known as ATSC 3.0 for both real-time and non-real-time television content and data delivery methods for fixed and mobile devices. As a part of this development, ATSC has been working on the ATSC Technology Group 3 (ATSC 3.0), 2013 (TG3-S2 Doc # 023r20, "Call for Proposals for ATSC-3.0 PHYSICAL LAYER, A Terrestrial Broadcast Standard" March 26, 2006), which aims to identify techniques that can be combined to create a new physical layer of the ATSC 3.0 standard. The ATSC 3.0 system will be designed as a hierarchical architecture, and it is understood that a generalized hierarchical model for ATSC 3.0 has been proposed. The scope of the CFP described above is limited to the base layer of this model, namely the ATSC 3.0 physical layer corresponding to Layer 1 and 2 of the ISO / IEC 7498-1 model.

ATSC 3.0 should not require backward compatibility with current broadcasting systems, including ATSC 1.0 and ATSC 2.0. However, the CFP will utilize and reference existing standards known to be effective solutions to meet these requirements wherever practicable, wherever practicable.

Other existing standards developed for digital content broadcasting include a set of open standards developed and maintained by the DVB project and published by the European Telecommunications Standards Institute (ETSI). One such standard is ETSI EN 302 755 V1.3.1 (" Digital Video Broadcasting (DVB) ") and Technical Specification ETSI TS 10 There is DVB-T2, a standard which is disclosed in several documents including < RTI ID = 0.0 > 831 V1.2.1 ("Digital Video Broadcasting (DVB); Implementation guidelines for a second generation digital terrestrial television broadcasting system (DVB-T2)

In DVB-T2, data is transmitted in a frame structure as shown in FIG. At the top level, the frame structure 100 is composed of super frames 101a, 101b and 101c divided into a plurality of T2 frames (T2-frames) 103a, 103b, 103c and 103d . Each T2 frame 103a, 103b, 103c and 103d includes a plurality of preamble symbols 105, 107a, 107b and 107c and a plurality of data symbols 109a to 109e, Multiplexing symbols are sometimes subdivided into symbols (sometimes referred to as cells). The preamble symbols 105, 107a, 107b and 107c in the T2 frames 103a, 103b, 103c and 103d correspond to one P1 preamble symbol 105 and one or more P2 preamble symbols 107a, 107b and 107c thereafter. .

P1 symbol 105 located at the beginning of T2 frames 103a, 103b, 103c and 103d signals S1 signaling and certain basic transmission parameters used to identify the format of P2 symbols 107a, 107b and 107c It carries seven bits for signaling, including the S2 signaling used to advertise. The P2 symbols 107a, 107b, 107c immediately following the P1 symbol 105 are used for fine frequency and timing synchronization and channel estimation. P2 symbols 107a, 107b, and 107c carry L1 signaling information and also carry data. L1 signaling is divided into L1-pre-signaling (L1-pre signaling) and L1-post signaling (L1-post signaling). L1-Pre-signaling includes basic information about the T2 frame structure 100 and enables reception and decoding of L1-Post signaling. The L1-Post signaling provides sufficient information for the receiver to decode Physical Layer Pipes (hereinafter also referred to as "PLPs ") in the T2-frames 103a, 103b, 103c and 103d carrying the data.

Bitstreams (e.g., signaling or data) typically undergo various types of processing and encoding before the bits are mapped to symbols (cells). Bitstreams carrying different types of information (e.g., L1-pre-signaling, L1-post signaling and data) are typically handled differently.

FIG. 2 shows an example of a bit interleaved coding and modulation (BICM) chain for processing a bitstream carrying L1-post signaling in a transmitting apparatus. The BICM chain 200 includes a segmenter 201 for dividing a bitstream into blocks of K _sig size, a decoder 201 for converting (for example, replacing) bits in each block output from the segmenter 201 A scrambler 203, and a K _bch And a Zero padder 205 for padding each block output from the scrambler 203 with zeros to obtain a padded block of size (e.g., K _bch = 7032).

BICM chain 200 N _bch represented also K _ldcp A BCH encoder (BCH encoder) 207 for BCH encoding each block output from zero fader 205 to obtain a BCH encoded block of size (e.g., N _bch = K _ldpc = 7200), and N _ldpc (LDPC encoder) 209 for LDPC encoding each block output from the BCH encoder 207 to obtain an LDPC encoded block of size (e.g., N _ldcp = _16,200 ).

The BICM chain 200 includes a parity interleaver 211 for interleaving the LDPC parity bits of each block output from the LDPC encoder 209 and a puncturer for puncturing N _punc of the LDPC parity bits puncturer 213 as shown in FIG. In the BICM chain 200, the zero-padded bits are also removed, leaving a block of N _post size.

The BICM chain 200 includes N _post (Bit interleaver) 215 for bit interleaving the respective block outputs from the puncturer 213 to obtain a bit interleaving block of a predetermined size.

Finally, the BICM chain 200 includes a demultiplexer 217 for demultiplexing each interleaving block output from the bit interleaver 215 and a demultiplexer 218 for demultiplexed bit output from the demultiplexer 217 (QAM mapper) 219 for mapping to a QAM symbol used to generate an OFDM symbol (cell).

The corresponding chain in the receiving device processes the received symbols to recover the L1-Post signaling bits.

Another possible preamble structure includes one symbol (e.g., an OFDM symbol) with a specific length (e.g., 8K) left for only L1-free and L1-post signaling. In this case, the coding and puncturing patterns used for L1-post signaling may vary and may, for example, be based on the length of the L1-post information (e.g., the number of L1-post information bits) . The coding rate and puncturing scheme can be applied to fill the entire single symbol for any length of the input data.

The operation of the bit interleaver 215 shown in FIG. 2 is shown in FIG. The bit interleaver 215 receives N _c Column and N _post / N _c Lt; RTI ID = 0.0 > interleaver. ≪ / RTI > As shown in FIG. 3, the bits are input in the bit interleaver 215 column direction to obtain the interleaved sequence, and are output from the bit interleaver 215 row direction. The value of N _c may vary and may, for example, be dependent on the modulation scheme and code rate used. For example, N _c = 8 using 16-QAM and a code rate of 1/2, and N _c = 12 using 64-QAM and a code rate of 1/2.

The structure shown in Figure 2 has a relatively simple advantage. However, this structure also has the disadvantage of having relatively poor performance in certain situations. For example, a 3 dB operation may cause a loss in certain situations.

Accordingly, a need exists for a method, apparatus, and system for bit interleaving and bit de-interleaving with improved performance while maintaining a relatively simple structure.

It is an object of the present invention to provide a method, an apparatus and a system for bit interleaving and bit de-interleaving with improved performance while maintaining a relatively simple structure.

에 매핑되도록 비트의 세트 a ≡{a_k: k= 0, 1, 2,...N_post-1}를 어레이 B={B_{i ,j}:i=0, 1, 2,...M-1; j=0, 1, 2,...N-1}에 매핑하는 단계, 여기서 상기 mod는 모듈로 연산자(modulo operator), 상기

는 플로어 연산자(floor operator), 상기 M과 상기 N은 정수이고, 다음 중 적어도 하나를 수행하는 단계, ㅇ 적어도 하나의 제1 비트의 그룹 내의 적어도 두 개의 비트를 치환하는 단계를 포함하는 제1 퍼뮤테이션(permutation) 동작, 여기서 각각의 제1 비트의 그룹은 G ⁽¹⁾ _p={B_{i ,p}: i=0, 1, 2,...M-1;p∈{0, 1, 2,...N-1}}로 정의되고, ㅇ 적어도 하나의 제2 비트의 그룹 내의 적어도 두 개의 비트를 퍼뮤팅하는 단계를 포함하는 제2 퍼뮤테이션(permutation) 동작, 여기서 각각의 제2 비트의 그룹은 G ⁽²⁾ _q={B_{q ,j}: j=0, 1, 2,...N-1;q∈{0, 1, 2,...M-1}}로 정의되며, 비트 B_{i ,j}가 b_{Ni +j}에 디-매핑되도록 인터리빙된 비트의 세트 b ≡{b_k: k= 0, 1, 2,...N_post-1}를 획득하기 위하여 B로부터 비트를 디-매핑하는 단계를 포함할 수 있다.The bit interleaving method according to an embodiment of the present invention for achieving the object described above is a _k-bit is

A set of bits to be mapped to _{a ≡ {a k: k =} 0, 1, 2, ... N post -1} to an array _{B = {B i, j:} i = 0, 1, 2, ... M -One; j = 0, 1, 2, ..., N-1}, where mod is a modulo operator,

(M) and the N is an integer, performing at least one of the following: replacing at least two bits in a group of at least one first bit, presentation (permutation) operation, in which groups of each of the first bit is _{^{G (1) p = {B}} i, p: i = 0, 1, 2, ... M-1; p∈ {0, 1, 2 , ... N-1}}, wherein permutation operation comprises permuting at least two bits in the group of at least one second bit, wherein each second bit 1, 2, ..., M-1}} is defined as G ⁽²⁾ _q = {B _{q , j} : j = 0,1,2 ... N- , the bit B _{i, j} is the _j b _{Ni +} D - of the mapped set of bits to be interleaved _{b ≡ {b k: k =} 0, 1, 2, ... N post -1} from the bits B to obtain And de-mapping the received signal.

Also, the at least one group of first bits may be a first group { G ⁽¹⁾ _p : p mod g = h; g? {1, 2, 3, ...; h? {0, 1, 2, ..., g-1}}.

And g = 2 and h = 0 or 1.

In addition, the first permutation operation comprises the step of substitution in position B _i, where the bits of _p B _{π1 (i), p,} wherein π ₁ (i) may include a first permutation function .

And? ₁ (i) = Mi-1.

Also, the second permutation operation may comprise replacing the bits of position B _{q , j} with a position B _{q ,} π ₂ (j), where π ₂ (j) may comprise a second permutation function .

Then, π ₂ (j) = (j + s (q)) mod N, where s (q) may include a shift function.

Also, s (q) = q or s (q) = q.

And wherein the mapping step includes writing the set a of bits in a column direction to a block interleaver consisting of M rows and N columns, wherein the first permutation operation is performed in at least two of the at least one column of the block interleaver Wherein the second permutation operation comprises replacing at least two bits in at least one row of the block interleaver, wherein the de-mapping step comprises: replacing the interleaved bits a set of b from the block interleaver may be a step to read in the row direction.

Also, the first permutation operation may include replacing bits in all gth columns.

And, the first permutation operation may include replacing bits in each odd column or each even column.

Also, the first permutation operation may include replacing bits in at least one column according to a first permutation function.

And, the first permutation function may comprise flipping the bits in at least one column backwards.

In addition, the second permutation operation may include replacing bits in at least one row according to a second permutation function.

And, the second permutation function may include shifting at least one row.

Also, the second permutation function may include shifting the p-th row by p in a specific direction.

The method may further include the step of selecting a value of N.

Further, the value of N may be selected based on the value of N _post .

If the value of N _post exceeds the threshold value, the value of N is selected as N _mod . If the value of N _post does not exceed the threshold value, the value of N is selected as N _mod / 2, N _mod may be related to the order of the demodulation scheme used to transmit the set of interleaved bits.

Further, the step of selecting the value of N is, by using a table that stores the information representing the value of the associated N and the range of the value of the value or N _post of N _post comprise a step of obtaining a value of the N .

The method may further include signaling the selected N value.

The method may further include selecting at least one of the first permutation operation and the second permutation operation and applying the selected bit to the bit interleaving method.

The method may further include signaling one of the first permutation operation and the second permutation operation applied to the bit interleaving method.

에 매핑되도록 비트의 세트 a ≡{a_k: k= 0, 1, 2,...N_post-1}를 어레이 B={B_{i ,j}:i=0, 1, 2,...M-1; j=0, 1, 2,...N-1}에 매핑하는 매퍼(mapper), 여기서 상기 mod는 모듈로 연산자(modulo operator), 상기

는 플로어 연산자(floor operator), 상기 M과 상기 N은 정수이고, 다음 중 적어도 하나를 수행하는 퍼뮤터(permuter), ㅇ 적어도 하나의 제1 비트의 그룹 내의 적어도 두 개의 비트를 치환하는 제1 퍼뮤테이션(permutation) 동작, 여기서 각각의 제1 비트의 그룹은 G ⁽¹⁾ _p={B_{i ,p}: i=0, 1, 2,...M-1;p∈{0, 1, 2,...N-1}}로 정의되고, ㅇ 적어도 하나의 제2 비트의 그룹 내의 적어도 두 개의 비트를 퍼뮤팅하는 제2 퍼뮤테이션(permutation) 동작, 여기서 각각의 제2 비트의 그룹은 G ⁽²⁾ _q={B_{q ,j}: j=0, 1, 2,...N-1;q∈{0, 1, 2,...M-1}}로 정의되며, 비트 B_{i ,j}가 b_{Ni +j}에 디-매핑되도록 인터리빙된 비트의 세트 b ≡{b_k: k= 0, 1, 2,...N_post-1}를 획득하기 위하여 B로부터 비트를 디-매핑하는 디-매퍼(de-mapper)를 포함할 수 있다.Bit interleaver in accordance with one embodiment of the present invention for achieving the object described above is a _k-bit is

A set of bits to be mapped to _{a ≡ {a k: k =} 0, 1, 2, ... N post -1} to an array _{B = {B i, j:} i = 0, 1, 2, ... M -One; a modulator operand, a modulo operator, a modulo operator, a modulo operator,

A permuter for performing at least one of the following: M and N being integers, a first permuter for replacing at least two bits in a group of at least one first bit, presentation (permutation) operation, in which groups of each of the first bit is _{^{G (1) p = {B}} i, p: i = 0, 1, 2, ... M-1; p∈ {0, 1, 2 , ... N-1}}, wherein a second permutation operation permuting at least two bits in the group of at least one second bit, wherein each second bit group is defined as G ^{_{(2) q = {B q}} , j: j = 0, 1, 2, ... N-1; q∈ {0, 1, 2, ... M-1}} is defined as, B _i bit _, de-mapped bits from B to obtain a set of interleaved bits b ≡ {b _k : k = 0, 1, 2, ... N _post -1} such that _j is de-mapped to b _{Ni +} And a de-mapper for performing a de-mapper operation.

Also, the at least one group of first bits may be a first group { G ⁽¹⁾ _p : p mod g = h; g? {1, 2, 3, ...; h? {0, 1, 2, ..., g-1}}.

And g = 2 and h = 0 or 1.

In addition, the first permutation operation is substituted in position B _i, where the bits of _p B _{π1 (i), p,} wherein π ₁ (i) may include a first permutation function.

And? ₁ (i) = Mi-1.

Further, the second permutation operation replaces the bits of the position B _{q , j} with the positions B _{q ,} π ₂ (j), where π ₂ (j) may comprise a second permutation function.

Then, π ₂ (j) = (j + s (q)) mod N, where s (q) may include a shift function.

Also, s (q) = q or s (q) = q.

And, the mapper, and write a set a of the bits in the column direction in M rows and N columns comprising a block interleaver, wherein the first permutation operation, and substituting at least two bits in the at least one column of the block interleaver, The second permutation operation replaces at least two bits in at least one row of the block interleaver and the de-mapper may read the interleaved set of bits b in the row direction from the block interleaver.

Also, the first permutation operation may replace bits in all gth columns.

And, the first permutation operation may replace bits in each odd column or each even column.

Also, the first permutation operation may replace bits in at least one column according to a first permutation function.

The first permutation function may flip bits in at least one column backwards.

Also, the second permutation operation may replace bits in at least one row according to a second permutation function.

The second permutation function may shift at least one row.

In addition, the second permutation function may shift the p-th row by p in a specific direction.

The controller may further include a controller for selecting a value of N.

Further, the value of N may be selected based on the value of N _post .

If the value of N _post exceeds the threshold value, the value of N is selected as N _mod . If the value of N _post does not exceed the threshold value, the value of N is selected as N _mod / 2, N _mod may be related to the order of the demodulation scheme used to transmit the set of interleaved bits.

Further, the control section, it is possible to use a table that stores the information representing the value of N associated with the value or range of values of the _post N _post of N to obtain a value of the N.

The control unit may signal the selected N value.

Also, the controller may select at least one of the first permutation operation and the second permutation operation to apply the bit interleaving method.

The control unit may signal one of the first permutation operation and the second permutation operation applied to the bit interleaving method.

로부터 디-매핑되도록 디-인터리빙된 비트의 세트 a ≡{a_k: k= 0, 1, 2,...N_post-1}를 획득하기 위하여 B로부터 비트를 디-매핑하는 단계, 여기서 상기 mod는 모듈로 연산자(modulo operator), 상기

는 플로어 연산자(floor operator)를 포함할 수 있다.The bit interleaving method according to an embodiment of the present invention for achieving the object as described above, the bit B _{i, j} is the bit b _{Ni +} set of bits to be mapped from a _{j b ≡ {b k: k} = 0, 1, 2, ..., N _post -1} with array B = {B _{i , j} : i = 0, 1, 2, ... M-1; j, where M and N are integers, performing at least one of the following: (i) at least one in the group of at least one first bit, A first permutation operation comprising substituting two bits, wherein the group of each first bit is G ⁽¹⁾ _p = {B _{i, p} : i = 0, 1, 2, ... M-1; p? {0,1,2, ..., N-1}, and permuting at least two bits in the group of at least one second bit, Wherein a group of each second bit is G ⁽²⁾ _q = {B _{q , j} : j = 0,1,2 ... N-1; 2, ... M-1}}, and the bit a _k is

De-mapped bits from B to obtain a set of de-interleaved bits a ≡ {a _k : k = 0, 1, 2, ..., N _post -1} to be de-mapped from B , mod is a modulo operator,

May include a floor operator.

로부터 디-매핑되도록 인터리빙된 비트의 세트 a ≡{a_k: k= 0, 1, 2,...N_post-1}를 획득하기 위하여 B로부터 비트를 디-매핑하는 디-매퍼(de-mapper), 여기서 상기 mod는 모듈로 연산자(modulo operator), 상기

는 플로어 연산자(floor operator)를 포함할 수 있다.Bit interleaver in accordance with one embodiment of the present invention for achieving the object as described above, the bit B _i, the set of bits that _j is mapped from the bit _{b Ni + j b ≡ {b} k: k = 0, 1, 2 , ... N _post- 1} are arranged in an array B = {B _{i , j} : i = 0, 1, 2, ... M-1; a permuter for mapping at least one of M and N to integers and performing at least one of the following: A first permutation operation for replacing at least two bits in a group of first bits, wherein each first group of bits is G ⁽¹⁾ _p = {B _{i, p} : i = 0, , ... M-1; p ∈ {0, 1, 2, ... N-1}}, and wherein the second permutation is defined as permitting at least two bits in the group of at least one second bit presentation (permutation) operation, in which groups of each of the second bit is _{^{G (2) q = {B}} q, j: j = 0, 1, 2, ... N-1; q∈ {0, 1, 2 , ... M-1}}, and the bit a _k is

To de-map bits from B to obtain a set of interleaved bits a ≡ {a _k : k = 0, 1, 2, ..., N _post -1} map, where mod is a modulo operator,

May include a floor operator.

1 shows a frame structure used in DVB-T2 for data transmission.
2 shows a BICM chain for processing a bitstream according to an embodiment of the present invention.
Fig. 3 shows the operation of the bit interleaver shown in Fig.
Figure 4 shows constellations for 64-QAM using a gray mapping scheme.
5 illustrates a functional structure of a bit interleaver according to an embodiment of the present invention.
6A to 6D show the operation of the bit interleaver shown in FIG.
7 illustrates a functional structure of a bit de-interleaver according to an embodiment of the present invention.
8 shows a system according to an embodiment of the present invention.
9A is a flowchart of a method for bit interleaving according to an embodiment of the present invention.
9B is a flowchart of a method for bit de-interleaving according to an embodiment of the present invention.

In the following, various embodiments of the present invention will be described in conjunction with the accompanying drawings, assisting an understanding of the invention as defined by the claims, and the claims of the present invention being defined by the claims. The detailed description includes specific details to facilitate understanding, but is provided by way of example only. Accordingly, one of ordinary skill in the art can make various modifications and variations of the embodiments without departing from the scope of the present invention.

The same or similar components will be denoted by the same or similar reference numerals even though they are shown in different drawings.

The detailed description of techniques, characteristics, elements, structures, configurations, functions, operations or processes known in the art may be omitted for clarity, simplicity and ambiguity with the present invention.

The terms and words used hereinafter are not intended to be limited to bibliographical or standard meanings and may be used to enable a clear and consistent understanding of the present invention.

Throughout the description and the claims of the present invention, the word "comprising," " including, " and " And is not intended to exclude at least one of the other features, elements, components, integers, steps, processes, operations, functions, characteristics, and attributes.

Throughout the description and claims of the present invention, it is to be understood that a feature, parameter or value quoted to mean " fairly "is not necessarily to be precise but is to be construed as being limited by the appended claims, Means that deviations or variations, including factors, can occur without eventually excluding the effect intended to provide the characteristic.

Throughout the description and claims of the present invention, the term "X for Y" (where Y is a particular operation, process, operation, function, action or step, and X is an operation, process, Means) comprise a specially adapted, constructed or arranged means X that is not essential but not exclusive to Y.

At least one of the features, elements, structures, integers, steps, processes, operations, functions, characteristics, and characteristics described and disclosed in connection with the specific aspects, embodiments, examples, or claims of the invention are not mutually exclusive, , Embodiments, examples, or claims.

Embodiments of the present invention provide various techniques (e.g., methods, apparatus, and systems) for at least one of bit interleaving and bit de-interleaving. Embodiments of the present invention may be implemented using at least one current and next generation digital broadcast system, e.g., a Digital Video Broadcasting (DVB) project and an Advanced Television Systems Committee (ATSC) (e.g., the ATSC 3.0 standard) System can be implemented within a digital broadcasting system. However, it will be appreciated by those of ordinary skill in the art that the present invention is not limited to being used in connection with any particular system or standard, and that various embodiments may be used for at least one of bit interleaving and bit de-interleaving, Technology in the future.

According to an embodiment of the present invention, the techniques described can be used to perform at least one of bit interleaving and bit de-interleaving of signaling data such as L1-post signaling or similar type signaling. It should be understood, however, that the present invention is not limited to the use of the present invention in connection with a particular type of data, and that various embodiments may employ techniques for at least one of bit interleaving and bit de-interleaving, I will admit to providing.

Moreover, the present invention is not limited to being used with a particular type of data structure or preamble structure. For example, when a preamble structure is used, a suitable type of preamble structure, including a single symbol or multi-symbol structure of a suitable type, may be used in an embodiment of the present invention.

Embodiments of the present invention may be implemented in the form of at least one of a suitable method, system, and apparatus for using digital broadcast. For example, embodiments of the present invention may be used in mobile / portable terminals (e.g., mobile telephones), hand-held devices, personal computers, digital television or digital radio broadcast transmission or reception devices, As shown in FIG. At least one of these methods, systems, and devices may be compatible with at least one of current or future digital broadcast systems and standards, e.g., the digital broadcast systems and standards described above.

Embodiments of the present invention may be implemented in the form of a system including a transmitting apparatus and a receiving apparatus. The transmitting apparatus can be implemented to perform bit interleaving (also, other necessary processing and encoding) of the data and to transmit the signal corresponding to the bit interleaved data to the receiving apparatus. The receiving device may be implemented to receive signals and perform bit de-interleaving (as well as other necessary processing and decoding). Embodiments of the present invention may include a transmission device, a receiving device, or a system including both.

As described above, the structure shown in Fig. 2 has a disadvantage in that it exhibits relatively low performance in a specific situation. One of the reasons is explained.

Figure 4 shows a constellation diagram for 64-QAM in which a 6-bit value is mapped to a respective constellation point according to a Gray mapping scheme. Using the mapping shown in FIG. 4, it can be seen that the two most significant bits (MSBs) of the 6-bit value (0 and 1 bit) determine which constellation point corresponds to which constellation quadrant . The next two MSBs (2 and 3 bits) determine the sub-quadrant of the quadrant where the corresponding constellation point will be located. Finally, the last two MSBs (4 and 5 bits) determine which constellation point of the four constellation points forming the sub-quadrant corresponds to the corresponding constellation point.

Thus, a change in one of the first two MSBs (0 and 1 bit) causes a relatively large change in the location of the corresponding sex store (e.g., a change in the quadrant). Conversely, a relatively large amount of noise is required to cause an error in one of these bits. In comparison, a change in one of the next two MSBs (2 and 3 bits) causes a smaller change in the location of the corresponding sex store (e.g., a change in the sub-quadrant of the quadrant), and conversely, A small amount of noise can cause errors in this bit. Finally, a change in one of the last two MSBs (4 and 5 bits) causes a relatively small change in the location of the corresponding gender store (e.g., a change in the gender of the sub-quadrant), and conversely, A relatively low degree of noise can cause errors in this bit.

The above principles also apply to other orders of QAM, e.g., 16-QAM, 64-QAM, 256-QAM ... , Or 2 ^2m -QAM (m = 2, 3, 4, ...).

Each bit of the n-bit value mapped to the 2 ^{< n >} -QAM constellation property point can be considered to pass through n 1-bit channels each. Each 1-bit channel may tolerate noise to a different degree, e.g., for the reasons stated above, the error rate and thus the channel capacity according to a given level of noise may be different per channel (e.g., per bit) . In particular, the channel capacity for a channel corresponding to a less significant bit is generally smaller than for a channel corresponding to a more significant bit. For example, for a particular modulation scheme, such as 2 ^2m -QAM, the channel pair may have the same or similar channel capacity, for example, bits {0,1}, {2, 3} and {4, 5}.

Referring again to FIG. 3, the bits mapped to a single store are generally output from the same row of the bit interleaver 215 (e.g., the bits indicated by dashed lines in FIG. 3). For example, in the case of the 256-QAM and 8-column bit interleaver shown in FIG. 3, the 8 bits output from one row of the bit interleaver 215 are generally mapped to one 256-QAM static store. This means that the bits located in the same column are transmitted on the same 1-bit channel. In addition, since the bits are input to the bit interleaver 215 in the column direction, many consecutive bits of the input bit stream will occupy the same row. Thus, many consecutive bits of the input bitstream will all be transmitted on the same channel. This causes many consecutive bits to be transmitted over the channel with insufficient capacity, which is undesirable.

An embodiment of the present invention provides a bit interleaver that can avoid or mitigate the above-described problems, thereby improving performance while maintaining a relatively simple structure.

5 illustrates a functional structure of a bit interleaver according to an embodiment of the present invention. 6A to 6D show the operation of the bit interleaver shown in FIG. According to an embodiment of the present invention, the bit interleaver may form part of a BICM chain, for example the BICM chain shown in FIG. A system according to an embodiment of the present invention, including the bit interleaver 500 shown in FIG. 5, is shown in FIG. The method according to one embodiment of the present invention performed by the bit interleaver 500 shown in FIG. 5 is shown in FIG. 9A.

In the following embodiment, the bit interleaver is described as a block interleaver. However, the embodiment of the present invention is not limited to being implemented in the form of a block interleaver. For example, in accordance with one embodiment of the present invention, a bit interleaver may be provided in another form for performing bit interleaving according to the same overall interleaving pattern as applied by the block interleaver described herein. In addition, the rows and columns of the described bit interleaver and the operations performed thereby may be modified to other embodiments.

According to one embodiment of the present invention, the input bit sequence is first written to the block interleaver in the first direction (e.g., column direction). Next, one or more columns (e.g., odd columns) of the bit interleaver are replaced according to one or more first permutation patterns (e.g., the columns are inverted), and one or more rows of the bit interleaver are replaced by one (E.g., the rows are periodically shifted) over the first permutation pattern. Finally, the output bit sequence is generated by reading the bits from the bit interleaver in the second direction (e.g., the row direction).

5, the bit interleaver 500 in the transmission apparatus includes an interleaver array 501, a mapper 503, a column permuter 505, (Row permuter) 507 and a de-mapper 509. The R- The bit interleaver 500 further includes a controller 511 for controlling the interleaver array 501, the mapper 503, the thermal permuter 505, the hopper mutator 507 and the de-mapper 509 .

According to an embodiment, the thermal permuter 505 and the passive masker 507 are separated, but according to another embodiment, the thermal passive mute 505 and the passive mute 507 are implemented as one permuter block .

In addition, one embodiment of the present invention is not limited to the configuration shown in Fig. For example, according to another embodiment, the bit interleaver may be implemented in a chain structure such that the bit sequences may be sequentially passed through the various blocks in the chain to perform the operations of each mapping, thermal permutation, hopper muting and de- As shown in FIG.

In addition, the arrays of the present invention are not limited to physical arrays, but may refer to mathematical arrays. That is, for example, two variables can be defined for the purpose of defining the permutation operation more clearly or comfortably. However, according to the embodiment, the same permutation operation as the permutation operation described in the present invention (e.g., generating the same output for a given specific input) can be applied to bits stored or processed in only one way have.

이고, mod는 모듈로 연산자(modulo operator),

는 플로어 연산자(floor operator)를 나타낸다. 이러한 매핑은 도 6a에 도시되어 있다.The interleaver array 501 is composed of M rows and N columns, thus forming an M x N array of cells, and the i-th row and the j-th column (i = 0, 1, 2, ...) of the array. , M-1, and j = 0, 1, 2, ..., N-1) may be represented by B _{i , j} . The mapper 503 receives the input bit sequence {a _k } (k = 0, 1, 2, ...) and maps the bits of the input bit sequence to the cells of the interleaver array 501. For example, the mapper 503 writes the input bit sequence {a _k } in the column direction of the interleaver array 501 so that bit a _k is mapped to cell B _{i , j} , where i = k mod M and

Mod is a modulo operator,

Represents a floor operator. This mapping is shown in FIG. 6A.

The thermal permuter 505 is configured to replace a plurality of cells of one or more columns of the interleaver array 501 according to one or more permutation patterns. For example, the thermal permuter 505 may be configured to replace a set of columns {j} with all pth columns, e.g., j mod p = q, where p = 1, 2, 3,. ..., and q = 0, 1, 2, ..., p-1 are fixed values. In one embodiment of the present invention, the column permuter 505 is configured to replace a set of columns {j} with an odd number of columns, e.g., j mod 2 = 1. A permuting cell in the pth column (p = 0, 1, 2, ..., N-1) can be regarded as a permuting cell in a cell group denoted G ⁽¹⁾ _p = {B _{i ,} Where i = 0, 1, 2, ..., M-1.

The thermal permuter 505 may replace some or all of the columns using the same permutation pattern or other permutation pattern. In the embodiment of the present invention, the odd-numbered columns are respectively replaced by the same permutation pattern.

The thermal permuter 505 may substitute heat using an appropriate permutation pattern. For example, where B _{i, j} of the bit may be substituted in position B _{π1 (i), j, 1,} where π (i) represents the first permutation function. For example, in an embodiment of the invention shown in Figure 6b for the heat permuter 505 position B _i, new position after the bits of _j are the column permutation before the column permutation B _{'i, j} = B _{M -} th row of the interleaver array 501 such that, for example, π ₁ (i) = Mi-1 so as to be replaced with _{i-1, j} .

The cells that make up the column may be replaced by any other suitable method. For example, the cells that make up a column can be replaced semi-randomly. As another example, a column can be divided into two or more sub-columns (e. G., The same) and cells in each sub-column can be assigned a specific permutation pattern (e. G., By flipping each sub- Lt; / RTI > may be independently substituted.

The farrmuter 507 is configured to replace a plurality of cells of one or more rows of the interleaver array 501 according to one or more permutation patterns. For example, where B _{i, j} of the bit may be substituted in position B _{i, π2 (j),} where π ₂ (j) represents a second permutation function. A permuting cell in the qth column (q = 0, 1, 2, ..., M-1) can be regarded as a permuting cell in a cell group denoted G ⁽²⁾ _q = {B _q, Where j = 0, 1, 2, ..., N-1. The passive mutator 507 may substitute some or all of the rows using the same permutation pattern or another permutation pattern.

According to an embodiment of the present invention, the permutation pattern may include a shift. For example, the thermal permuter 507 may be configured to shift all cells of a particular column to a specific number of cells in a particular direction. In the embodiment of the invention shown in FIG. 6C, the rows are rotated in such a way that one row is not shifted, the next row is shifted right by one cell, and the next row is shifted right by two cells Shifted. More generally, when shifting is used as a permutation pattern, the path mutator 507 determines whether the bits of the position B _{i , j} before the row permutation are in the new positions B ' _{i , j} = B _{i , + s (i)) modN (e.g., p 2 (j) = (} j + s (i)) being arranged to shift a line able to be substituted on mod N), where, s (i) is the line Represents the number of shifts defined as a function of the variable i (e.g., in units of cells). For example, according to the embodiment, s (i) = i. According to another example, the number of shifts can be defined in other ways, for example s (i) = 2i or s (i) = - i.

By applying the column or row permutation to the interleaver array 501 as described above, the performance can be improved. For example, by replacing the other rows of the interleaver array 501 using different permutation patterns (for example, by replacing the other rows of the interleaver array 501 by a different number) It can be seen that successive bits of the original input bit sequence {a _k } to be read into the column tend to diffuse to other columns following the permutation of the rows. As a result, when the bit output from the bit interleaver 500 is mapped to the store point, successive bits of the input bit sequence {a _k } tend to occupy different bit positions. Thus, successive bits tend to be transmitted over a 1-bit channel with different channel capacity, thereby reducing the likelihood that consecutive bits will be transmitted over a channel with a relatively low channel capacity.

In addition, by replacing a specific column of the interleaver array 501 (for example, by inverting an odd column), the performance is improved, for example, for the following reasons.

When the rows of the interleaver array 501 are shifted without replacing the columns of the interleaver array 501, as shown in FIG. 6D, after the rows are shifted, the bit values of the specific column are shifted to the original bit sequence {a _k } And a relatively large number of pairs of values corresponding to the value of position N-1 apart from each other. Further, after the row are shifted, a peripheral column bit value of the original bit sequence {a _k} relative to values of a larger number corresponding to the successive values of the original bit sequence _{{a k} N, N-} 2 by And a pair of many values corresponding to the values of the distant positions.

For the reasons stated above, bits occupying the same column can be transmitted over the same 1-bit channel with a certain channel capacity. In addition, for the reasons stated above, the bits occupying the surrounding rows in certain cases may be transmitted over another 1-bit channel having the same or similar channel capacity. Thus, data generated in the original bit sequence {a _k } that repeats with a certain period (e.g., period N) tends to be transmitted over another 1-bit channel having the same or similar channel capacity. This results in data being transmitted over a channel having a relatively low channel capacity, which is undesirable.

However, by substituting certain columns, for example as shown in FIG. 6C, the bit values of the particular column and the bit values of the neighboring columns may have a smaller number of values corresponding to adjacent values in the original bit sequence {a _k } Pair and a smaller number of pairs of values corresponding to values at locations separated by N, N-1, N-2 in the original bit sequence {a _k }. Thus, the periodic data occurring in the original bit sequence {a _k } is unlikely to be transmitted over a channel having the same or similar bit capacity, and such data is transmitted over a channel having a relatively low channel capacity . As can be seen by comparing FIGS. 6C and 6D, in the case of FIG. 6D in which the columns are not replaced, a pair of more values corresponding to the value at a position N apart from the original bit sequence {a _k } Lt; / RTI > transmitted in a channel having the same or similar channel capacity.

The de-mapper 509 is configured to de-map the bits from the interleaver array to produce an output interleaved bit sequence {b _k }. For example, de-mapper 509 may be configured to read bits from interleaver array 501 in the row direction such that bits b _k of the output bit sequence are de-mapped from cell B _{i , j} of interleaver array 501 Where k = Ni + j.

The thermal permuter 505 and the passive mutator 507 may be configured to operate in the interleaver array 501 in a particular order. For example, in one embodiment, the column permuter 505 may replace the columns of the worker array 501 before the worker mute 507 replaces the rows of the interleaver array 501. Alternatively, the incidental mutator 507 may replace the rows of the interleaver array 501 before the thermal permuter 505 replaces the columns of the interleaver array 501. According to one embodiment, the order of operations on the interleaver array 501 of the thermal permuter 505 and the path mutator 507 can be controlled, for example, by the control unit 511. [

A specific example of bit interleaving according to an embodiment of the present invention will be described below. According to an embodiment, the input data has a length of L-I, and the number of columns is C. A matrix of sizes (R (row), C (column)) is defined, where R = ceil (L-1 / C). The first matrix output M is defined as M (r, c) = input (c * R + (r-1)). One example of the first matrix output is shown in Figure 6a. The second matrix A is computed according to A (r, c) = M ((R-r) mod R, c) from M and (c mod 2 ≠ 0). One example of a second matrix output is shown in FIG. 6B. The third matrix B is computed from A to B (r, c) = A (r, (c + r) mod C). An example of a third matrix output is shown in Figure 6c.

According to one embodiment, only one of the column permuter 505 and the pass through mutator 507 may be provided, so that only one of the columns and rows may be replaced. According to another embodiment, both the thermal permuter 505 and the passive mutator 507 may be provided and at least one of the thermal permuter 505 and the passive mutator 507 may be selectively activated or deactivated . This configuration includes a bit interleaver (i) a mode in which only rows are replaced, (ii) a mode in which only columns are replaced, (iii) a mode in which both rows and columns are replaced, and (iv) To operate in a number of different modes. A specific mode may be selected by the control unit 501, for example, in accordance with an appropriate condition or criterion. For example, according to one embodiment, the mode may be selected based on the length of the bit sequence {a _k }, and may be denoted as N _post .

The bit interleaver 500 may be configured such that the number N of columns used during operation of the interleaver array 501 is varied. For example, the mapper 503 and the de-mapper 509 may be configured to map and de-map bits from a particular number of columns or columns of the interleaver array 501, Or some of the available columns.

The number of columns N used during operation of the interleaver array 501 may be selected, for example, by the control unit 511 according to appropriate conditions or criteria. For example, according to one embodiment, the number of columns may be selected based on the length N _post of the bit sequence {a _k }. For example, if the value of N _post is relatively large, the number of columns may be the same as the number of bits to be mapped to each sex shops (e.g., represented by the N _mod 2 in ^Nmod -QAM), N _post If a relatively small value, the number of columns may be equal to half the number of bits to be mapped to each sex shops (e.g., represented by the _mod N / 2 eseo 2 ^Nmod -QAM). According to a particular embodiment, the number of columns may be independent of the N _post value in the order of the particular sex store. For example, the number of columns in 16-QAM (N _mod = 4) may be equal to N _mod (= 4) for all values of N _post .

As described above, heat permuter 505 and row selective activation and deactivation of the permuter 507, and the interleaver array can be selected for their heat to be used during operation of the unit 501 is at least in part, a bit sequence {a _{k} Lt;} / RTI > may be performed based on the length _Npost of the data _stream . In one embodiment, the bit interleaver 500 is enabled to activate and deactivate at least one of the appropriate preferences (e.g., at least one of the column permuter 505 and the hangper mutator 507) according to each value of N _post , The number of columns of the array 501). According to one embodiment, the same preference is set for N _post Values, in which case the table may be simplified by storing preferences in the range of each value rather than individual values. According to another embodiment, a suitable configuration may be used, for example, a field indicating a pair of activation flags corresponding to the column permuter 505 and the path mutator 507, respectively, and the number of columns of the interleaver array 501 may be transmitted from the transmitting apparatus to the receiving apparatus by using the feild.

The receiving apparatus is provided with a bit de-interleaver corresponding to a bit interleaver of the transmitting apparatus. The bit de-interleaver is configured to de-interleave the bit sequence generated by demodulating the received symbol stream. 7 illustrates a functional structure of a bit de-interleaver according to an embodiment of the present invention. A system according to an embodiment of the present invention including the bit de-interleaver 700 of FIG. 7 is shown in FIG. A method according to an embodiment of the present invention performed by the bit de-interleaver 700 of FIG. 5 is shown in FIG. 9b.

7, the bit de-interleaver 700 includes a de-interleaver array 701, a mapper 703, a column permuter 705, (Row permuter) 707 and a de-mapper 709. The bit de-interleaver 700 further includes a controller 701 for controlling the de-interleaver array 701, the mapper 703, the thermal permuter 705, the hopper mutator 707, ) ≪ / RTI >

The de-interleaver array 701 has a shape similar to the interleaver array 501 of the transmission apparatus and also includes M rows and N columns forming an M x N array of cells. The mapper 703 performs the reverse operation of the operation performed by the de-mapper 509 of the transmission apparatus. For example, the mapper 703 records the bit sequence b _k in the row direction of the de-interleaver array 701.

The thermal permuter 705 is configured to perform a reverse operation of the operation performed by the thermal permuter 505 of the transfer device. For example, the thermal permuter 705 is configured to replace cells of at least one row of the de-interleaver array 701 according to at least one permutation pattern, wherein the permuter 705 used by the thermal permuter 705 The transfer pattern is the inverse of the permutation pattern used by the thermal permuter 505 of the transfer device. For example, if the transfer permuter 505 of the transfer device flips the odd columns, the thermal permuter 705 of the receiver can flip the odd columns.

Similarly, the path mutator 707 is configured to perform the reverse operation of the operation performed by the path former's mutator 507 of the transmitting apparatus. For example, the path mutator 707 is configured to replace cells of at least one column of the de-interleaver array 701 according to at least one permutation pattern, wherein the permuter The transfer pattern is the inverse of the permutation pattern used by the transfer function of transfer device 507. For example, if the transfer function of transfer device 507 shifts a row by cycle, the transfer function of transfer device 707 is shifted in a direction opposite to the cyclic shift performed by transfer function of transfer device 507 As shown in FIG.

The thermal permuter 705 and the passive masker 707 of the receiving device operate on the de-interleaver array 701 as opposed to the thermal permuter 505 and the passive mutator 507 of the transmission device.

The de-mapper 709 performs the reverse operation of the operation performed by the mapper 503 of the transmission apparatus. For example, the de-mapper 709 reads the bit sequence a _k in the column direction from the de-interleaver array 701 to obtain the de-interleaver bit sequence.

Interleaver array 701 may be configured to selectively activate or deactivate a particular number of pulses of a particular number of pulses, such as, for example, And may be configured to operate using columns. For example, the preferences for configuring the thermal permuter 705, the path mutator 707 and the de-interleaver array 701 may be determined using a table according to the method described above, .

Meanwhile, a non-transitory computer readable medium may be provided in which a program for sequentially performing a method for interleaving and de-interleaving according to the present invention is stored.

A non-transitory readable medium is a medium that stores data for a short period of time, such as a register, cache, memory, etc., but semi-permanently stores data and is readable by the apparatus. In particular, the various applications or programs described above may be stored on non-volatile readable media such as CD, DVD, hard disk, Blu-ray disk, USB, memory card, ROM,

In addition, although a bus is not shown in the above-described block diagram of the apparatus, the communication between the respective elements in the electronic apparatus may be performed via the bus. Further, each device may further include a processor such as a CPU, a microprocessor, or the like that performs the various steps described above.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention.

500: bit interleaver 501: interleaver array
503: Mapper 505: Thermal multiplier
507: Hang Pufferer 509: D-Mapper
511: control unit 700: bit de-interleaver
701: De-interleaver array 703: Mapper
705: thermal fuse 707:
709: D-mapper 711: Control section

Claims (20)

Bit a _k

A set of bits to be mapped to _{a ≡ {a k: k =} 0, 1, 2, ... N post -1} to an array _{B = {B i, j:} i = 0, 1, 2, ... M -One; j = 0, 1, 2, ..., N-1}, where mod is a modulo operator,

Is a floor operator, where M and N are integers;
Performing at least one of the following:
A first permutation operation comprising replacing at least two bits in a group of at least one first bit, wherein each group of first bits is G ⁽¹⁾ _p = {B _{i , p} : i = 0, 1, 2, ... M-1; p? {0,1,2 ... N-1}
A second permutation operation comprising permuting at least two bits in a group of at least one second bit, wherein each second group of bits is G ⁽²⁾ _q = {B _{q , j} = 0, 1, 2, ..., N-1; q? {0,1,2 ... M-
Bit B _{i, j} is the _j b _{Ni +} D - a set of interleaved bits to map ≡ b: to obtain a _{{b k k = 0, 1} , 2, ... N post -1} from the bits to B And de-mapping the bit-interleaved bits. The method according to claim 1,
Wherein the group of at least one first bit comprises a first group { G ⁽¹⁾ _p : p mod g = h; g? {1, 2, 3, ...; is a set of h? {0, 1, 2, ..., g-1}}. 3. The method of claim 2,
wherein g = 2 and h = 0 or 1. 4. The method according to any one of claims 1 to 3,
The first permutation operation is located B _i, the bit position of _{π1 p} B _(i), and comprising a _{p-substituted,} wherein π ₁ (i) comprises a first permutation function,
₁ < / RTI _> (i) = Mi-1. 4. The method according to any one of claims 1 to 3,
Characterized in that the second permutation operation comprises the step of replacing the bits of the position B _{q , j} with the positions B _{q , 2} (j), where π ₂ (j) comprises a second permutation function Bit interleaving method. 6. The method of claim 5,
and _{π 2 (j) = (j} + s (q)) mod N, where and s (q) comprises a shift (shift) function,
s (q) = q or s (q) = q. The method according to claim 1,
Wherein the mapping step comprises writing the set a of bits in a column direction to a block interleaver consisting of M rows and N columns,
Wherein the first permutation operation comprises replacing at least two bits in at least one column of the block interleaver,
Wherein the second permutation operation comprises replacing at least two bits in at least one row of the block interleaver,
Wherein the de-mapping comprises reading the interleaved set of bits b in the row direction from the block interleaver. 8. The method of claim 7,
Wherein the first permutation operation includes replacing bits in all gth columns. 9. The method of claim 8,
Wherein the first permutation operation comprises replacing bits in each odd column or each even column with each other. 10. The method according to any one of claims 7 to 9,
Wherein the first permutation operation includes replacing bits in at least one column according to a first permutation function. 11. The method of claim 10,
Wherein the first permutation function flips the bits in at least one column backwards. 10. The method according to any one of claims 7 to 9,
Wherein the second permutation operation comprises replacing bits in at least one row according to a second permutation function. 13. The method of claim 12,
And the second permutation function shifting at least one row. ≪ Desc / Clms Page number 22 > 14. The method of claim 13,
And the second permutation function shifting the pth row by p in a specific direction. 4. The method according to any one of claims 1 to 3,
Selecting a value of N,
And the value of N is selected based on the value of N _post . 16. The method of claim 15,
If the value of said N _post exceeds the threshold value of said N is selected as a _mod N, the value of said N _post does not exceed the threshold value of said N is selected as a _mod N / 2,
_Wherein the N _mod relates to a degree of a demodulation scheme used to transmit a set of interleaved bits. 16. The method of claim 15,
By including; the method comprising selecting a value of N is, by using a table that stores the information representing the value of the associated N and the range of the value of the value or N _post of N _post obtaining a value of the N Bit interleaving method. 4. The method according to any one of claims 1 to 3,
Further comprising: selecting at least one of the first permutation operation and the second permutation operation and applying the bit interleaving method to the bit interleaving method. 4. The method according to any one of claims 1 to 3,
Further comprising: signaling one of the first permutation operation and the second permutation operation applied to the bit interleaving method. Bit a _k

A set of bits to be mapped to _{a ≡ {a k: k =} 0, 1, 2, ... N post -1} to an array _{B = {B i, j:} i = 0, 1, 2, ... M -One; a modulator operand, a modulo operator, a modulo operator, a modulo operator,

Is a floor operator, where M and N are integers;
A permuter for performing at least one of:
A first permutation operation for replacing at least two bits in a group of at least one first bit, wherein each group of first bits is G ⁽¹⁾ _p = {B _{i , p} : i = 0 1, 2, ... M-1; p? {0, 1, 2, ... N-1}
A second permutation operation for permuting at least two bits in a group of at least one second bit, wherein each second group of bits is G ⁽²⁾ _q = {B _{q , j} : j = 0, 1, 2, ... N-1; q? {0, 1, 2, ... M-
Bit B _{i, j} is the _j b _{Ni +} D - a set of interleaved bits to map ≡ b: to obtain a _{{b k k = 0, 1} , 2, ... N post -1} from the bits to B De-mapped de-mappers.

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