KR20150032454A - transmitter apparatus and zero bits padding method thereof - Google Patents

Abstract

The present invention relates to a transmitting apparatus and to a zero bit padding method thereof. The transmitting apparatus includes: a zero padding unit which generates an information language by padding a zero bit to L1 post signaling; and an encoding unit which encodes the information language, wherein the zero padding unit divides the information language into a plurality of groups, pads the zero bit in a plurality of groups by group, and pads the additional zero bit from a front end or a rear end of the groups according to a predetermined standard.

Description

[0001] TRANSMITTER APPARATUS AND ZERO BITS PADDING METHOD THEREOF [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission apparatus and a zero bit padding method thereof, and more particularly, to a transmission apparatus that processes and transmits L1 post signaling and a zero bit padding method thereof.

In the information society of the 21st century, broadcasting and communication services are in the era of full-scale digitalization, multi-channelization, broadband and high-quality. Particularly, as the spread of high-definition digital TV, PMP, and mobile broadcasting equipment has expanded in recent years, demands for supporting various receiving methods of digital broadcasting services are also increasing.

In response to these demands, the standard group sets various standards and provides various services that satisfy the needs of the users. Accordingly, there is a need to search for ways to provide better services to users through better performance.

It is an object of the present invention to provide a transmission apparatus and a zero bit padding method therefor, which can improve performance by padding zero bits to L1 post signaling with a simpler operation.

According to an aspect of the present invention, there is provided a transmission apparatus including a zero padding unit for generating an information word by padding a zero bit to the L1 post signaling and an encoding unit for encoding the information word, The zero padding unit divides the information word into a plurality of groups, padding the plurality of groups with zero bits in group units, and padding additional zero bits from the front end or the rear end of one of the plurality of groups according to a predetermined reference.

Here, the zero padding unit may calculate the number of groups constituting the information word based on the number of bits of the information word, and may divide the information word into a plurality of groups based on the calculated number.

The zero padding unit may calculate the number of groups of zero bits to be padded based on the number of groups constituting the information word or the number of zero bits to be padded.

If the number of bits constituting the L1 post signaling is less than or equal to the number of bits included in one of the plurality of groups, the zero padding unit may calculate the number of groups of zero bits padded based on Equation (6) Can be calculated.

In addition, when the number of bits constituting the L1 post signaling exceeds the number of bits included in one of the plurality of groups, the zero padding unit calculates the number of bits of the group of zero bits padded based on Equation (7) It is possible to calculate the number.

The zero padding unit may determine a position of a group to which the zero bit is padded among the plurality of groups based on a predetermined shortening pattern, and may padd the zero bits at the determined position in a group unit.

Here, the predetermined shortening pattern to and is defined as follows: Table 4, the zero-padding unit when the number of groups of zero bits to be the padding of N _pad, of the plurality of group π _s (0) th group , π _s (1) th group, ..., π _s (N _pad -1) th groups.

In the case of the zero padding portion is the N _pad satisfies a first predetermined condition, and determines on the basis of the table in the group is added zero bits above the π _s (N _pad) th group padding, the π _s ( N _pad) may be padded with additional zero bits from the rear end of the second group in sequence.

The first predetermined condition may be N _pad = N _gruop- 1 when the number of groups constituting the information word is N _gruop .

In addition, the number of additional zero bits may be 360-K _sig when the number of bits included in one of the plurality of groups is 360 and the number of bits constituting the L1 post signaling is _Ksig .

On the other hand, if the zero padding portion is the N _pad satisfies a second predetermined condition, determining the group based on the table is π _s (N _pad) the second group an additional zero bits the padding, and the π _s ( N _pad) may be padded with additional zero bits from the rear end of the second group in sequence.

Here, if the number of groups constituting the information word is N _gruop , the second preset condition may be such that N _pad <N _gruop- 1 where? (N _pad ) is smaller than a predetermined value.

The number of additional zero bits may be set such that the number of bits constituting the information word is K _bch and the number of bits constituting the L1 post signaling is K _sig and the number of bits included in one of the plurality of groups is 360 , It can be K _bch- K _sig -360 x N _pad .

On the other hand, if the N _pad does not satisfy the first predetermined condition and the second predetermined condition, the zero padding unit _{pads the} group of? _S (N _pad ) based on the table with the additional zero bit Group, and further zero bits can be padded sequentially from the front end of the group of? _S (N _pad ).

Here, the number of bits wherein the additional agent, the number of bits constituting the information word K _bch is the number of bits constituting the L1 post-signaling K _sig is the number of bits included in one of said plurality of groups 360, it may be K _bch- K _sig -360 x N _pad .

The zero padding unit may generate the information word by sequentially mapping the L1 post signaling to a position where the zero bit is not padded in the information word.

Meanwhile, a zero bit padding method according to an embodiment of the present invention includes a step of generating an information word by padding a zero bit to the L1 post signaling and a step of encoding the information word, Grouping the groups into a plurality of groups, padding the plurality of groups with zero bits in group units, and padding additional zero bits from the front end or the rear end of one of the plurality of groups according to a predetermined reference.

Here, the generating step may calculate the number of groups constituting the information word based on the number of bits of the information word, and may divide the information word into a plurality of groups based on the calculated number.

Also, the generating step may calculate the number of groups of zero bits to be padded based on the number of groups constituting the information word or the number of zero bits padded.

If the number of bits constituting the L1 post signaling is equal to or less than the number of bits included in one of the plurality of groups, the generating step may include calculating the number of groups of the zero bit padding Can be calculated.

If the number of bits constituting the L1 post signaling exceeds the number of bits included in one of the plurality of groups, the generating step may include: Can be calculated.

Meanwhile, the generating step may determine a position of a group to which the zero bit is padded among the plurality of groups based on a predetermined shortening pattern, and may padd the group of zero bits at the determined position.

Herein, the predetermined shortening pattern is defined as shown in Table 4 below, and when the number of groups of the zero bit padded is N _pads , π _s (0) of the plurality of groups, Th group, the? _S (1) th group,? _S (N _pad -1), and the zeroth bit in the group unit.

In addition, the generating step that is and the N _pad is determined in a first group if they meet the predetermined condition, based on said table π _s (N _pad) th group of the bits are padded said additional agent group, the π _s It is possible to sequentially _{pad the} additional zero bits from the rear end of the (N _pad ) th group.

The first predetermined condition may be N _pad = N _gruop- 1 when the number of groups constituting the information word is N _gruop .

In addition, the number of additional zero bits may be 360-K _sig when the number of bits included in one of the plurality of groups is 360 and the number of bits constituting the L1 post signaling is _Ksig .

On the other hand, the method comprising the generation is the N _pad is determined in the second phase if they meet the predetermined condition, the group on the basis of the table in which π _s (N _pad) the second group an additional zero bits the padding, and the π _s It is possible to sequentially _{pad the} additional zero bits from the rear end of the (N _pad ) th group.

Here, if the number of groups constituting the information word is N _gruop , the second preset condition may be such that N _pad <N _gruop- 1 where? (N _pad ) is smaller than a predetermined value.

The number of additional zero bits may be set such that the number of bits constituting the information word is K _bch and the number of bits constituting the L1 post signaling is K _sig and the number of bits included in one of the plurality of groups is 360 , It can be K _bch- K _sig -360 x N _pad .

If the N _pad does not satisfy the first predetermined condition and the second predetermined condition, the generating step may include adding the group of? _S (N _pad ) (N _pad ) group from the _preceding stage of the? _S (N _pad ) th group.

Here, the number of bits wherein the additional agent, the number of bits constituting the information word K _bch is the number of bits constituting the L1 post-signaling K _sig is the number of bits included in one of said plurality of groups 360, it may be K _bch- K _sig -360 x N _pad .

Meanwhile, the generating step may generate the information word by sequentially mapping the L1 post signaling to a position where the zero bit is not padded in the information word.

According to various embodiments of the present invention as described above, the additional zero bits can be padded from the front end or the rear end of one of the plurality of groups constituting the information word. Accordingly, the L1 post-signaling bits are continuously located from the non-padded bits to the next group of additional zero bits of the group to which the additional zero bits are padded, or the additional zero bits are padded from the previous group of the group to which the additional zero bits are padded The additional zero bits of the group can be consecutively located up to the non-padded bits. Thus, the information word can be located in the L1 post signaling with a simpler operation.

1 is a diagram for explaining a frame structure used in a general broadcast / communication system,
2 is a block diagram illustrating a configuration of a transmitting apparatus according to an embodiment of the present invention.
3 is a block diagram illustrating a detailed configuration of an encoding unit according to an embodiment of the present invention;
4 is a diagram illustrating a structure of a parity check matrix according to an embodiment of the present invention.
5 is a view for explaining a plurality of groups of information words according to an embodiment of the present invention;
FIGS. 6 to 8 illustrate a method for generating an information word according to an embodiment of the present invention,
9 is a block diagram illustrating a detailed configuration of a transmitting apparatus according to an embodiment of the present invention.
FIG. 10 is a diagram for explaining a shortening operation according to an embodiment of the present invention, and FIG. 11 is a block diagram for explaining a configuration of a transmitting apparatus according to another embodiment of the present invention.
12 is a block diagram illustrating a detailed configuration of a transmitting apparatus according to another embodiment of the present invention;
13 is a block diagram illustrating a configuration of a receiving apparatus according to an embodiment of the present invention.
14 is a block diagram for explaining a detailed configuration of a decoding unit according to an embodiment of the present invention;
15 is a block diagram illustrating a detailed configuration of a receiving apparatus according to an embodiment of the present invention, and Fig.
16 is a flowchart illustrating a zero bit padding method of a transmitting apparatus according to an embodiment of the present invention.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a diagram for explaining a frame structure used in a general broadcast / communication system. Referring to FIG. 1, a frame 100 includes a preamble 110 and a data symbol 120.

The preamble 110 is a portion in which the L1 signal is transmitted and includes an L1 pre-signaling 111 (i.e., L1 pre-signaling information) and an L1 post signaling 112 (i.e., L1 post signaling information) Lt; / RTI &gt;

Herein, the L1 pre-signaling 111 includes information necessary for a receiving apparatus (not shown) to access the L1 post signaling 112, and the L1 post signaling 112 is used when the receiving apparatus (not shown) It contains necessary information.

The data symbol 120 is a portion through which actual broadcast data is transmitted, and may be composed of one or more physical layer pipes (PLPs). In this case, different signal processing can be independently performed for each PLP. For example, different modulation schemes and code rates may be used for each PLP.

In this way, in a general broadcast / communication system, a transmitter transmits broadcast data in a frame structure as shown in FIG. 1, and a receiver obtains information on a method of transmitting data, a frame length, and the like through L1 signaling, Reception.

The present invention relates to a method for processing L1 post signaling during L1 signaling and will be described in detail below. In the following description, code lengths of code words, information words, parity bits, and L1 signaling mean the number of bits included in each of them.

2 is a block diagram illustrating a configuration of a transmitting apparatus according to an embodiment of the present invention. Referring to FIG. 2, the transmission apparatus 200 includes a zero padding unit 210 and an encoding unit 220.

The zero padding unit 210 generates an information word by padding a zero bit (or a zero padding bit) to the L1 post signaling. The zero padding unit 210 outputs the information word to the encoding unit 220.

Here, the L1 post signaling may be configured with a smaller number of bits than the information words that can be encoded by the encoding unit 220. [ However, the number of bits constituting the L1 post signaling, that is, the length of the L1 post signaling, may be variable.

Specifically, the encoding unit 220 performs encoding in the order of a BCH (Bose, Chaudhuri, Hocquenghem) code and an LDPC (Low Density Parity Check) code, and a BCH code requires an information word having a predetermined length according to a coding rate. Accordingly, the zero padding unit 210 may paddle the zero bit in the L1 post signaling so as to be the length of the information word required in the BCH code. For example, when the length of the information word of the BCH code is K _bch and the length of the L1 post signaling is K _sig , the zero padding unit 210 _paddes zero bits of K _bch -K _sig bits to L1 post signaling .

A specific method of padding the zero bit by the zero padding unit 210 will be described later.

The encoding unit 220 encodes the information word. For this, the encoding unit 220 may include a BCH encoder 221 and an LDPC encoder 222 as shown in FIG.

The BCH encoder 221 and the LDPC encoder 222 are arranged in concatenation and the output of the zero padding unit 210 is input to the BCH encoder 221. [ Therefore, the information word generated by padding the zero bit in the L1 post signaling can be the information word of the BCH code.

The BCH encoder 221 performs BCH coding for L1 free signaling in which zero bits are padded. Then, the BCH encoder 221 outputs the BCH codeword generated by the BCH coding to the LDPC encoder 222.

Herein, since the BCH code is a systematic code, the information word can be directly included in the BCH codeword. That is, the BCH encoder 221 can generate BCH codewords by performing BCH coding of input bits with information words, and the BCH codeword can be a form in which BCH parity bits are added to input bits of information words.

On the other hand, the input bits may be composed of the same number of bits as the information word of the BCH code (e.g., K _bch ) as L1 post signaling in which zero bits are padded.

The LDPC encoder 222 performs LDPC encoding on the BCH codeword to generate LDPC codewords.

Herein, since the LDPC code is a systematic code, the information word can be directly included in the LDPC code word. That is, the LDPC encoder 222 can generate LDPC codewords by performing LDPC encoding of input bits with LDPC information words, and the LDPC codeword can be a form in which LDPC parity bits are added to input bits of information words.

On the other hand, the input bits may be composed of the same number of bits as the information word (e.g., K _ldpc ) of the LDPC code as the BCH codeword.

Meanwhile, a coding parameter of the encoding unit 220 for the L1 post signaling can be defined as shown in Table 1 below.

Here, K _bch is the length of the information word of the BCH code, and K _ldpc indicates the length of the information word of the LDPC code.

On the other hand, the LDPC coding generates LDPC codewords satisfying H 占^{T T} = 0. Here, H denotes a parity check matrix, and C denotes an LDPC code word. That is, the LDPC encoder 222 may multiply the parity check matrix to generate an LDPC codeword so as to be zero.

The LDPC encoder 222 may perform LDPC encoding according to various coding rates to generate LDPC codewords having various lengths. For example, the LDPC encoder 222 may perform LDPC encoding with a code rate of 7/15 or the like to generate an LDPC code word composed of 16200 bits.

Meanwhile, the parity check matrix used in LDPC coding can be defined according to the coding rate. Hereinafter, the parity check matrix used in the present invention will be described.

First, the structure of a parity check matrix according to an embodiment of the present invention will be described with reference to FIG.

Referring to FIG. 4, the parity check matrix 400 includes an information word partial matrix 410, which is a partial matrix corresponding to an information word, and a parity partial matrix 420, which is a partial matrix corresponding to a parity bit.

The information word _sub- matrix 410 includes K _ldpc columns and the parity submatrix 420 includes N _parity = N _ldpc- K _ldpc columns. Meanwhile, the number of rows of the parity check matrix 400 is equal to the number of columns N _parity = N _ldpc- K _ldpc of the parity partial matrix 420.

In the parity check matrix 400, N _ldpc indicates the length of the LDPC code word, K _ldpc indicates the length of the information word, and N _parity = N _ldpc -K _ldpc indicates the length of the parity.

Hereinafter, the structure of the information word partial matrix 410 and the parity partial matrix 420 will be described in detail. The elements of the information word partial matrix 410 and the parity partial matrix 420 excluding 1 are zero.

The information word submatrix 410 is a matrix including K _ldpc columns (i.e., the 0th column to the K _{ldpc -1th} column), and follows the following rules.

First, the K _ldpc columns constituting the information word submatrix 410 belong to the same group of M, and are divided into a total of K _ldpc / M column groups. The columns belonging to the same column group are shifted (i.e., cyclic shifted) by Q _ldpc .

Here, M is the interval at which the column pattern is repeated at the information word _sub- matrix 410 (M = 360, for example), and Q _ldpc is the size at which each column is shifted in the information word _sub- matrix 410. M and Q _ldpc are integers and are determined such that Q _ldpc = (N _{ldpc -} K _ldpc ) / M holds. At this time, K _ldpc / M is also an integer. The specific values of M and Q _ldpc may vary depending on the length and coding rate of the LDPC codeword.

이라 하면, i 번째 열 그룹 내의 j 번째 열에서 무게-1(weight-1)(즉, 1 값을 가지는 원소들)이 위치한 행의 인덱스

는 하기의 수학식 1과 같이 결정된다.Second, the degree of the 0th column of the i-th (i = 0,1, .., K _ldpc / M-1) column group (where the degree is the number of 1 values existing in the column, The order of all the columns belonging to is the same) is _denoted by D _i , and the position of each row with 1

, The index of the row in which the weight-1 (i.e., elements having a value of 1) is located in the jth column in the ith column group

Is determined according to the following equation (1).

Here, k = 0,1,2, ..., D _i -1, i = 0,1, ..., K _ldpc / M-1, j = 1,2, ..., M-1.

Meanwhile, Equation 1 can be expressed equally as Equation 2 below

Here, k = 0,1,2, ..., D _i -1, i = 0,1, ..., K _ldpc / M-1, j = 1,2, ..., M-1.

는 i 번째 열 그룹 내의 j 번째 열에서 k 번째 무게-1이 있는 행의 인덱스, N_ldpc는 LDPC 코드워드의 길이, K_ldpc는 정보어의 길이, D_i는 i 번째 열 그룹에 속하는 열들의 차수, M은 하나의 열 그룹에 속하는 열의 개수, Q_ldpc는 각 열이 쉬프트되는 크기를 의미한다.In these equations,

N _ldpc is the length of the LDPC codeword, K _ldpc is the length of the information word, D _i is the _rank of the columns belonging to the ith column group, , M is the number of columns belonging to one column group, and Q _ldpc is the size at which each column is shifted.

값만을 알면 i 번째 열 그룹 내의 k 번째 무게-1이 있는 행의 인덱스를 알 수 있음을 나타난다. 그러므로, 각각의 열 그룹 내의 첫 번째 열에서 k 번째 무게-1이 있는 행의 인덱스 값을 저장하면, 도 4의 구조를 갖는 정보어 부분 행렬(410))에서 무게-1이 있는 열과 행의 위치가 파악될 수 있다.According to these equations,

If we know only the value, it means we can know the index of the row with the kth weight -1 in the ith column group. Therefore, if the index value of the row having the kth weight -1 in the first column in each column group is stored, the position of the row and column having the weight -1 in the information word submatrix 410 having the structure of FIG. 4) Can be grasped.

According to the above rules, the orders of the columns belonging to the ith column group are all the same as D _i . Accordingly, an LDPC code storing information on a parity check matrix according to the above rules can be briefly expressed as follows.

For example, the N _ldoc 30, K _ldpc is 15, Q _ldpc the case of three, position information of the rows are in weight -1 in the 0th column of the three columns group to represented by a sequence such as the equation (3) , Which may be referred to as a &quot; weight-1 position sequence &quot;.

는 i번째 열 그룹 내의 j번째 열에서 k번째 무게-1이 있는 행의 인덱스를 의미한다.From here,

Denotes an index of a row having the kth weight -1 in the jth column in the ith column group.

The weight-1 position sequences such as Equation (3) representing the index of the row where 1 is located in the 0th column of each column group can be expressed more simply as shown in Table 2 below.

Table 2 shows the position of the weight-1, that is, the one having the value 1 in the parity check matrix, and the i-th weight-1 position sequence is the row of the row having weight -1 in the 0th column belonging to the i- Lt; / RTI &gt;

On the other hand, the parity partial matrix 420 is a partial matrix including N _ldpc- K _ldpc columns (i.e., K _ldpc -th column to N _ldpc -1-th column), and has a dual diagonal structure. Therefore, the order of the remaining columns except for the last column (i.e., N _ldpc -1 th column) included in the parity partial matrix 420 is 2, and the order of the last column (i.e., N _ldpc -1 th column) Is 1.

Hereinafter, a specific structure of a parity check matrix used in LDPC coding according to an embodiment of the present invention will be described.

Specifically, when the length _Nldpc of the LDPC codeword is 16200, the length _Kldpc of the information word is 7560, the coding rate is 7/15, and M is 360, the parity check matrix can be defined as shown in Table 3 below.

Table 3 shows the index of the row where 1 is located in the 0th column of the i-th column group of the information word partial matrix of the parity check matrix.

That is, the information word sub-matrix consists of 21 column groups each including 360 columns, and the position of one value in the 0-th column of each column group can be defined by the above-mentioned Table 3. [ For example, in the 0th column of the 0th column group, 1 may exist in the 432nd row, the 655th row, the 893rd row, ..., and so on.

A row in which 1 is present in the 0th column of each column group is shifted by Q _ldpc , and a row in which 1 is located in another column of the column group can be defined.

Specifically, in the case of Table 3, the index of the row where Q _ldpc = (N _ldpc- K _ldpc ) / M = (16200-7560) / 360 = 24 and the 1 in the 0th column of the 0th column group is 432, 655 , 893, ..., the index of the row in which the 1 is located in the first column of the 0th column group is 456 (= 432 + 24), 679 (= 655 + 24), 917 (= 893 + 24) ... , And the index of the row in which the 1 is located in the second column of the 0th column group may be 480 (= 456 + 24), 703 (= 679 + 24), 941 (= 917 + 24),.

Meanwhile, the parity check matrix defined in Table 3 has a structure as shown in FIG. 4, so that the parity partial matrix can have a double diagonal structure.

Meanwhile, the transmitting apparatus 200 may include a memory (not shown) to store information on the parity check matrix.

Hereinafter, a specific method of padding the zero bit by the zero padding unit 210 will be described.

The zero padding unit 210 divides the information word into a plurality of groups, padding a plurality of groups with zero bits in group units, and padding additional zero bits from a front end or a rear end of one of the plurality of groups according to a predetermined reference .

To this end, the zero padding unit 210 may divide the information word into a plurality of groups. Specifically, the zero padding unit 210 may calculate the number of groups constituting the information word based on the number of bits of the information word, and divide the information word into a plurality of groups based on the calculated number.

)를 N_group 개의 그룹으로 구분할 수 있다. For example, the zero padding unit 210 may generate information words (i ₀ , i ₁ , ..., i ₂ ) based on the following Equation (4) or

) Can be divided into N _group groups.

는 x보다 작은 최대 정수를 의미하며, 일 예로,

이다.In these equations, Z _j represents the j-th group and K _bch represents the length of the information word of the BCH code. And,

Means a maximum integer smaller than x, for example,

to be.

On the other hand, when the coding parameters are as shown in Table 1, information words divided into a plurality of groups can be represented as shown in FIG.

Referring to FIG. 5, information words are divided into N _groups . Here, when the coding parameters are as shown in Table 1, N _group can be 21.

번째 그룹은 192(=360-(K_ldpc-K_bch)=360-(7560-7392)) 비트로 구성된다.Then, the j-th group of Z _j of the _group of N group satisfies -2 0≤j≤N _group consists of 360 bits and the last group

Second group is _{192 (= 360- (K ldpc -K} bch) = 360- (7560-7392)) bit configuration.

In FIG. 5, a BCH parity bit (BCF FEC) and an LPDC parity bit (LDPC FEC) are also shown. In this case, the BCH parity bits may be configured with 168 bits, and the LPDC parity bits may be configured with different numbers of bits according to the coding rate. For example, if the length _Nldpc of the LDPC LDPC code word is 16200, the length of the information word _Kldpc is 7560, and the coding rate is 7/15, the LDPC parity bit may be composed of 8640 (= 16200-7560) bits.

Then, the zero padding unit 210 calculates the number of zero bits to be padded in the L1 post signaling.

Specifically, the zero padding unit 210 may calculate the difference between the length of the information word of the BCH code and the length of the L1 post signaling as the number of zero bits to be padded. For example, if the length of the information word of the BCH code is K _bch and the length of the L1 post signaling is K _sig , then the number of zero bits padded may be K _bch - K _sig .

In addition, the zero padding unit 210 can calculate the number of groups of zero bits to be padded in the point that the zero bits are padded in groups in the L1 post signaling.

In this case, the zero padding unit 210 may calculate the number of groups of zero bits to be padded based on the number of groups constituting the information word and the number of zero bits to be padded.

Specifically, when the number of bits constituting the L1 post signaling is equal to or smaller than the number of bits included in one of the plurality of groups, the zero padding unit 210 calculates the number of groups of zero bits padded based on Equation (6) Can be calculated. Here, the number of bits included in one of the plurality of groups may be 360. [

Here, N _pad is the number of groups of zero bits to be padded, and N _group is the number of groups constituting the information word.

That is, when the number of bits constituting the L1 post signaling is K _sig , the zero padding unit 210 subtracts 1 from the number N _group of groups constituting the information word when 0 < K _sig &lt; The number of groups of zero bits padded can be calculated as N _pad .

However, when the number of bits constituting the L1 post signaling exceeds the number of bits included in one of the plurality of groups, the zero padding unit 210 determines the number of groups of bits to be padded Can be calculated. Here, the number of bits included in one of the plurality of groups may be 360. [

는 x보다 작은 최대 정수를 의미하며, 일 예로,

이다.Here, N _pad is the number of constituting the control number, K _bch is information of a group of bit zero is padding bits, K _sig is the number of bits constituting the L1 post-signaling, K _bch - K _sig is zero are padding bits . And,

Means a maximum integer smaller than x, for example,

to be.

That is, the zero padding unit 210 sets a maximum integer smaller than a value obtained by dividing the number _Kbch -K _sig of padded zero bits by the number of bits 360 contained in one group when zero (K _sig > 360) The number of groups of bits can be calculated as N _pad .

The reason why the zero padding unit 210 calculates the number of groups of zero bits padded in the above-described manner is as follows.

Referring to FIG. 5, if the number of bits of the L1 post signaling is less than or equal to 360, the L1 post signaling may be mapped in one group as long as it is not located in the N _group- 1 group. Therefore, since zero bits can be padded in units of groups except for the group in which the L1 post signaling is located, the zero padding unit 210 subtracts 1 from the number of groups constituting the information word and zeros are padded The number of groups is calculated. In other cases, when the number of bits of the L1 post signaling exceeds 360, the L1 post signaling is placed in two or more groups. Therefore, the zero padding unit 210 sets the number of zero bits to be padded to the number of bits included in one group And divides the number of groups into which zero bits are padded.

Thereafter, the zero padding unit 210 determines a position of a group to which a zero bit is padded among a plurality of groups based on a preset shortening pattern, and pads the group of zero bits at the determined position .

In this case, the preset shortening pattern can be defined as shown in Table 4 below.

Here,? _S (j) represents a j-th group in which zero bits are padded among a plurality of groups constituting information words. Therefore,? _S (j) may be a sequence of the jth group of shortening patterns.

π _s (j) is defined differently depending on the modulation scheme and the coding rate of the LDPC code. For example, if the modulation scheme is binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) and the code rate is 7/15 as shown in Table 4, the modulation scheme is 16-QAM (quadrature amplitude modulation) A case where the modulation scheme is 64-QAM, a coding rate is 7/15, and a case where the modulation scheme is 256-QAM and the coding rate is 7/15, different shortening pattern sequences may be applied.

Meanwhile, a method of padding a zero bit by group using a shortening pattern as shown in Table 4 is as follows.

그룹,

그룹,...,

그룹을 제로 비트가 패딩되는 그룹으로 판단하고, 해당 그룹에 제로 비트를 그룹 단위로 패딩할 수 있다. Zero-padding unit 210 when the number of groups of zero padding bits calculated in N _pad, π _s (0) of the plurality of groups, the second group, π _s (1) is the second group, ..., π _s (N _pad -1) th group by zero bits. For example, when Z _j corresponds to the j-th group in the information word, the zero padding unit 210

group,

group,...,

The group can be determined as a group in which zero bits are padded, and zero bits can be padded to the group in units of groups.

번째 그룹은 192 비트로 구성된다는 점에서 해당 그룹에는 192 개의 제로 비트를 그룹 단위로 패딩할 수 있다.In this case, the zero padding unit 210 can padd a zero bit as many as the number of bits included in each group into the corresponding group. That is, the zero-padding unit 210 may _group N groups of the _group 0≤j≤N -2 padding the j-th group Z _j is the group of zero bits, the 360 by one in that the configuration bits 360 that satisfy a group basis And the last group

Th group is composed of 192 bits, the group can be padded with 192 zero bits in groups.

Thereafter, the zero padding unit 210 may calculate an additional zero bit, and may pad an additional zero bit of the calculated number of large bits. Here, the additional zero bit may be a bit remaining after padding in units of a group in units of the number of bits included in each group from the entire zero bit padded. Thus, the additional zero bit may be composed of fewer bits than the number of bits contained in the group being padded.

On the other hand, the group in which the additional zero bit is padded may be determined by a preset shortening pattern. Specifically, if the number of groups of zero bits to be padded is N _pads , the group in which the additional zero bits are padded may be? _S (N _pad ).

For example, assume that the number of groups of zero bit padded N _pad is 2, the modulation scheme is BPSK, and the code rate is 7/15. In this case, according to the shortening pattern as shown in Table 4, the zero bits are padded by 360 zeros in groups of 4 (=? _S (0)) and 5 (=? _S . Therefore, the remaining zero bits, i.e., K _bch -K _sig - (2 x 360) bits excluding the padded zero bits in the fourth group and the fifth group in the padded overall zero bit K _bch -K _sig become additional zero bits . The group in which the additional zero bit is padded is 6 (=? _S (2)) and K _bch - K _sig - (2 x 360) has a value smaller than 360 which is the number of bits included in the sixth group do.

On the other hand, the zero padding unit 210 may padd additional zero bits in different ways depending on whether the predetermined criteria are satisfied or not. Here, the different schemes include that additional zero bits are padded from the front end of the group or padded from the rear end.

That is, the zero padding unit 210 may padd additional zero bits from the front end or the rear end of one of the plurality of groups according to a predetermined criterion.

Specifically, the zero padding unit 210 adds π _s (N _pad ) th group based on Table 4 when the number N _pad of groups of padded zero bits satisfies a first predetermined condition, (N _pad ) group from the rear end of the group, and further zero bits can be sequentially padded from the rear end of the group π _s (N _pad ).

Here, the first predetermined condition may be N _pad = N _group -1 when the number of groups constituting the information word is N _group . The number of additional zero bits may be 360-K _sig when the number of bits contained in one of the plurality of groups is 360 and the number of bits constituting L1 post signaling is K _sig .

For example, assume that the number N _group of groups constituting information words is 21, the number of groups of zero bit padding N _pad is 20, the modulation method is QPSK, and the coding rate is 7/15. In this case, since N _group -N _pad = 1, it can be seen that the first predetermined condition is satisfied. Then, based on Table 4, since the group in which the additional zero bit is padded is 0 (=? _S (20)) th group, the additional zero bit can be padded to the 0th group.

At this time, the zero padding unit 210 can sequentially pad the zero bit from the last bit out of the 360 bits constituting the 0th group. For example, when the additional zero bit is 200 bits, the zero padding unit 210 _outputs i ₃₅₉ , i ₃₅₈ , i ₃₅₈ among the (i ₀ , i ₁ , ..., i ₃₅₈ , i ₃₅₉ ) ..., i ₁₆₁ , i _{160 in this} order. Accordingly, zero bits are padded to the 200 bits behind the 360 bits.

On the other hand, when the number N _pad of groups of zero bits to be padded satisfies the second predetermined condition, the zero padding unit 210 adds π _s (N _pad ) th group based on Table 4 with an additional zero bit padded Group, and add-zero bits can be sequentially padded from the rear end of the group of? _S (N _pad ).

Here, the second predetermined condition is that when the number of groups constituting the information word is N _group ,? _S (N _pad ) is set to a predetermined value (here, the predetermined value may be 4, for example) It can be small and N _pad <N _group -1. If the number of bits included in one of the plurality of groups is 360 and the number of bits constituting L1 post signaling is _Ksig and the number of bits constituting L1 post signaling is _Ksig , K _bch- K _sig -360 x N _pad .

For example, assume that the number N _group of groups constituting information words is 21, the number of groups of zero bit padding N _pad is 11, the modulation scheme is QPSK, and the coding rate is 7/15. In this case, since N _pad <N _group -1 and 2 (=? _S (11)) <4 based on Table 4, it can be seen that the second predetermined condition is satisfied. And, based on Table 4, since the group in which the additional zero bit is padded is 2 (=? _S (10)) th group, the additional zero bit can be padded to the second group.

At this time, the zero padding unit 210 can sequentially padd zer bit from the last bit out of the 360 bits constituting the fifteenth group. For example, if the additional bit is a zero bit 200, a zero padding 210 2 constituting the second group (i _720, i _721, ..., ₁₀₇₈ i, ₁₀₇₉ i) from ₁₀₇₉ i, ₁₀₇₈ i, ..., i ₈₈₁ , i ₈₈₀ in total. Accordingly, the second group is padded with zero bits at the 200 bits behind the 360 bits.

On the other hand, zero-padding section 210 is the number of groups of bit zero is padded N _pad, the first predetermined condition and a second group if it is not satisfied with a predetermined condition, and π _s (N _pad), the second group based on Table 4 May be determined as a group to which additional zero bits are padded, and padding of additional zero bits sequentially from the previous stage of the group of [pi] _s (N _pad ).

Here, the number of additional zero bits is such that if the number of bits contained in one of the plurality of groups is 360, the number of bits constituting L1 post signaling is _Ksig and the number of bits constituting L1 post signaling is _Ksig , K _bch- K _sig -360 x N _pad .

For example, assume that the number N _group of groups constituting information words is 21, the number N _pad of groups of zero bit padded is 10, the modulation method is QPSK, and the code rate is 7/15. In this case, since N _pad <N _group -1 and 15 (=? _S (10))> 4 based on Table 4, it can be seen that the first and second predetermined conditions are not satisfied. And, based on Table 4, since the group in which the additional zero bits are padded is 15 (=? _S (10)) th group, the additional zero bits can be padded to the 15th group.

At this time, the zero padding unit 210 can sequentially padd zer bit from the first bit among the 360 bits constituting the 15th group. For example, if the additional bit is a zero bit 200, a zero padding unit 210 constituting the 15-th group (i _5400, i _5401, ..., ₅₇₅₈ i, ₅₇₅₉ i) from ₅₄₀₀ i, ₅₄₀₁ i, ..., i ₅₅₉₈ , i ₅₅₉₉ in total. Accordingly, the fifteenth group is padded with zero bits in the front 200 bits of 360 bits.

After the zero bits are padded in this manner, the zero padding unit 210 can generate the information word by positioning the L1 post signaling in the information word.

Specifically, the zero padding unit 210 can generate an information word by sequentially padding L1 post signaling at a position where zero bits are not padded in the information word.

)에서 (i₂₀₀,i₂₀₁,...,

,

)에 제로 비트가 위치하게 되는 경우, 제로 패딩부(210)는 200 비트로 구성된 L1 포스트 시그널링을 (i₀,i₁,...,i₁₉₈,i₁₉₉)에 순차적으로 위치시킬 수 있다. 이 경우, L1 포스트 시그널링이 (s₀,s₁,..,s₁₉₈,s₁₉₉)인 경우, 결국, 정보어는 (i₀,i₁,...,

)=(s₀,s₁,..,s₁₉₈,s₁₉₉,0,0,...,0,0)와 같이 구성될 수 있다.For example, the information word _{(i 0, i 1, ...} ,

(I ₂₀₀ , i ₂₀₁ , ...,

,

, The zero padding unit 210 can sequentially position the 200-bit L1 post signaling to (i ₀ , i ₁ , ..., i ₁₉₈ , i ₁₉₉ ). In this case, if the L1 post signaling is (s ₀ , s ₁ , .., s ₁₉₈ , s ₁₉₉ ), eventually, the information word is (i ₀ , i ₁ ,

) = (s ₀ , s ₁ , ..., s ₁₉₈ , s ₁₉₉ , 0, 0, ..., 0, 0).

Hereinafter, a method of generating an information word will be described with reference to FIGS. 6 and 7. FIG. The coding parameters used in FIGS. 6 and 7 are shown in Table 1, and the BCH FEC indicates BCH parity bits added to information words by BCH coding.

6 shows a case where the number K _sig of bits constituting the L1 post signaling is 1144, the modulation method is QPSK, and the coding rate is 7/15.

In this case, the number of zero bits to be padded is the _{6248 (= K bch -K sig =} 7392-1144). Further, since 1144 (= K _sig ) > 360, the number N _pad of groups of zero bits padded according to Equation (7) becomes 17.

The index of the group in which the zero bits are padded is 4 (=? _S (0)), 5 (=? _S (1)), _{6 (= π s (2)} ), 7 (= π s (3)), 8 (= π s (4)), 9 (= π s (5)), 3 (= π s (6)), _{12 (= π s (7)} ), 13 (= π s (8)), 14 (= π s (9)), 15 (= π s (10)), 2 (= π s (11)), _{16 (= π s (12)} ), 17 (= π s (13)), 18 (= π s (14)), 1 (= π s (15)), 10 (= π s (16)) is do.

Accordingly, the zero padding unit 210 padding 360 zero bits to each group in order of the fourth group, the fifth group, ..., the first group, and the tenth group among the plurality of groups constituting the information word .

On the other _{hand, 17 (= N pad) <} 20 (= N group -1) and _{19 (= π s (17)} ) , so <4, more zero bit is padded to _{19 (= π s (17)} ) th group, It can be sequentially padded from the front end of the 19th group. In this case, the number of additional zero bits is 128 (= K _bch- K _sig -360 x N _pad = 7392-1144-360 x 17).

Accordingly, the zero padding unit 210 can padding 128 bits of additional zero bits sequentially from the previous stage of the 19th group.

After padding the zero bits in this way, the zero padding unit 210 can place the L1 post signaling in the bits where the zero bit is not located among the bits constituting the information word. That is, the zero padding unit 210 applies all the bits of the 0th group, all the bits of the 11th group, the bits of which no additional zero bits are located in the 19th group, and all bits of the 20th group, Can be positioned.

In this case, only the 20th group is composed of 192 bits, and the remaining groups except the 20th group are composed of 360 bits. The number of bits in which the additional zero bit is not located in the 19th group is 232. Thus, 1144 (= 360 + 360 + 232 + 192) bits of L1 post signaling can be placed in the information word.

7 shows a case where the number K _sig of bits constituting the L1 post signaling is 1832, the modulation method is QPSK, and the code rate is 7/15.

In this case, the number of zero bits to be padded is the _{5560 (= K bch -K sig =} 7392-1832). Further, since 1144 (= K _sig ) > 360, the number N _pad of zero bit groups padded according to Equation (7) becomes 15.

The index of the group in which the zero bits are padded is 4 (=? _S (0)), 5 (=? _S (1)), _{6 (= π s (2)} ), 7 (= π s (3)), 8 (= π s (4)), 9 (= π s (5)), 3 (= π s (6)), _{12 (= π s (7)} ), 13 (= π s (8)), 14 (= π s (9)), 15 (= π s (10)), 2 (= π s (11)), 16 (=? _S (12)), 17 (=? _S (13)) and 18 (=? _S (14)).

Accordingly, the zero padding unit 210 padding 360 zero bits to each group in the order of the fourth group, fifth group, ..., seventeenth group, and eighteenth group among the plurality of groups constituting the information word .

On the other _{hand, 15 (= N pad) <} 20 (= N group -1) and because it is _{1 (= π s (15)} ) <4, additional bit is zero padded to _{1 (= π s (15)} ) th group, And may be sequentially padded from the rear end of the 15th group. In this case, the number of bits of the additional zero bit is 160 (= K _bch- K _sig -360 x N _pad = 7392-1832-360 x 15).

Accordingly, the zero padding unit 210 can sequentially padd 160 bits of additional zero bits from the rear end of the 15th group.

After padding the zero bits in this way, the zero padding unit 210 can place the L1 post signaling in the bits where the zero bit is not located among the bits constituting the information word. That is, the zero padding unit 210 receives all the bits of the 0th group, all bits of the 10th group, all bits of the 11th group, all bits of the 11th group, All the bits of the 20th group, and the L1 post signaling to all bits of the 20th group.

In this case, only the 20th group is composed of 192 bits, and the remaining groups excluding the 20th group are composed of 360 bits. The number of bits in which the additional zero bit is not located in the first group is 200. Thus, 1832 (= 360 + 200 + 360 + 360 + 360 + 192) bits of L1 post signaling can be placed in the information word.

The reason for padding the zero bits in the above-described manner in the present invention is as follows.

For example, referring to FIG. 6, which is an example of padding of zero bits in the manner described in the present invention, additional zero bits are sequentially located from the front of the 19th group. In this case, among the 19th group, the bits where no additional zero bit is located are continuously connected to the bits of the 20th group.

Accordingly, if only the position of the bit where no additional zero bit is located in the 19th group is known, the L1 post signaling is sequentially located from the bit in which no additional zero bit is located among the 19th group, and the L1 post signaling Can be positioned.

However, as shown in FIG. 8, when the additional zero bit is located from the rear of the 19th group, it is necessary to know not only the position of the bit where no additional zero bit is located but also the position of the start bit of the 20th group, It is possible to place the L1 post signaling in the 20th group, which is a problem in that the calculation becomes complicated as compared with the embodiment shown in Fig.

As described above, in the present invention, the information word can be generated by a simpler operation by adjusting the starting point of the position where the additional zero bit is padded.

Meanwhile, the transmitting apparatus 200 can modulate the LDPC codeword output from the encoding unit 220 and transmit the modulated LDPC codeword to a receiving apparatus (not shown).

Specifically, the transmitting apparatus 200 generates modulation symbols by mapping LDPC codeword bits to the ST points based on BPSK, QPSK, 16-QAM, 64-QAM, and 256-QAM, May be mapped to an OFDM frame and transmitted to a receiving apparatus (not shown).

In this case, the padded zero bits are removed and not transmitted to the receiving device (not shown). Thus, the fact that padded zero bits are removed after coding is referred to as shortening, and the padded zero bits are not transmitted by shortening.

9 is a block diagram illustrating a detailed configuration of a transmitting apparatus according to an embodiment of the present invention. 9, the transmission apparatus 200 includes a segment padding 230, a scrambler 240, a parity interleaver 250, a puncturing unit 260, an interleaver 270 (not shown) in addition to the zero padding unit 210 and the encoding unit 220. [ And a modulating unit 280. The modulating unit 280 modulates the modulated signal. Here, the zero padding unit 210 and the encoding unit 220 are the same as those described in FIG. 2 to FIG. 8, and a detailed description thereof will be omitted.

The segment unit 230 segments the L1 post signaling and outputs the segmented L1 post signaling to the scrambler 240. [

Specifically, the segment unit 230 may segment the L1 post signaling to have a predetermined number of bits or less and output the segmented L1 post signaling (or L1 post block) to the scrambler 240. [ In this case, the preset number may be smaller than the length of the information word that can be encoded by the encoding unit 220. [

The scrambler 240 scrambles the segmented L1 post signaling. That is, the scrambler 240 may randomize the bits constituting the segmented L1 post signaling and output the randomized L1 post signaling to the zero padding unit 210. [

Accordingly, the zero padding unit 210 pads zero bits for the L1 post signaling output from the scrambler 240, and outputs the padded zero bits to the encoding unit 220. [ The encoding unit 220 may perform BCH encoding and LDPC encoding of the bits output from the zero padding unit 210 with information words to generate LDPC codewords and output the LDPC codewords to the parity interleaver 250.

The parity interleaver 250 receives the LDPC codeword from the encoder 220 and performs interleaving on the LDPC parity bits constituting the LDPC codeword. Then, the parity interleaver 250 outputs the parity-interleaved LDPC codeword to the puncturing unit 260.

) 중에서 LDPC 패리티 비트만을 인터리빙하고, 패리티 인터리빙된 LDPC 코드워드 U=(u₀,u₁,...,

)를 펑처링부(260)로 출력할 수 있다.Specifically, the parity interleaver 250 calculates LDPC code words C = (c ₀ , c ₁ , ..., c ₁ ) output from the coding unit 220 based on the following equation (8)

), Interleaves only the LDPC parity bits, and outputs the parity interleaved LDPC codeword U = (u ₀ , u ₁ , ...,

) To the puncturing unit 260. [

Here, M is the interval at which the pattern of the column is repeated in the information word submatrix, that is, the number of columns included in the column group, Q _ldpc is the size by which each column is shifted in the information word submatrix, and K _ldpc is the LDPC information word The number of bits.

For example, when LDPC coding is performed based on the parity check matrix defined by Table 3, K _ldpc = 7560, M = 360, Q _ldpc = 24.

The puncturing unit 260 punctures at least a part of the LDPC parity bits constituting the LDPC codeword. Here, the puncturing means that some of the parity bits are removed and not transmitted, so that the punctured LDPC parity bits may not be transmitted. For example, the puncturing unit 260 may puncture a predetermined number of LDPC parity bits in consideration of the coding rate and the number of bits of the LDPC parity bits.

In addition, the puncturing unit 260 can remove the zero bit padded by the zero padding unit 210. [ That is, the puncturing unit 260 performs the shortening operation, and the padded zero bits are not transmitted by the shortening.

Specifically, the puncturing unit 260 can remove the K _bch -K _sig zero bits padded by the zero padding unit 210. For example, if the zero bit is padded in the same manner as described with reference to FIG. 6, the puncturing unit 260 may _divide the K _bch -K _sig zero bits padded between the L1 post signaling and the BCH parity bits Can be removed.

Accordingly, K _sig L1 post-signaling bits (i.e., signaling information in FIG. 10), 168 BCH parity bits, (N _ldpc - K _ldpc - N _punc) the LDPC parity bit only remains. Where N _punc represents the number of bits to be punctured.

In this way, the puncturing unit 260 punctures at least a part of the LDPC parity bits in the LDPC code word, removes the zero bits padded by the zero padding unit 210, and outputs the zero bits to the interleaver 270.

The interleaver 270 interleaves the bits output from the puncturing unit 240 and outputs the interleaved bits to the demux 280. In this case, the interleaver 270 may interleave the bits output from the puncturing unit 260 using N _c columns composed of N _r rows.

Specifically, the interleaver 270 writes the bits output from the puncturing unit 260 in the column direction from the first column to the N _c -th column, and outputs the bits from the first row to the N _r -th row of the plurality of columns in which the bits are written Direction and perform interleaving. Accordingly, the bits written to the same row in each column are sequentially output, so that the order of the bits can be refined compared to before interleaving.

Meanwhile, the interleaver 270 may selectively perform interleaving according to a modulation scheme. For example, the interleaver 270 may perform an interleaving operation only when the modulation scheme is 16-QAM, 64-QAM, or 256-QAM.

On the other hand, the number of columns N _c and the number of rows N _r of the interleaver 270 can be variously changed according to the coding rate and the modulation method. For example, when the coding rate of the LDPC code is 7/15, the number of columns N _c is equal to the modulation order for L1 post signaling, and the number N _r of rows is the number of LDPC code words output from the puncturing unit 260 Number of bits / N _c . That is, when the number of bits of the LDPC code word output from the _puncturing unit 260 is N _{L1 post} , the modulation order is 16, QAM, 64-QAM, and 256-QAM, respectively, The number of columns N _c is 4, 6, 8, respectively, and the number of rows N _r may be N _L1post / 4, N _L1post / 6, N _L1post / 8.

The demux 280 demultiplexes the bits output from the interleaver 270. Specifically, the demux 280 performs a bit-to-cell conversion on the bits output from the interleaver 270, and outputs the bits output from the interleaver 270 to a predetermined number of bits (Or a parallel data cell) having a plurality of cells.

For example, the demux 280 may output the interleaved LDPC codeword bits output from the interleaver 270 sequentially to one of the plurality of sub-streams, convert the interleaved LDPC codeword bits into cells, and output the interleaved LDPC codeword bits. In this case, bits having the same index in each of the plurality of sub-streams can constitute the same cell.

Here, the number of sub-streams is equal to the number of bits constituting the cell. For example, when the modulation scheme is BPSK, QPSK, 16-QAM, 64-QAM, or 256-QAM, the number of sub-streams may be 1, 2, 4, 6, _{N L1post, N L1post / 2,} N L1post / 4, can be an _{N L1post / 6, N L1post /} 8.

Meanwhile, the demux 280 may selectively demultiplex according to a modulation scheme. For example, the demux 280 may not perform a demultiplexing operation when the modulation scheme is BPSK.

The modulator 290 may modulate the cells output from the demux 280. Specifically, the modulator 290 can map the cells output from the demux 280 to the store using various modulation schemes such as BPSK, QPSK, 16-QAM, 64-QAM, and 256-QAM to modulate have. Here, when the modulation method is BPSK, QPSK, 16-QAM, 64-QAM, or 256-QAM, the number of bits constituting the modulated cell (i.e., modulation symbol) is 1, .

Meanwhile, the transmitting apparatus 200 can transmit the modulation symbols to a receiving apparatus (not shown). For example, the transmitting apparatus 200 may map a modulation symbol to an OFDM frame using the OFDM scheme, and transmit the modulation symbol to a receiving apparatus (not shown) through the assigned channel. In this case, the modulation symbols of the L1 signaling can be mapped to the preamble in the OFDM frame.

11 is a block diagram illustrating a configuration of a transmitting apparatus according to another embodiment of the present invention. Referring to FIG. 11, the transmitting apparatus 200 'includes a BCH encoder 221', a zero padding unit 210 ', and an LDPC encoder 222'.

The transmitting apparatus 200 'shown in FIG. 11 is different from the transmitting apparatus 200 described with reference to FIG. 2 and FIG. 3 only in the arrangement relationship of the elements, and the operations and parameters used in the elements are the same. Therefore, the following description will focus on the above-described differences.

The BCH encoder 221 'performs BCH coding for the L1 post signaling and outputs the BCH codeword generated by the BCH coding to the zero padding unit 210'.

In this case, the L1 post signaling may have a length equal to the length of the information word required for BCH coding, and 168 BCH parity bits may be generated by BCH coding.

The zero padding unit 210 'paddes zero bits to the BCH codeword and outputs it to the LDPC encoder 222'.

Here, when the BCH codeword is composed of N _bch bits and the length of the information word of the LDPC code is K _ldpc , the zero padding unit 210 'may pad K _ldpc - N _bch zero bits.

On the other hand, the method of padding the zero bits may be the same as the method described in Figs. 2 to 10. However, the information word to which the zero bit is padded in FIGS. 2 to 10 is the information word of the BCH code, but it may be the information word of the LDPC code in this embodiment. Therefore, in this embodiment, the part to which the information word of the BCH code is applied in FIG. 2 to FIG. 10 can be applied as an information word of the LDPC code.

The LDPC encoder 222 'performs LDPC encoding on the BCH codeword with zero bits padded.

12 is a block diagram illustrating a detailed configuration of a transmitting apparatus according to another embodiment of the present invention. Referring to FIG. 11, the transmitting apparatus 200 'includes a segment unit 230', a scrambler 240 ', a parity interleaver (not shown) in addition to the BCH encoder 221', the zero padding unit 210 'and the LDPC encoder 222' 250 ', a puncturing unit 260', an interleaver 270 ', and a modulating unit 280'.

Here, the BCH encoder 221 ', the zero padding unit 210', and the LDPC encoder 222 'are the same as those described with reference to FIG. 11, and a detailed description thereof will be omitted. In addition, the transmitting apparatus 200 'shown in FIG. 12 is different from the transmitting apparatus 200 described in FIG. 9 only in the arrangement relationship of the constituent elements, but the operations and parameters used in the respective constituent elements are the same. Therefore, the following description will focus on the above-described differences.

The scrambler 240 'scrambles the segmented L1 post signaling and outputs it to the BCH encoder 221'.

Accordingly, the BCH encoder 221 'performs BCH encoding on the L1 post signaling output from the scrambler 240, and outputs the result to the zero padding unit 210. Then, the zero padding unit 210 pads the BCH codeword output from the BCH encoder 221 'with zero bits and outputs it to the LDPC encoder 222'. The LDPC encoder 222 'performs LDPC encoding on the BCH codeword with padding of zero bits to generate an LDPC codeword and output it to the parity interleaver 250'.

13 is a block diagram illustrating a configuration of a receiving apparatus according to an embodiment of the present invention. 13, the receiving apparatus 1300 includes a decoding unit 1310 and a depadding unit 1320.

The decoding unit 1310 decodes the signal received from the transmitting apparatus 200. [ For this, the decoding unit 1320 may include an LDPC decoder 1311 and a BCH decoder 1312 as shown in FIG.

Specifically, the LDPC decoder 1311 can perform LDPC decoding using the LLR value for the signal received from the transmitting apparatus 200. [ In this case, the receiving apparatus 1300 may further include a demodulator (not shown) for demodulating the received signal to generate an LLR value corresponding to the LDPC codeword.

For example, the LDPC decoder 1311 may perform LDPC decoding with iterative decoding based on a sum-product algorithm. Here, the summing algorithm is a type of message passing algorithm, and the message passing algorithm is a method in which messages (e.g., LLR values) are exchanged through an edge on a bipartite graph generated based on a parity check matrix, It shows an algorithm that calculates and updates the output message from messages input to variable nodes or check nodes.

Here, the parity check matrix used in the LDPC decoding may have a structure as shown in FIG. 4, and may be composed of an information word partial matrix and a parity partial matrix. Here, the information word submatrix is defined as shown in Table 3 and the parity submatrix can have a double diagonal structure. Meanwhile, the receiving apparatus 1300 may include a memory (not shown) to store information on the parity check matrix.

Then, the BCH decoder 1312 performs BCH decoding on the output value of the LDPC decoder 1311.

Here, the BCH decoder 1312 corrects the error using the BCH parity bits in that the output value of the LDPC decoder 1311 is composed of L1 post signaling, zero bit padded in the L1 post signaling, and BCH parity bits. And outputs the zero bits padded to the L1 post signaling and the L1 post signaling to the demapping unit 1320. [

Information on the coding parameters used in decoding may be stored in the receiving apparatus 1300 or may be provided from the transmitting apparatus 200. [

The demapping unit 1320 may demodulate the padded zero bits in the L1 post signaling. As a result, the zero bit is removed so that the L1 post signaling can be restored.

Specifically, the demapping unit 1320 demaps a group in which zero bits are padded and a group in which additional zero bits are padded, based on information on the number of groups of zero bits padded in the transmitting apparatus 200 and a preset shortening pattern And remove the zero bits present in the group. Here, the predetermined shortening pattern can be defined as shown in Table 4 described above.

In particular, the de-padding unit 1320 may determine whether the additional zero bit is padded from the previous or following end of the group, and may remove the additional zero bit according to the determination result.

Information on the various types of information for depadding, for example, the number of groups of zero bits padded in the transmitting apparatus 200, the shortening pattern, and the like may be stored in the receiving apparatus 1300 or provided from the transmitting apparatus 200 .

15 is a block diagram illustrating a detailed configuration of a receiving apparatus according to an embodiment of the present invention. 15, the receiving apparatus 1300 includes a demodulator 1330, a demultiplexer 1340, a deinterleaver 1350, a demultiplexer 1360, a parity decoder 1360, and a demultiplexer 1360 in addition to the decoder 1310 and the demultiplexer 1320. An interleaver 1370, a descrambler 1380, and a combiner 1390. Here, the decoding unit 1310 and the depadding unit 1320 are the same as those described in FIG. 14, and a detailed description thereof will be omitted.

The demodulation unit 1330 receives and demodulates the signal transmitted from the transmission apparatus 200. Specifically, the demodulator 1330 demodulates the received signal, generates a value corresponding to the LDPC codeword, and outputs the value to the multiplexer 1340.

Here, the value corresponding to the LDPC codeword can be expressed by the channel value. There are various ways to determine the channel value, for example, a method for determining the LLR value.

Here, the LLR value can be represented by a value obtained by taking the ratio of the probability that the bit transmitted from the transmitting apparatus 200 is 0 and the probability of one day to Log. Alternatively, the LLR value may be a bit value determined according to a hard decision, and the LLR value may be a representative value determined according to a period in which the probability that the bit transmitted from the transmitting apparatus 200 is 0 or 1 belongs .

The multiplexer 1340 multiplexes the output value of the demodulator 1330 and outputs the multiplexed output to the deinterleaver 1350.

Specifically, the MUX 1350 corresponds to the DEMUX 260 of the transmitting apparatus 200 and can perform an operation corresponding to the DEMUX 280. That is, the Mux 1350 can perform cell-to-bit conversion on the output value of the demodulator 1330 and multiplex the LLR values of the cell unit on a bit-by-bit basis.

The deinterleaver 1350 deinterleaves the output value of the MUX 1340 and outputs it to the demultiplexing unit 1360.

Specifically, the deinterleaver 1350 is a component corresponding to the interleaver 270 of the transmitting apparatus 200, and can perform an operation corresponding to the interleaver 270. That is, the deinterleaver 1350 may deinterleave the output value of the mux 1340 by performing the interleaved operation in the interleaver 270 inversely.

The de-interfinger 1360 adds a specific value to the output value of the de-interleaver 1350 and outputs it to the parity deinterleaver 1370.

Specifically, the depuncturing unit 1360 corresponds to the puncturing unit 260 of the transmitting apparatus 200, and performs an operation corresponding to the puncturing unit 260. That is, the de-puncturing unit 1360 can add the LLR value corresponding to the punctured parity bits and the LLR value corresponding to the bits that have been shortened to the LLR value output from the deinterleaver 1350. Here, the LLR value corresponding to the punctured bits may be 0, and the LLR value corresponding to the bits that have been shortened may be ∞, -∞.

To this end, the receiving apparatus 1300 may store information on the number and position of the punctured bits in the transmitting apparatus 200, or may receive the information from the transmitting apparatus 200. In addition, the receiving apparatus 100 may store information on the number, position, and bit values of the shortened bits in the transmitting apparatus 200, or may receive the information from the transmitting apparatus 200.

The parity deinterleaver 1370 performs parity deinterleaving on the output value of the de-punting unit 1360 and outputs it to the decrypting unit 1310.

Specifically, the parity deinterleaver 1370 corresponds to the parity interleaver 250 of the transmitting apparatus 200, and performs operations corresponding to the parity interleaver 250. That is, the parity deinterleaver 1370 inversely performs the interleaving operation performed by the parity interleaver 250 and deinterleaves the LLR values corresponding to the LDPC parity bits among the LLR values output from the demultiplexing unit 1360 .

In this case, the decoding unit 1310 may perform decoding on the output value of the parity deinterleaver 1370, and may output the bits generated as the decoding result to the depadding unit 1320. In this case, the bits generated as a result of decoding may be composed of zero bits padded to L1 post signaling and L1 post signaling, and zero bits may be removed by the demapping unit 1320. [

The descrambler 1380 descrambles the L1 post signaling.

Specifically, the descrambler 1380 corresponds to the scrambler 240 of the transmitting apparatus 200, and performs an operation corresponding to the scrambler 240. That is, the descrambler 1380 can reverse-randomize the L1 post signaling bits and output the de-randomized L1 post signaling to the combiner 1390.

The combiner 1390 performs disaggregation on the output value of the descrambler 1380.

Specifically, the combiner 1390 is a component corresponding to the segment unit 230 of the transmission apparatus 200, and can perform an operation corresponding to the segment unit 230. That is, the combiner 1390 may de-segment the L1 post signaling to generate the L1 post signaling before being segmented.

16 is a flowchart illustrating a zero bit padding method of a transmitting apparatus according to an embodiment of the present invention.

First, an information word is generated by padding a zero bit to the L1 post signaling (S1610).

Then, the information word is encoded (S1620).

Specifically, in step S1610, the information word is divided into a plurality of groups, and a plurality of groups are padded with zero bits in group units, and additional zero bits are padded from the front end or the rear end of one of the plurality of groups according to a predetermined reference have.

Here, it is possible to calculate the number of groups constituting the information word based on the number of bits of the information word, and divide the information word into a plurality of groups based on the calculated number.

In this case, the number of groups of zero bits padded based on the number of groups constituting the information word or the number of zero bits to be padded can be calculated.

For example, when the number of bits constituting the L1 post signaling is equal to or less than the number of bits included in one of the plurality of groups, the number of groups of zero bits padded based on Equation (6) can be calculated.

Further, when the number of bits constituting the L1 post signaling exceeds the number of bits included in one of the plurality of groups, it is possible to calculate the number of groups of zero bits padded based on Equation (7).

In step S1610, the position of the group to which the zero bit is padded among the plurality of groups is determined based on the preset shortening pattern, and the zero bit is padded on the group basis in the determined position.

Here, the predetermined shortening pattern, as defined in the table as shown in Table 4, S1610 step is when the number of groups of bit zero is padding the N _pad, the plurality of groups π _s (0) th group, π _s ( 1) th group, ..., n _s (N _pad -1) th group.

In this case, N _pad is the first predetermined if they meet the condition, on the basis of the Table 4 and determine the π _s (N _pad) group is the second group an additional zero bits the padding, the π _s (N _pad) th Additional zero bits can be sequentially padded from the end of the group.

Here, the first predetermined condition may be N _pad = N _gruop- 1 when the number of groups constituting the information word is N _gruop . The number of additional zero bits may be 360-K _sig when the number of bits included in one of the plurality of groups is 360 and the number of bits constituting L1 post signaling is _Ksig .

On the other hand, N _pad of the second group if they meet the predetermined condition, based on Table 4 and determine the group is π _s (N _pad) Add the a second group of zero bit padding, π _s (N _pad) th group Additional zero bits can be padded sequentially from the back end.

Here, the second predetermined condition may be N _pad <N _gruop- 1 when? (N _pad ) is smaller than a preset value and the number of groups constituting the information word is N _gruop . If the number of bits added to zero if the number of bits constituting the information word K _bch is the number of bits constituting the L1 post-signaling K _sig is 360, the number of bits included in one of a plurality of groups, K _bch - K _sig -360 x N _pad .

On the other hand, if N _pad does not satisfy the first predetermined condition and the second predetermined condition, the group of? _S (N _pad ) is determined as a group to which the additional zero bit is padded based on Table 4, and? _S N _pad ) group from the previous stage.

When here, the number of bits added to zero if the number of bits constituting the information word K _bch is the number of bits constituting the L1 post-signaling K _sig is 360, the number of bits included in one of a plurality of groups, K _bch -K _sig -360 x N _pad .

In step S1610, the information word may be generated by sequentially mapping the L1 post signaling to a position where the zero bit is not padded in the information word.

Meanwhile, a non-transitory computer readable medium storing a program for sequentially performing the zero bit padding method according to the present invention may be provided.

A non-transitory readable medium is a medium that stores data for a short period of time, such as a register, cache, memory, etc., but semi-permanently stores data and is readable by the apparatus. In particular, the various applications or programs described above may be stored on non-volatile readable media such as CD, DVD, hard disk, Blu-ray disk, USB, memory card, ROM,

Although the buses are not shown in the block diagrams of the transmitting apparatus and the receiving apparatus, the communication between the respective elements in the transmitting apparatus and the receiving apparatus may be performed via the bus. Further, the transmitting apparatus and the receiving apparatus may further include a processor such as a CPU, a microprocessor, or the like that performs the various steps described above.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention.

200: transmitting apparatus 210: zero padding unit
220:

Claims (32)

A transmission apparatus for processing and transmitting L1 post-signaling,
A zero padding unit for generating an information word by padding a zero bit to the L1 post signaling; And
And an encoding unit encoding the information word,
The zero-
Dividing the information word into a plurality of groups, padding the plurality of groups with zero bits in group units, and padding additional zero bits from the front end or the rear end of one of the plurality of groups according to a predetermined criterion Transmitting apparatus. The method according to claim 1,
The zero-
Calculates the number of groups constituting the information word based on the number of bits of the information word, and divides the information words into a plurality of groups based on the calculated number. 3. The method of claim 2,
The zero-
Wherein the number of groups of zero bits to be padded is calculated based on the number of groups constituting the information word or the number of zero bits to be padded. The method of claim 3,
The zero-
Wherein when the number of bits constituting the L1 post signaling is equal to or less than the number of bits included in one of the plurality of groups, the number of groups of zero bits to be padded is calculated based on the following equation Device:

Here, N _pad is the number of groups of padded zero bits, and N _group is the number of groups constituting the information word. The method of claim 3,
The zero-
And the number of groups of zero bits padded is calculated based on the following equation when the number of bits constituting the L1 post signaling exceeds the number of bits included in one of the plurality of groups Transmitting apparatus:

Here, N _pad is the number of bits constituting the count, K _bch is the information word of a group of bit zero being the padding, K _sig is a number of bits constituting the L1 post-signaling, K _bch - K _sig is the The number of zero bits to be padded. The method of claim 3,
The zero-
Determines a position of a group to which the zero bit is padded among the plurality of groups based on a preset shortening pattern, and pads the group of zero bits at the determined position. The method according to claim 6,
The preset shortening pattern is defined by the following table,

The zero-
If the number of groups of zero bits to be padded is N _pad , a group of? _S (0) th group,? _S (1) th group,? _S (N _pad -1) And the padding unit groups the zero bits in a group unit. 8. The method of claim 7,
The zero-
The N _pad of the first group if they meet the predetermined condition, determining the group based on the table that is π _s (N _pad) the second group an additional zero bits the padding, and the π _s (N _pad) th group And sequentially padding additional zero bits from the rear end. 9. The method of claim 8,
The first predetermined condition is that,
And N _pad = N _gruop- 1 when the number of groups constituting the information word is N _gruop . 9. The method of claim 8,
Wherein the number of additional zero bits,
The transmission apparatus as if the number of bits included in one of the plurality of group 360 and the number of bits constituting the L1 post-signaling K _sig, characterized in that the 360-K _sig. 9. The method of claim 8,
The zero-
The N _pad of the second group if they meet the predetermined condition, determining the group based on the table that is π _s (N _pad) the second group an additional zero bits the padding, and the π _s (N _pad) th group And sequentially padding additional zero bits from the rear end. 12. The method of claim 11,
The second preset condition is that,
(N _pad ) is smaller than a predetermined value and N _pad < N _gruop- 1 when the number of groups constituting the information word is N _gruop . 12. The method of claim 11,
Wherein the number of additional zero bits,
If the number of bits constituting the information word K _bch is the number of bits constituting the L1 post-signaling, and K _sig is the number of bits included in one group of the plurality 360, K _bch -K _sig - _Wherein the transmission unit is a 360 x N _pad . 12. The method of claim 11,
The zero-
Wherein the N _pad is determined by the first predetermined condition and the second group does not meet the predetermined condition, based on said table π _s (N _pad) th group of the bits are padded said additional agent group, and and sequentially padding additional zero bits from the front end of the group of? _s (N _pad ). 15. The method of claim 14,
Wherein the number of additional zero bits,
If the number of bits constituting the information word K _bch is the number of bits constituting the L1 post-signaling, and K _sig is the number of bits included in one group of the plurality 360, K _bch -K _sig - _Wherein the transmission unit is a 360 x N _pad . The method according to claim 1,
The zero-
Wherein the information word is generated by sequentially mapping the L1 post signaling to a position where the zero bit is not padded in the information word. A zero bit padding method of a transmitter for processing and transmitting L1 post signaling,
Padding a zero bit to the L1 post signaling to generate an information word; And
And encoding the information word,
Wherein the generating comprises:
Dividing the information word into a plurality of groups, padding the plurality of groups with zero bits in group units, and padding additional zero bits from the front end or the rear end of one of the plurality of groups according to a predetermined criterion Zero bit padding method. 18. The method of claim 17,
Wherein the generating comprises:
The number of groups constituting the information word is calculated based on the number of bits of the information word, and the information word is divided into a plurality of groups based on the calculated number. 19. The method of claim 18,
Wherein the generating comprises:
Wherein the number of groups of zero bits to be padded is calculated based on the number of groups constituting the information word or the number of zero bits to be padded. 20. The method of claim 19,
Wherein the generating comprises:
Wherein when the number of bits constituting the L1 post signaling is equal to or less than the number of bits included in one of the plurality of groups, the number of groups of zero bits to be padded is calculated based on the following equation Bit padding method:

Here, N _pad is the number of groups of padded zero bits, and N _group is the number of groups constituting the information word. 20. The method of claim 19,
Wherein the generating comprises:
And the number of groups of zero bits padded is calculated based on the following equation when the number of bits constituting the L1 post signaling exceeds the number of bits included in one of the plurality of groups The zero bit padding method:

Here, N _pad is the number of bits constituting the count, K _bch is the information word of a group of bit zero being the padding, K _sig is a number of bits constituting the L1 post-signaling, K _bch - K _sig is the The number of zero bits to be padded. 20. The method of claim 19,
Wherein the generating comprises:
Determining a position of a group to which the zero bit is padded among the plurality of groups based on a preset shortening pattern, and padding the zero bit at a group position in the determined position. 23. The method of claim 22,
The preset shortening pattern is defined by the following table,

Wherein the generating comprises:
If the number of groups of zero bits to be padded is N _pad , a group of? _S (0) th group,? _S (1) th group,? _S (N _pad -1) Wherein the zero bits are padded on a group basis. 24. The method of claim 23,
Wherein the generating comprises:
The N _pad of the first group if they meet the predetermined condition, determining the group based on the table that is π _s (N _pad) the second group an additional zero bits the padding, and the π _s (N _pad) th group And further zeroing bits are sequentially padded from the rear end. 25. The method of claim 24,
The first predetermined condition is that,
And N _pad = N _gruop- 1 when the number of groups constituting the information word is N _gruop . 25. The method of claim 24,
Wherein the number of additional zero bits,
If the number of bits included in one of the plurality of group 360 and the number of bits constituting the L1 post-signaling of K _sig, how zero padding bits, characterized in that 360-K _sig. 25. The method of claim 24,
Wherein the generating comprises:
The N _pad of the second group if they meet the predetermined condition, determining the group based on the table that is π _s (N _pad) the second group an additional zero bits the padding, and the π _s (N _pad) th group And further zeroing bits are sequentially padded from the rear end. 28. The method of claim 27,
The second preset condition is that,
_Wherein the number of groups constituting the information word is N _gruop , and π (N _pad ) is smaller than a predetermined value and N _pad <N _gruop- 1. 28. The method of claim 27,
Wherein the number of additional zero bits,
If the number of bits constituting the information word K _bch is the number of bits constituting the L1 post-signaling, and K _sig is the number of bits included in one group of the plurality 360, K _bch -K _sig - Gt; x N _pad . &_Lt; / RTI &gt; 28. The method of claim 27,
Wherein the generating comprises:
Wherein the N _pad is determined by the first predetermined condition and the second group does not meet the predetermined condition, based on said table π _s (N _pad) th group of the bits are padded said additional agent group, and and padding the additional zero bits sequentially from the front end of the group of [pi] _s (N _pad ). 31. The method of claim 30,
Wherein the number of additional zero bits,
If the number of bits constituting the information word K _bch is the number of bits constituting the L1 post-signaling, and K _sig is the number of bits included in one group of the plurality 360, K _bch -K _sig - Gt; x N _pad . &_Lt; / RTI &gt; 18. The method of claim 17,
Wherein the generating comprises:
Wherein the information word is generated by sequentially mapping the L1 post signaling to a position where the zero bit is not padded in the information word.

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