KR102223813B1 - Transmiting apparatus, data mapping method thereof, receiving apparatus and data processing method thereof - Google Patents

Abstract

A data mapping method is disclosed. The data mapping method includes mapping the first data and the second data to an OFDM symbol and transmitting a frame including an OFDM (Othogonal Frequency Division Multiplexing) symbol. After the first data and the second data are mapped, the second data may be additionally mapped to the remaining cells.

Description

Transmitting device, data mapping method thereof, receiving device and data processing method thereof {TRANSMITING APPARATUS, DATA MAPPING METHOD THEREOF, RECEIVING APPARATUS AND DATA PROCESSING METHOD THEREOF}

The present invention relates to a transmitting apparatus, a data mapping method thereof, a receiving apparatus and a data processing method thereof, and more particularly, to a transmitting apparatus for mapping data to an OFDM symbol, a data mapping method thereof, a receiving apparatus and a data processing method thereof. will be.

In the information society of the 21st century, broadcasting and communication services are entering the era of full-scale digitalization, multi-channelization, broadbandization, and high quality. In particular, as the spread of high-definition digital TVs, PMPs, and portable broadcasting devices has recently increased, there is an increasing demand for supporting various reception methods for digital broadcasting services.

In response to these demands, the standard group has established various standards to provide various services that can satisfy the needs of users. Accordingly, it is requested to find a way to provide a better service to users through better performance.

The present invention is in accordance with the above-described necessity, and an object of the present invention is to provide a transmitting apparatus, a data mapping method thereof, a receiving apparatus and a data processing method thereof, which additionally map and transmit data to the remaining cells of an OFDM symbol, It is in the offering.

A data mapping method according to an embodiment of the present invention for achieving the above object includes mapping the first data and the second data to an OFDM symbol and transmitting a frame including the OFDM symbol, The mapping step further maps the second data to cells remaining after the first data and the second data are mapped in the OFDM symbol.

Here, the second data may be composed of a plurality of second data blocks.

In addition, in the mapping step, the first data and the plurality of second data blocks are mapped to cells in the OFDM symbol, and the number of cells remaining after the first data and the second data block are mapped to the ODFM symbol And calculating the length of the second data block to be additionally mapped based on the number of the second data blocks, and adding a part of each of the plurality of second data blocks to the remaining cells based on the calculated block length. Can be mapped.

In the mapping step, the first data and one of the plurality of second data blocks may be mapped to cells in the OFDM symbol, and a part of the mapped second data block may be additionally mapped to a next cell. .

Here, in the mapping step, the other one of the plurality of second data blocks is mapped to a cell next to the cell to which the partial second data block is mapped, and a part of the other mapped second data block is next Can be further mapped to cells.

Meanwhile, a transmission apparatus according to an embodiment of the present invention includes a frame mapper for mapping first data and second data to an OFDM symbol, and a transmission unit for transmitting a frame including the OFDM symbol, wherein the frame mapper includes the The second data may be additionally mapped to cells remaining after the first data and the second data are mapped in the OFDM symbol.

Here, the second data may be composed of a plurality of second data blocks.

In addition, the frame mapper maps the first data and the plurality of second data blocks to cells in the OFDM symbol, and the number of cells remaining after the first data and the second data block are mapped to the ODFM symbol, and The length of the second data block to be additionally mapped is calculated based on the number of the second data blocks, and a part of each of the plurality of second data blocks is additionally mapped to the remaining cells based on the calculated length of the block. can do.

In addition, the frame mapper may map the first data and one of the plurality of second data blocks to cells in the OFDM symbol, and further map a part of the mapped second data block to the next cell.

Here, the frame mapper maps the other one of the plurality of second data blocks to a cell next to the cell to which the part of the second data block is mapped, and maps a part of the other mapped second data block to the next cell. It can be mapped in addition to.

Meanwhile, a data processing method of a receiving device according to an embodiment of the present invention includes receiving a signal from a transmitting device and processing the received signal, wherein the signal received from the transmitting device is first data And second data is mapped to an OFDM symbol, first data and second data are mapped in the OFDM symbol, and the second data is additionally mapped to remaining cells.

Here, the second data may be composed of a plurality of second data blocks.

In addition, in the signal received from the transmission device, the first data and the plurality of second data blocks are mapped to cells in the OFDM symbol, and a portion of each of the plurality of second data blocks is additionally mapped to the remaining cells. Is a signal, and the length of the additionally mapped second data block is calculated based on the number of cells remaining after the first data and the second data block are mapped to the ODFM symbol and the number of the second data block. I can.

In the signal received from the transmitting device, one of the first data and the plurality of second data blocks is mapped to cells in the OFDM symbol, and a part of the mapped second data block is further mapped to the next cell. It may be a signal.

Herein, the signal received from the transmitting device is mapped to a cell next to the cell to which the part of the second data block is mapped, and the other one of the plurality of second data blocks is mapped. Some may be signals additionally mapped to the next cell.

Meanwhile, a receiving device according to an embodiment of the present invention receives and processes a signal from a transmitting device, and in the signal received from the transmitting device, first data and second data are mapped to an OFDM symbol, and the first data is mapped to the OFDM symbol. The first data and the second data may be mapped and the second data may be additionally mapped to the remaining cells.

Here, the second data may be composed of a plurality of second data blocks.

In addition, in the signal received from the transmission device, the first data and the plurality of second data blocks are mapped to cells in the OFDM symbol, and a portion of each of the plurality of second data blocks is additionally mapped to the remaining cells. Is a signal, and the length of the additionally mapped second data block is calculated based on the number of cells remaining after the first data and the second data block are mapped to the ODFM symbol and the number of the second data block. I can.

In the signal received from the transmitting device, one of the first data and the plurality of second data blocks is mapped to cells in the OFDM symbol, and a part of the mapped second data block is further mapped to the next cell. It may be a signal.

Herein, the signal received from the transmitting device is mapped to a cell next to the cell to which the part of the second data block is mapped, and the other one of the plurality of second data blocks is mapped. Some may be signals additionally mapped to the next cell.

According to various embodiments of the present disclosure as described above, the second data may be additionally mapped to the remaining cells in the OFDM symbol. In this way, if the second data is additionally mapped, the reliability that the receiving side can receive and process the second data may be improved.

1 is a block diagram illustrating a configuration of a transmission device according to an embodiment of the present invention.
2 to 12 are diagrams for explaining a method of additionally mapping L1 post signaling when second data is L1 post signaling according to an embodiment of the present invention;
13 and 14 are block diagrams for explaining a detailed configuration of a transmission device according to an embodiment of the present invention;
15 to 17 are block diagrams for explaining the configuration of a receiving device according to an embodiment of the present invention;
18 is a flowchart illustrating a data mapping method of a transmission device according to an embodiment of the present invention, and
19 is a flowchart illustrating a data processing method of a receiving device according to an embodiment of the present invention.

1 is a block diagram illustrating a configuration of a transmission device according to an embodiment of the present invention. Referring to FIG. 1, the transmission device 100 includes a frame mapper 110 and a transmission unit 120.

The frame mapper 110 maps data of a first type (hereinafter, referred to as first data) and data of a second type (hereinafter, referred to as second data) to an OFDM (Othogonal Frequency Division Multiplexing) symbol.

Here, the OFDM symbol may be one preamble symbol in the frame. As an example, the preamble symbol may be one 8k OFDM symbol composed of 8192 cells (or sub-carriers). However, in some cases, the first data and the second data may be mapped not only to the preamble symbol but also to the data symbol.

Meanwhile, the first data includes information necessary for the receiving device 1500 to access the second data, and the second data is for the receiving device 1500 to access the data mapped to the data symbols in the OFDM frame. May contain information. In this case, information on the first data, for example, the length of the first data and the location of cells to which the first data is mapped in the OFDM symbol, may be predefined between the transmitting device 100 and the receiving device 1500. .

Accordingly, the receiving apparatus 1500 may restore first data from the OFDM symbol, obtain information on second data from the first data, and restore second data from the OFDM symbol. Here, the first data may include information on the second data, and the information on the second data includes information on the length of the second data and information on the positions of cells to which the second data is mapped in the OFDM symbol. It may include at least one of. Accordingly, the reception device 1500 may restore the second data from the OFDM symbol based on the information on the second data.

In addition, the receiving device 1500 may obtain information on a transmission method, length, etc. of data mapped to a data symbol based on the second data, and receive the corresponding data from the data symbol using this.

For example, the first data may be L1 pre-signaling, and the second data may be L1 post-signaling. In this case, the data mapped to the data symbol may be broadcast data (eg, data representing actual broadcast content) composed of one or more physical layer pipes (PLPs).

Meanwhile, the first data and the second data may be input to the frame mapper 110 in the form of a modulation symbol.

Specifically, the bits constituting each of the first data and the second data are BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), 16-QAM (Quadrature Amplitude Modulation), 64-QAM, 256-QAM, 1024 It is modulated according to various modulation schemes such as -QAM and 4096-QAM, and may be input to the frame mapper 110, and the frame mapper 110 may map each of the modulation symbols to cells of an OFDM symbol. Here, as the modulation scheme, not only the conventional QAM scheme, but also a modulation scheme having a non-uniform constellation may be applied.

In this case, the number of modulation symbols input to the frame mapper 110 may be as follows.

Specifically, when the number of bits constituting the first data is N _{data _1} , the number of modulation symbols for the first data is equal to _{N data _1} /η _{MOD _ data _ 1.} If here, η _{MOD _ data _ 1} is the first is in order of modulation (modulation order) for a data modulation scheme BPSK, QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM η MOD _ _{data _ 1} can be 1,2,4,6,8,10 respectively.

Meanwhile, the second data is segmented to have a length less than a certain value, and each of the segmented second data may be mapped to an OFDM symbol. Accordingly, when the second data is _segmented into N data_block_2 pieces and the number of bits constituting each of the segmented second data is N _{data _2} , the number of modulation symbols for each segmented second data is N _{data _2/ηMOD_data_2,} and , The number of total modulation symbols for the second data may be N _{data _2} /η _{MOD _ data _2} ×N _{data_block_2} . Here, η _{MOD _ data _2 is the modulation order for the second data, and η MOD _ data _2} is each 1 when the modulation method is BPSK, QPSK, 16-QAM, 64-QAM, 256-QAM, and 1024-QAM. Can be ,2,4,6,8,10.

Hereinafter, as an example of a case where the first data is L1 pre-signaling and the second data is L1 post-signaling, the number of modulation symbols input to the frame mapper 110 will be described in more detail.

The L1 pre-signaling and the L1 post-signaling may be encoded and then modulated to be input to the frame mapper 110, and the frame mapper 110 may map the modulation symbols to cells of the preamble symbol.

In this case, when the bit stream generated by encoding L1 pre-signaling (that is, coded bits for L1 pre-signaling) is called an L1-pre Forward Error Correction FRAME, The number of modulation symbols is _equal to N L1pre /η _{MOD _ L1pre} . Here, N _L1pre is the number of bits constituting the L1 pre-FEC frame, η _{MOD _ L1pre} is the modulation order for L1 pre-signaling, and the modulation method is BPSK, QPSK, 16-QAM, 64-QAM, 256-QAM. , In case of 1024-QAM, η _{MOD _ L1pre} may be 1,2,4,6,8,10, respectively.

Meanwhile, since the length of the L1 post signaling is variable, the L1 post signaling may be segmented to have a length less than a certain value, and each of the segmented L1 post signaling may be encoded. In this way, since each of the segmented L1 post signaling is encoded after the L1 post signaling is segmented, a bit stream generated by encoding each of the segmented L1 post signaling (i.e., encoded bits for the segmented L1 post signaling) Each may be referred to as an L1-post FEC frame (L1-post FEC FRAME).

In this case, when the number of bits constituting each of the L1 post FEC frames is N _L1post , each of the L1 post FEC frames is _{mapped to N MOD _ L1post _ per _ FEC} (=N _L1post /η _{MOD _ L1post} ) modulation symbols. Can be. Here, η _{MOD _ L1post is a modulation order for L1 post signaling, and η MOD _ L1post} is 1,2, respectively, when the modulation method is BPSK, QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM. Can be ,4,6,8,10.

Accordingly, when the number of L1 post FEC frames is N _{L1post _ FECFRAME} , the number of modulation symbols for L1 post signaling N _{MOD _ L1post _ Total} is N _{MOD _ L1post _ Total} = N _{MOD _ L1post _ per _ FEC} × N _Same as L1post_FECFRAME.

Hereinafter, a method of mapping the first data and the second data to the OFDM symbol by the frame mapper 110 will be described in more detail.

First, the frame mapper 110 maps first data and second data to cells of an OFDM symbol. Specifically, the frame mapper 110 may sequentially map the first data and the second data to a plurality of cells constituting the OFDM symbol.

For example, the index of the cells that make up the OFDM symbols 0, 1, 2, ... and the same time, the frame mapper 110 is from 0-th _data cell N _{_1} / η _{MOD _ _1} first _data to the second cell, The modulation symbols for data are sequentially mapped. In addition, the frame mapper 110 sequentially maps the modulation symbols for the second data from the cell next to the cell to which the modulation symbol for L1 pre-signaling was last mapped, that is, from the N _{data _1} /η _{MOD _ data _1 th cell.} can do.

In this case, the frame mapper 110 may perform mapping for each data block. That is, since the second data is segmented and each segmented second data is mapped to an OFDM symbol, when each segmented second data block is referred to as a second data block, the frame mapper 110 determines the second data. 2 Can be mapped to OFDM symbols for each data block.

For example, when there are three second data blocks, the frame mapper 110 sequentially maps the modulation symbols for the first second data block, and sequentially maps the modulation symbols for the second second data block. , The modulation symbols for the third second data block may be sequentially mapped.

Thereafter, the frame mapper 110 may additionally map the second data to the remaining cells after the first data and the second data are mapped in the OFDM symbol. In this case, as described above, the second data may be composed of a plurality of data blocks.

Specifically, the frame mapper 110 maps the first data and the plurality of second data blocks to cells in the OFDM block, and the first data and the plurality of second data blocks are mapped to the OFDM symbol, and the number and plurality of remaining cells are mapped. A length of the second data block to be additionally mapped may be calculated based on the number of second data blocks of, and a part of each of the plurality of second data blocks may be additionally mapped to the remaining cells based on the calculated length.

Here, the calculated length means the number of modulation symbols that can be mapped to remaining cells among a plurality of modulation symbols constituting the second data block. In this case, the calculated length may have the same value for all of the plurality of second data blocks, or the difference in length calculated for each of the plurality of second data blocks may have a value less than 1.

To this end, the frame mapper 110 may calculate the number of cells remaining after the first data and the second data are mapped in the OFDM symbol. Here, since the second data constitutes a plurality of second data blocks, mapping of the second data may be regarded as mapping of a plurality of second data blocks.

Specifically, the frame mapper 110 maps the first data and the second data to the remaining cells based on the maximum number of cells to which modulation symbols for first data and modulation symbols for second data can be mapped in an OFDM symbol. You can calculate the number of them.

Here, the mappable cells refer to cells to which modulation symbols for each of the first data and the second data can be mapped among a plurality of cells constituting the OFDM symbol. For example, 8192 constituting one 8k OFDM symbol Assuming that the number of cells pre-determined to be used for other purposes such as a pilot is 1324 among the cells, 6868 cells other than this may be cells to which the first data and the second data can be mapped.

For example, when the maximum number of cells in which modulation symbols for first data and modulation symbols for second data can be mapped is N _{preamble _ Available _ Cells} in a preamble symbol, first data and second data are mapped. The number of remaining cells N _{preamble _ Remaining _ Cells} is equal to N _{preamble_Remaining_Cells} =N _{preamble_Available_Cells} -N _{data_1} /η _{MOD _ data _1} -(N _{data _2} /η _{MOD _ data _2} ×N _{data _ block _2} ) (here, When the first data is L1 pre-signaling and the second data is L1 post signaling, N _{preamble _ Remaining _ Cells} is expressed as N _{preamble _ Remaining _ Cells} = N _{preamble _ Available _ Cells} -N _L1pre /η _{MOD_L1pre} -N _{MOD_L1post_Total.} Can). That is, the number of remaining cells may be a value obtained by subtracting the number of modulation symbols for each of the first data and the second data from the maximum number of mappable cells.

As a specific example, when the first data is modulated with BPSK, since η _{MOD _ data _1} = 1, N _{preamble_Remaining_Cells} is N _{preamble _ Remaining _ Cells} = N _{preamble _ Available _ Cells} -N _{data _1} -(N _{data _2} /η _{MOD _ It is the same as data _2} ×N _{data_block_2} ). As another example, when the first data is modulated with QPSK, η _{MOD _ data _1} =2, so N _{preamble _ Remaining _ Cells} is N _{preamble _ Remaining _ Cells} = N _{Preablble _ Available _ Cells} -N _{data _1} /2-(N _{data _2} /η _{MOD_data_2} ×N _{data _ block _2} ).

Further, the frame mapper 110 calculates the length of a block that can be mapped to the remaining cells in each of the second data blocks based on the number of remaining cells. Here, the length of the block means the number of modulation symbols that can be mapped to the remaining cells among the plurality of modulation symbols constituting the second data block, and they all have the same value for the plurality of second data blocks, or The difference in lengths of blocks calculated for each of the plurality of second data blocks may have a value less than 1.

In this case, the frame mapper 110 may calculate the length of a block that can be mapped to cells remaining in each of the second data blocks according to a predefined rule.

Here, the predefined rule may be determined by a quotient and a remainder obtained by dividing the number of cells remaining after the first data and a plurality of second data blocks are mapped in the OFDM symbol by the number of second data blocks. have.

To this end, the frame mapper 110 determines whether the number of remaining cells is an integer multiple of the number of second data blocks. That is, the frame mapper 110 has a _{value of N preamble_Remaining_Cells} /N _{data_block_2} (here, when the first data is L1 pre-signaling and the second data is L1 post signaling, N _{preamble _ Remaining _ Cells} / N _{L1post _ FECFRAME} value) is Determine whether it is an integer.

Accordingly, when the number of remaining cells is an integer multiple of the number of second data blocks (i.e., when the remainder does not exist), the frame mapper 110 divides the number of remaining cells by the number of second data blocks. A block having a length of as much may be copied from each of the second data blocks and mapped to the remaining cells.

That is, the frame mapper 110 has N _{preamble _ Remaining _ Cells} / N _{data _ block _2} (here, when the first data is L1 pre-signaling and the second data is L1 post signaling, N _{preamble_Remaining_Cells} / N _{L1post_FECFRAME} ) of The modulation symbols may be copied in each second data block, and N _{preamble _ Remaining _ Cells} / N _{data _ block _2} modulation symbols copied from each second data block may be mapped to the remaining cells.

In this way, when the number of remaining cells is an integer multiple of the number of second data blocks, the frame mapper 110 divides the remaining cells by the number of second data blocks, and has the same length copied from each second data block. Each block can be additionally mapped to each divided cell. In this case, each divided cell may be composed of the same number of cells.

On the other hand, when the number of remaining cells is not an integer multiple of the number of second data blocks (i.e., when there is a remainder), the frame mapper 110 operates at least one of the plurality of second data blocks. Blocks with a length different from the one can be copied.

For example, it is assumed that the number of remaining cells and the number of second data blocks _{satisfy a formula such as N preamble_Remaining_Cells} =Q×N _{data _ block _2} +R (R>0) (here, the first data Is L1 pre-signaling and the second data is L1 post-signaling, N _{preamble _ Remaining _ Cells} = Q×N _{L1post _ FECFRAME} +R (R>0)). That is, when the number of remaining cells is divided by the number of second data blocks, it means a case where the neck is Q and the remainder is R.

In this case, a frame mapper 110 (N _{data_block_2} -R) copying the plurality of the second data block R of the second block having a length of as much as in the data blocks, each Q + 1 to the value of the mapping to the remaining cells, and of In each of the second data blocks, a block having a length of a Q value may be copied and mapped to the remaining cells (here, when the first data is L1 pre-signaling and the second data is L1 post-signaling, (N _{L1post _ FECFRAME} -R) copies a block having a length of Q value from each of the second data blocks).

That is, the frame mapper 110 copies Q+1 modulation symbols from each of the R second data blocks and maps them to the remaining cells, and maps the Q modulation symbols to (N _{data _ block _2} -R) second data blocks. Each can be copied and mapped to the remaining cells.

In this case, the frame mapper 110 may map the copied blocks in the order of length to the remaining cells. That is, the frame mapper 110 may sequentially map the remaining cells from a cell having a small cell index to a block having a long length.

Referring to the above example, a block having a length of Q+1 value is copied from each of R second data blocks, and a length of Q value is copied from each of (N _{data _ block _2} -R) second data blocks. The block with is copied. In this case, the frame mapper 110 sequentially maps blocks of length Q+1 from a cell having a small cell index among remaining cells, and sequentially maps blocks of length Q to cells after the corresponding blocks are mapped. I can.

As a specific example, _{it is assumed that N data _ block _2} =3 and R=2. In this case, the frame mapper 110 copies blocks of length Q+1 from each of two second data blocks among three second data blocks, and copies blocks of length Q from one second data block. . In addition, the frame mapper 110 may sequentially map two blocks having a length of Q+1 from a cell having a small cell index among remaining cells, and map one block having a length of Q to the remaining cells.

In this way, when the number of remaining cells is not an integer multiple of the number of second data blocks, the frame mapper 110 classifies the remaining cells as many as the number of second data blocks, and each block copied from each second data block. Can be additionally mapped to each of the separated cells. In this case, at least one of each divided cell may be composed of a different number of cells than the rest.

As in the above-described embodiments, the frame builder 110 sequentially maps the first data and the plurality of second data blocks to cells in the preamble symbol, and additionally maps a portion of each of the plurality of second data blocks to the remaining cells. can do.

Hereinafter, when the first data is L1 pre-signaling and the second data is L1 post signaling, a method of additionally mapping the L1 post signaling will be described in more detail with reference to FIGS. 2 to 12. Meanwhile, for convenience of explanation, it is assumed that 3 L1 post FEC frames in FIGS. 2 to 12 and 6868 (=N _{Preamble _ Available _ Cells} ) cells among one 8k preamble OFDM symbol are used for L1 signal transmission. I did. That is, it is assumed that the number of cells to which L1 pre-signaling and L1 post-signaling can be mapped among cells constituting one 8k preamble OFDM symbol, N _{Preamble _ Available _ Cells, is 6868.}

Meanwhile, as described above, the L1 post signaling may be additionally mapped to the remaining cells after the L1 pre-signaling and the L1 post signaling are mapped. In this way, repetitive mapping of L1 post signaling is referred to as a repetition scheme (repetiton scheme or cyclic repetiton scheme) in this specification, and blocks copied in L1 post signaling are repeated in order to be additionally mapped to the remaining cells. , It will be referred to as a block.

First, FIG. 2 is a diagram illustrating a method of additionally mapping an L1 post FEC frame to the remaining cells when the number of remaining cells is an integer multiple of the number of L1 post FEC frames according to an embodiment of the present invention.

The frame mapper 110 maps the L1 pre-FEC frame and the three L1 post-FEC frames to the preamble symbol.

For example, as shown in FIG. 2, the frame mapper 110 maps modulation symbols for the L1 pre-FEC frame to cells having a cell index of 0,1,..,x-1. Here, x may be N _L1pre /η _{MOD _ L1pre} . That is, the frame mapper 110 may _{sequentially map N L1pre} /η _{MOD _ L1pre} modulation symbols for the L1 free FEC frame to cells having a cell index of 0,1,..,x-1.

In addition, as shown in FIG. 2, the frame mapper 110 maps modulation symbols for the first L1 post FEC frame from a cell next to the cell to which the last modulation symbol for the L1 pre-FEC frame is mapped. That is, the frame mapper 110 maps the modulation symbols for the first L1 post FEC frame _{to y 1} cells from a cell having a cell index of x. Here, y ₁ may be N _{MOD_L1post_per_FEC.} Accordingly, the frame mapper 110 may map the N _{MOD _ L1post _ _ FEC per} modulation symbol for the first post 1 L1 FEC frame after the pre-mapped cell L1 FEC frame cells sequentially.

In addition, as shown in FIG. 2, the frame mapper 110 maps modulation symbols for the second L1 post FEC frame from a cell next to the cell to which the last modulation symbol for the first L1 post FEC frame is mapped. That is, the frame mapper 110 maps the modulation symbols for the second L1 post FEC frame _{to y 2} cells from a cell with a cell index of x+y _{1 to y 2.} Here, y ₂ may be N _{MOD_L1post_per_FEC.} Accordingly, the frame mapper 110 may map the N _{MOD _ L1post _ _ per FEC} modulation symbols for the 2 L1 post-FEC frame from the cell after the cell mapping claim 1 L1 post-FEC frame in order.

In addition, as shown in FIG. 2, the frame mapper 110 maps modulation symbols for the third L1 post FEC frame from a cell next to the cell to which the last modulation symbol for the second L1 post FEC frame is mapped. That is, the frame mapper 110 maps the modulation symbols for the third L1 post FEC frame _{to y 3} cells starting from a cell with a cell index of x+y ₁ +y _2. Here, y ₃ may be N _{MOD _ L1post _ per _ FEC} . Accordingly, the frame mapper 110 may map the N _{MOD _ L1post _ _ FEC per} modulation symbol for the first 3 L1 post-FEC frame from the cell after the cell is the 2 L1 post-FEC frame mappings sequentially.

_{In addition, the frame mapper 110 may additionally map three L1 post FEC frames to the remaining N Preamble _ Remaining _ Cells} cells after being mapped to the L1 pre-FEC frame and the 3 L1 post FEC frames in the preamble symbol. In this case, the length of the repeated block in each L1 post FEC frame may be N _{Preamble _ Remaining _ Cells} / N _{L1post _ FECFRAME} , and each of the repeated blocks is mapped to _{each of z 1} , z ₂ , and z _{3 cells.} I can. Here, z ₁ =z ₂ =z ₃ =N _{Preamble_Remaining_Cells} /N _{L1post_FECFRAME} .

Specifically, as shown in FIG. 2, the frame mapper 110 _{copies a block having a length of N Preamble _ Remaining _ Cells} / N _{L1post _ FECFRAME} in the first L1 post FEC frame, and the cell to which the third L1 post FEC frame is mapped. From the next cell of the first L1 post FEC frame, _{copying a block having a length of N Preamble _ Remaining _ Cells} / N _{L1post _ FECFRAME} in the second L1 post FEC frame to copy the repetitive block of the first L1 post FEC frame to the mapped cell. Mapping is performed sequentially from the next cell. _{Then, the frame mapper 110 copies a block having a length of N Preamble_Remaining_Cells} /N _{L1post_FECFRAME} in the third L1 post FEC frame, and sequentially maps from the next cell of the cell to which the repeating block of the second L1 post FEC frame is mapped. .

Meanwhile, in FIG. 2, it has been described that the blocks located at the front end of each L1 post FEC frame, that is, the modulation symbols generated by bits located at the front end of each L1 post FEC frame, are additionally mapped to the remaining cells of the preamble symbol. This is just an example. That is, a block additionally mapped to the remaining cells may be copied at any position in the L1 post FEC frame.

For example, as shown in FIG. 3, a block located at the front end of each L1 post FEC frame may be copied and further mapped to the remaining cells, and as shown in FIG. 4, a block located at the rear end of each L1 post FEC frame is copied and remaining cells 5, a block located in the middle of each L1 post FEC frame may be copied and further mapped to remaining cells. In these cases, the length of the repeated block may be _{N Preamble_Remaining_Cells} /N _{L1post_FECFRAME.}

Meanwhile, referring to FIG. 6, when the number of remaining cells is not an integer multiple of the number of L1 post FEC frames, a method of additionally mapping the L1 post FEC frame to the remaining cells will be described.

However, even in this case, since the method of mapping the L1 pre-FEC frame and the L1 post-FEC frame to the preamble symbol is the same as described with reference to FIG. 2, a detailed description will be omitted.

The frame mapper 110 may additionally map the three L1 FEC frames to the remaining cells after being mapped to the L1 pre-FEC frame and the three L1 post FEC frames in the preamble symbol. In the case of Figure 6, the number N _{preamble _ _ Remaining Cells} of the remaining cells may be equal to N _{preamble _ _ Cells Remaining} = Q × N _{L1po st_ FECFRAME} +2. Accordingly, the length of a block repeated in the first and second L1 post FEC frames is Q+1, and each block may be mapped to _{z 1} cells and z _{2 cells, respectively.} Here, z ₁ =z ₂ =Q+1 can be. In addition, the length of the repeated block in the third L1 post FEC frame is Q, and the corresponding block may be mapped to _{z 3 cells.} Here, z ₃ =Q can be.

In this case, as shown in FIG. 6, the frame mapper 110 copies a block having a length of Q+1 from the first L1 post FEC frame, and sequentially maps from the cell following the cell to which the third L1 post FEC frame is mapped, A block having a length of Q+1 is copied from the second L1 post FEC frame, and the repetitive blocks of the first L1 post FEC frame are sequentially mapped from a cell following the mapped cell. In addition, the frame mapper 110 copies a block having a length of Q in the third L1 post FEC frame and sequentially maps the repetitive block of the second L1 post FEC frame from a cell next to the mapped cell.

Meanwhile, in FIG. 6, it has been described that a block located at the front end of each L1 post FEC frame is additionally mapped to the remaining cells of the preamble symbol, but this is only an example. That is, a block additionally mapped to the remaining cells may be copied at any position in the L1 post FEC frame.

For example, as shown in FIG. 7, a block located at the front end of each L1 post FEC frame may be copied and further mapped to the remaining cells, and as shown in FIG. 8, a block located at the rear end of each L1 post FEC frame is copied and remaining cells The block located in the middle of each L1 post FEC frame as shown in FIG. 9 may be copied and further mapped to the remaining cells. In these cases, the length of the repeated block of the first and second L1 post FEC frames may be Q+1, and the length of the repeated block of the third L1 post FEC frame may be Q.

As described above, in the present invention, the first data and the second data among a plurality of cells constituting one preamble symbol may be mapped, and the second data may be additionally mapped to the remaining cells.

Meanwhile, in the above-described example, when the number of remaining cells is not an integer multiple of the number of second data blocks, the length of the repeated block in at least one of the plurality of second data blocks is repeated in the remaining second data blocks. It was described as being different from the length of the block. This is for filling all remaining cells with second data, and is only an example.

That is, the frame mapper 110 may not fill all remaining cells with the second data.

Hereinafter, a case where the first data is L1 pre-signaling and the second data is L1 post-signaling will be described in more detail by way of example.

Specifically, when a value obtained by dividing the number of remaining cells by the number of L1 post FEC frames is equal to N _{preamble_Remaining_Cells} = Q×N _{L1post _ FECFRAME} +R (R>0), as shown in FIG. 10, the frame mapper 110 is L1 In each post FEC frame, a block having a length of Q may be copied and sequentially mapped to the remaining cells. If the L1 post FEC frame is additionally mapped in this way, R cells remain. In this case, the R cells become dummy cells, and the frame mapper 110 may map zero bits to the R cells.

As described above, according to an embodiment of the present invention, even when the number of remaining cells is not an integer multiple of the number of L1 post FEC frames, a block of the same length is copied in each L1 post FEC frame and additionally mapped to the remaining cells. May be.

Further, in the above-described example, it has been described that a part of each of the second data blocks is additionally mapped from the cell following the cell to which all the second data is mapped, but this is only an example.

That is, the frame mapper 110 may map the first data and one of the plurality of second data blocks to cells in the OFDM symbol, and may additionally map a part of the mapped second data to the next cell. Further, the frame mapper 110 maps the other one of the plurality of second data blocks to a cell next to the cell to which some of the second data blocks are mapped, and adds a part of the other mapped second data block to the next cell. Can be mapped to.

For a more detailed description of this repetition scheme, refer to FIGS. 11 and 12. In FIGS. 11 and 12, for convenience of description, it is assumed that the first data is L1 pre-signaling and the second data is L1 post-signaling.

Meanwhile, FIG. 11 shows a case where the number of remaining cells is an integer multiple of the number of L1 post FEC frames, and the length of a block repeated in each L1 post FEC frame may be _{N preamble_Remaining_Cells} /N _{L1post_FECFRAME.} In addition, FIG. 12 shows a case where the number of remaining cells is not an integer multiple of the number of L1 post FEC frames, and a value obtained by dividing the number of remaining cells by the number of L1 post FEC frames is N _{preamble _ Remaining _ Cells} = Q×N _{L1post _ FECFRAME} +R (R>0) can be satisfied.

The frame mapper 110 maps L1 pre-signaling and one of a plurality of L1 post FEC frames to cells of a preamble symbol. That is, as shown in FIGS. 11 and 12, the frame mapper 110 sequentially maps the L1 pre-FEC frame and the first L1 post-FEC frame to a plurality of cells constituting the preamble symbol.

In addition, the frame mapper 110 copies a block having a length of a predetermined value in the first L1 post FEC frame, and sequentially maps the copied block from the next cell of the cell to which the first L1 post FEC frame is mapped. In this case, the length of the copied block in FIG. 11 may be N _{preamble_Remaining_Cells} /N _{L1post_FECFRAME} , and the length of the copied block in FIG. 12 may be Q+1.

Thereafter, the frame mapper 110 maps the second L1 post FEC frame from a cell next to the cell to which a part of the first L1 post FEC frame is mapped. In addition, the frame mapper 110 copies a block having a length of a predetermined value in the second L1 post FEC frame, and sequentially maps the copied block from the next cell of the cell to which the second L1 post FEC frame is mapped. In this case, the length of the copied block in FIG. 11 may be N _{preamble _ Remaining _ Cells} / N _{L1post _ FECFRAME} , and the length of the copied block in FIG. 12 may be Q+1.

Thereafter, the frame mapper 110 maps the third L1 post FEC frame from a cell next to the cell to which a part of the second L1 post FEC frame is mapped. Further, the frame mapper 110 copies a block having a length of a predetermined value in the third L1 post FEC frame, and sequentially maps the copied block from the next cell of the cell to which the third L1 post FEC frame is mapped. In this case, the length of the copied block in FIG. 11 may be N _{preamble _ Remaining _ Cells} / N _{L1post _ FECFRAME} , and the length of the copied block in FIG. 12 may be Q.

In this way, the frame mapper 110 may perform an iterative scheme by mapping the L1 post FEC frame, copying a block having a predetermined length from the corresponding L1 post FEC frame, and mapping after the mapped L1 post FEC frame. .

Meanwhile, in FIGS. 11 and 12, it has been described that a block located at the front end of each L1 post FEC frame is additionally mapped to the remaining cells of the preamble symbol, but this is only an example. That is, even in the case of FIGS. 11 and 12, a block additionally mapped to the remaining cells may be copied at any position in the L1 post FEC frame.

Meanwhile, in the above-described embodiments, it has been described that the first data and the plurality of second data blocks are mapped to the OFDM symbol, but this is only an example.

That is, when the second data is not segmented, the frame mapper 110 may map one first data and one second data to the preamble symbol.

Even in this case, the frame mapper 110 may additionally map the second data to the remaining cells after the first data and the second data are mapped in the preamble symbol.

Hereinafter, a case where the first data is L1 pre-signaling and the second data is L1 post-signaling will be described as an example.

Specifically, the frame mapper 110 may calculate the number of cells remaining after the L1 free FEC frame and the L1 post FEC frame are mapped. Here, the method of calculating the number of remaining cells is the same as the method described above, except _{that N MOD_L1post_Total} is N _{MOD _ L1post _ Total} = N _{MOD _ L1post _ per _ FEC} in that _{N L1post _ FECFRAME} =1. I can.

Further, the frame mapper 110 may additionally map the L1 post FEC frame to the remaining cells based on the number of remaining cells.

Specifically, when the number of remaining cells is greater than the number of modulation symbols for the L1 post FEC frame, the frame mapper 110 additionally maps the entire L1 post FEC frame to the remaining cells, and then the length of the remaining cells The block having a may be copied in the L1 post FEC frame and further mapped to the remaining cells.

On the other hand, when the number of remaining cells is less than the number of modulation symbols for the L1 post FEC frame, the frame mapper 110 copies a block having a length as much as the number of remaining cells from the L1 post FEC frame and maps the remaining cells. I can.

Returning to FIG. 1, the transmitter 120 may transmit an OFDM frame including a preamble symbol and a data symbol. Specifically, the transmitter 120 may transmit a frame including a preamble to which the first data and the second data are mapped to the reception device 1500 through an allocated channel, including an antenna (not shown). In this case, the frame may further include data symbols in addition to the preamble symbols.

Here, the preamble symbol may be composed of one or a plurality of OFDM symbols, and the data symbol may be composed of a plurality of OFDM symbols.

For example, when the first data is L1 pre-signaling and the second data is L1 post-signaling, broadcast data may be modulated and mapped to a data symbol. In this case, the frame mapper 110 may map the broadcast data to the data symbol, or the transmission device 100 may include a separate component for mapping the broadcast data to the data symbol.

Meanwhile, in the above-described example, it has been described that the first data and the second data are mapped to a preamble symbol among a plurality of OFDM symbols constituting an OFDM frame, and other data (eg, broadcast data) is mapped to a data symbol. It is only.

That is, the first data and the second data may be mapped to a data symbol. That is, when there is a cell to which the first data and the second data can be mapped to not only the preamble symbol but also the data symbol, the first data and the second data may be mapped to the data symbol.

Meanwhile, other data may be mapped to the preamble symbol. That is, broadcast data as well as first data and second data may be mapped to the preamble symbol. In this case, the remaining cells except for cells previously determined for use for other purposes such as pilot and broadcast data are the first data. And a cell to which the second data can be mapped.

In addition, although it has been described that the preamble symbol is composed of one OFDM symbol, this is only an example, and the preamble symbol may be composed of a plurality of OFDM symbols. In this case, the first data and the second data are composed of a plurality of OFDM symbols. It may be mapped to mappable cells among a plurality of cells constituting a symbol.

Meanwhile, as described above, each of the first data and the second data may be modulated and input to the frame mapper 110.

To this end, the transmission device 100 may further include a component for processing the first data and the second data.

For example, when the first data is L1 pre-signaling and the second data is L1 post-signaling, the transmission device 100 performs a component for processing L1 pre-signaling as shown in FIG. 13 and L1 post signaling as shown in FIG. 14. It may further include a component for processing.

Therefore, hereinafter, a method of processing each of the L1 pre-signaling and the L1 post-signaling will be described in detail with reference to FIGS. 13 and 14. However, FIGS. 13 and 14 are only examples, and L1 pre-signaling and L1 post-signaling may each be processed in various ways and provided to the frame mapper 110.

First, the transmission device 100 is a component for processing L1 pre-signaling as shown in FIG. 13A, and includes a zero padding unit 310, a Bose, Chaudhuri, Hocquenghem (BCH) encoder 320, and a low density parity check (LDPC). An encoder 330, a parity interleaver 340, a puncture unit 350, and a modulator 360 may be included.

The zero padding unit 310 pads zero bits in the L1 pre-signaling.

Specifically, the BCH encoder 320 generates a BCH codeword by BCH encoding and outputs it to the LDPC encoder 330, and the LDPC encoder 330 may perform LDPC encoding on the BCH codeword as information word bits. . In this case, in the case of the LDPC code performed by the LDPC encoder 330, information word bits of a certain length are required according to the code rate, so the BCH encoder 320 must generate a BCH codeword having a certain length.

Meanwhile, in order for the BCH encoder 320 to generate a BCH codeword having a predetermined length, BCH encoding must be performed on a predetermined number of bits. On the other hand, since the length of the L1 pre-signaling is fixed (for example, the L1 pre-signaling may consist of 200 bits), the zero padding unit 310 allows the L1 pre-signaling to have the length of the information word bits required in the BCH code. Zero bits are padded in the L1 pre-signaling, and L1 pre-signaling in which the zero bits are padded may be output to the BCH encoder 320.

The BCH encoder 320 performs BCH encoding on the output of the zero padding unit 310. Specifically, the BCH encoder 320 generates BCH parity bits by performing BCH encoding on the input bits as information word bits, and a BCH codeword composed of information word bits and BCH parity bits (i.e., BCH-encoded Bits (encoded bits) may be output to the LDPC encoder 330. Here, the BCH parity bits may consist of 168 bits.

The LDPC encoder 330 performs LDPC encoding on the output of the BCH encoder 320. Specifically, the LDPC encoder 330 generates LDPC parity bits by performing LDPC encoding of input bits into information word bits, and an LDPC codeword composed of information word bits and LDPC parity bits (that is, LDPC-encoded Bits) may be output to the parity interleaver 340.

In this case, the LDPC encoder 330 may generate an LDPC codeword having a predetermined length by performing LDPC encoding based on various code rates.

For example, a BCH encoder 320, information length K _bch of the control bit is 13 872, in the case of the LDPC encoder 330, information length K _ldpc of the control bit is 14040, the LDPC encoder 330 is the sign of the 13/15 LDPC codewords can be generated by performing LDPC encoding at a rate. In this case, the length N _ldpc of the LDPC codeword may be 16200.

In this way, the LDPC codeword generated by the LDPC encoder 330 may be referred to as an L1 pre-FEC frame (or L1 pre-signaling block).

The parity interleaver 340 interleaves the output of the LDPC encoder 330. Specifically, the parity interleaver 340 may perform interleaving on LDPC parity bits among bits constituting the LDPC codeword, and output the parity interleaved LDPC codeword to the puncturing unit 350.

In this case, the parity interleaver 340 may perform parity interleaving based on various interleaving rules.

) 중에서 LDPC 패리티 비트들만을 인터리빙하고, 패리티 인터리빙된 LDPC 코드워드 U=(u₀,u₁,...,

)를 펑처링부(350)로 출력할 수 있다.As an example, the parity interleaver 340 uses the LDPC codeword C = (c ₀ ,c ₁ ,..., output from the LDPC encoder 330) based on Equation 1 below.

), only LDPC parity bits are interleaved, and parity interleaved LDPC codeword U=(u ₀ ,u ₁ ,...,

) May be output to the puncturing unit 350.

Here, Q _ldpc can be 6.

The puncturing unit 350 may puncture some of the bits output from the parity interleaver 340. Here, puncture means that some of the LDPC parity bits are removed and not transmitted, and the punctured LDPC parity bits may not be transmitted.

Specifically, the puncturing unit 350 may puncture some of the LDPC parity bits output from the parity interleaver 340. For example, the puncturing unit 350 may puncture LDPC parity bits _{equal to N punc.}

Also, the puncturing unit 350 may remove zero bits that have been padded by the zero padding unit 310 from among bits output from the parity interleaver 340.

Specifically, the puncturing unit 350 is a zero bit padded by the zero padding unit 310 among bits output from the parity interleaver 340 based on the position and number of zero bits padded by the zero padding unit 310. Can be removed. Meanwhile, when the padded zero bits are encoded and then removed, it is referred to as shortening.

As a result, the puncturing unit 350 may output the remaining bits to the modulator 360 after performing puncturing and shortening. For example, L1 the length of the pre-signaling K _sig, the LDPC parity bits N _{ldpc _ pariry _ L1pre,} popping when the number of bits that are punctured N _punc la, the bits input to the modulator (360) N _L1pre is N _L1pre = K _sig is a +168+ (N _{ldpc parity _ _ L1pre} -N _punc). Here, 168 is the number of bits of the BCH parity bits.

The modulator 360 may modulate the output of the puncturing unit 350. Specifically, the modulator 360 maps bits output from the puncturing unit 350 to constellation points using various modulation methods such as BPSK, QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, etc. Thus, a modulation symbol may be generated, and the modulation symbol may be output to the frame mapper 110.

Here, when the modulation scheme is BPSK, QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, respectively, the number of bits constituting the modulation symbol (or modulated cell) is 1,2,4, respectively. Can be ,6,8,10.

As described above, since the modulator 360 maps bits output from the puncturing unit 350 to constellation points, the modulator 360 may be referred to as a constellation mapper.

Consequently, as described above, _{the N L1pre} bits generated by encoding L1 pre-signaling consisting of _{K sig} bits constitute an L1 free FEC frame, and the L1 free FEC frame is modulated and then modulated by the frame mapper 110. It can be mapped to a preamble symbol.

Meanwhile, in FIG. 13A, it has been described that the zero padding unit 310, the BCH encoder 320, and the LDPC encoder 330 are arranged in the order, but this is only an example. As shown in FIG. 13B, the zero padding unit 310 is a BCH encoder. It may be disposed between 320 and the LDPC encoder 330.

In this case, only the arrangement of the components is different from that described in FIG. 13A, and the operation performed by each component and the parameters used are the same. Therefore, hereinafter, it will be described focusing on the above-described differences.

Referring to FIG. 13B, the BCH encoder 320 may generate a BCH codeword by performing BCH encoding on L1 pre-signaling, and output the generated BCH codeword to the zero padding unit 310.

The zero padding unit 310 pads the BCH codeword with zero bits and outputs the BCH codeword padded with the zero bits to the LDPC encoder 330. For example, if the length of the BCH codeword is N _bch and the length of the information word required for LDPC coding is K _ldpc , the zero padding unit 310 sets _{zero bits as much as K ldpc} -N _bch bits to the BCH codeword. Can be padded on.

The LDPC encoder 330 may generate an LDPC codeword by performing LDPC encoding on a BCH codeword padded with zero bits, and may output the generated LDPC codeword to the parity interleaver 340. In this case, since the BCH codeword padded with zero bits is _{composed of K ldpc} bits, the LDPC encoder 330 performs LDPC encoding on the BCH codeword padded with zero bits to have an LDPC code having a length of _{N ldpc.} You can create words.

Further, although not shown in FIG. 13, the transmission device 100 may further include a scrambler (not shown). A scrambler (not shown) may perform a function of randomizing and outputting input bits. A scrambler (not shown) performing such a function may be disposed before the zero padding unit 310 in the case of FIG. 13A, and may be disposed before the BCH encoder 320 in the case of FIG. 13B.

Meanwhile, the transmission device 100 is a component for processing L1 post signaling as shown in FIG. 14, and includes a segment unit 410, a zero padding unit 420, a BCH encoder 430, an LDPC encoder 440, and a parity interleaver. (450), a puncture unit 460, an interleaver 470, a demux 480, and a modulator 490 may be further included.

The segment unit 410 segments the L1 post signaling. Specifically, since the length of the L1 post signaling is variable, the segment unit 410 segments the L1 post signaling to have a certain number of bits or less, and outputs each of the segmented L1 post signaling to the zero padding unit 420. I can.

The zero padding unit 420 pads zero bits for each segmented L1 post signaling.

Specifically, the BCH encoder 430 generates a BCH codeword by BCH encoding and outputs it to the LDPC encoder 440, and the LDPC encoder 440 may perform LDPC encoding on the BCH codeword as information word bits. . In this case, in the case of the LDPC code performed by the LDPC encoder 440, information word bits of a certain length are required according to the code rate, so the BCH encoder 430 must generate a BCH codeword having a certain length.

Meanwhile, in order for the BCH encoder 430 to generate a BCH codeword having a predetermined length, BCH encoding must be performed on a predetermined number of bits. Accordingly, the zero padding unit 420 pads zero bits in each of the segmented L1 post signaling so that the segmented L1 post signaling has the length of information word bits required in the BCH code, and performs each of the L1 post signaling padded with zero bits. It can be output to the BCH encoder 430.

The BCH encoder 430 performs BCH encoding on the output of the zero padding unit 420. Specifically, the BCH encoder 430 generates BCH parity bits by performing BCH encoding on each of the input bits as information word bits, and a plurality of BCH codewords composed of information word bits and BCH parity bits (i.e. , BCH-encoded bits) may be output to the LDPC encoder 440. Here, the BCH parity bits may consist of 168 bits.

The LDPC encoder 440 performs LDPC encoding on the output of the BCH encoder 430. Specifically, the LDPC encoder 440 generates LDPC parity bits by performing LDPC encoding on each of the input bits as information word bits, and a plurality of LDPC codewords composed of information word bits and LDPC parity bits (i.e. , LDPC-encoded bits) may be output to the parity interleaver 450.

In this case, the LDPC encoder 440 may generate a plurality of LDPC codewords having a predetermined length by performing LDPC encoding based on various code rates.

For example, a BCH encoder 430, information length K _bch of control bit 13 872, if the length of information bits of the LDPC encoder 440 K _ldpc is 14040, the LDPC encoder 440 is the sign of the 13/15 LDPC codewords can be generated by performing LDPC encoding at a rate. In this case, the length N _ldpc of each LDPC codeword may be 16200.

Accordingly, each of the plurality of LDPC codewords output from the LDPC encoder 440 may be referred to as an L1 post FEC frame (or L1 post signaling block).

The parity interleaver 450 interleaves the output of the LDPC encoder 440. Specifically, the parity interleaver 450 may perform interleaving on LDPC parity bits among bits constituting each LDPC codeword, and output each of the parity interleaved LDPC codewords to the puncturing unit 460.

In this case, the parity interleaver 450 may perform parity interleaving based on various interleaving rules.

) 중에서 LDPC 패리티 비트들만을 인터리빙하고, 패리티 인터리빙된 LDPC 코드워드 U=(u₀,u₁,...,

)를 펑처링부(460)로 출력할 수 있다.As an example, the parity interleaver 450 is the LDPC codeword C = (c ₀ ,c ₁ ,..., output from the LDPC encoder 330) based on Equation 2 below.

), only LDPC parity bits are interleaved, and parity interleaved LDPC codeword U=(u ₀ ,u ₁ ,...,

) May be output to the puncturing unit 460.

Here, Q _ldpc can be 24.

The puncturing unit 460 may puncture some of the bits output from the parity interleaver 450. Here, puncture means that some of the LDPC parity bits are removed and not transmitted, and the punctured LDPC parity bits may not be transmitted.

Specifically, the puncturing unit 460 may puncture some of the LDPC parity bits of each of the plurality of LDPC codewords output from the parity interleaver 450. For example, the puncturing unit 460 may puncture LDPC parity bits _{equal to N punc.}

Also, the puncturing unit 460 may remove zero bits that have been padded by the zero padding unit 420 from among bits output from the parity interleaver 450.

Specifically, the puncturing unit 460 applies to the zero padding unit 420 for each of the plurality of LDPC codewords output from the parity interleaver 340 based on the position and number of zero bits padded by the zero padding unit 420. Zero bits that have been padded by can be removed. Meanwhile, when the zero bits that have been padded in this way are encoded and then removed, it is called shortening.

As a result, the puncturing unit 460 may output the remaining bits to the interleaver 470 after performing puncturing and shortening. For example, the length of the segment L1 post-signaling K _sig, LDPC parity bit of N _{ldpc _ pariry _ L1post,} popping when the number of bits that are punctured N _punc la, bit input to the interleaver (470) N _L1post is N _L1post = K _sig is a +168+ (N _{ldpc parity _ _ L1post} -N _punc). Here, 168 is the number of bits of the BCH parity bits.

The interleaver 470 performs interleaving on the output of the puncturing unit 460. Specifically, the interleaver 470 interleaves each of the plurality of LDPC codewords output from the puncturing unit 460 and outputs each of the interleaved LDPC codewords to the demux 480.

In this case, the interleaver 470 may interleave bits output from the puncturing unit 460 using Nc columns consisting of Nr rows.

Specifically, the interleaver 470 writes bits output from the puncturing unit 460 in the column direction from the first column to the Nc-th column, and the bits are written from the first row to the Nr-th row in the row direction. Interleaving can be performed by reading. Accordingly, bits written to the same row in each column are sequentially output, and the order of bits may be rearranged compared to before interleaving.

The demux (or demultiplexer) 480 performs demultiplexing on the output of the interleaver 470.

Specifically, the demux 480 performs bit-to-cell conversion on each LDPC codeword output from the interleaver 470 to convert each LDPC codeword into a cell having a certain number of bits. It can be demultiplexed with (cell).

For example, the demux 480 may sequentially output bits constituting each of the LDPC codewords output from the interleaver 470 to one of a plurality of substreams, convert the LDPC codeword bits into cells, and output them. In this case, bits having the same index in each of the plurality of sub-streams may constitute the same cell.

Here, the number of sub-streams is the same as the number of bits constituting the cell. For example, when the modulation scheme is BPSK, QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, respectively, the number of sub-streams may be 1,2,4,6,8,10, respectively. And the number of cells may be N _L1post , N _L1post /2, N _L1post /4, N _L1post /6, N _L1post /8, and N _L1post /10, respectively.

The modulator 490 may modulate cells output from the demux 480. Specifically, the modulator 490 maps the cells output from the demux 480 to constellation points using various modulation schemes such as BPSK, QPSK, 16-QAM, 64-QAM, 256-QAM, and 1024-QAM. Can be modulated.

Here, when the modulation scheme is BPSK, QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, respectively, the number of bits constituting the modulated cell (ie, modulation symbol) is 1,2,4, respectively. Can be ,6,8,10.

As described above, since the modulator 490 maps cells output from the demux 480 to constellation points, the modulator 490 may be referred to as a constellation mapper.

Consequently, as described above, _{the N L1post} bits generated by encoding the segmented L1 post signaling consisting of _{K sig} bits constitute the L1 post FEC frame. Here, since each of the plurality of segmented L1 post signaling is encoded, in the end, a plurality of L1 post FEC frames may be generated. After each of the plurality of L1 post FEC frames is modulated, a preamble symbol by the frame mapper 110 Can be mapped to.

Meanwhile, in the above-described example, when the L1 post signaling is composed of a certain number or less of bits, the segment unit 410 may output the L1 post signaling without performing a separate segmentation operation. In this case, the L1 post signaling is encoded to configure one L1 post FEC frame.

Meanwhile, in FIG. 14A, it has been described that the zero padding unit 420, the BCH encoder 430, and the LDPC encoder 440 are arranged in the order, but this is only an example. As shown in FIG. 15B, the zero padding unit 420 is a BCH encoder. It may be disposed between 430 and LDPC encoder 40.

In this case, only the arrangement of the components is different from that described in FIG. 14A, and the operation performed by each component and parameters used are the same. Therefore, hereinafter, it will be described focusing on the above-described differences.

Referring to FIG. 14B, the BCH encoder 430 may generate a BCH codeword by performing BCH encoding on segmented L1 post signaling, and may output the generated BCH codeword to the zero padding unit 420.

The zero padding unit 420 pads the BCH codeword with zero bits and outputs the BCH codeword padded with the zero bits to the LDPC encoder 440. For example, if the length of the BCH codeword is N _bch and the length of the information word required for LDPC coding is K _ldpc , the zero padding unit 420 sets _{zero bits as much as K ldpc} -N _bch bits to the BCH codeword. Can be padded on.

The LDPC encoder 440 may generate an LDPC codeword by performing LDPC encoding on a BCH codeword padded with zero bits, and may output the generated LDPC codeword to the parity interleaver 430. In this case, since the BCH codeword padded with zero bits is _{composed of K ldpc} bits, the LDPC encoder 440 performs LDPC encoding on the BCH codeword padded with zero bits to have an LDPC code having a length of _{N ldpc.} You can create words.

Further, although not shown in FIG. 14, the transmission device 100 may further include a scrambler (not shown). A scrambler (not shown) may perform a function of randomizing and outputting input bits. A scrambler (not shown) performing such a function may be disposed between the segment unit 410 and the zero padding unit 420 in the case of FIG. 14A, and the segment unit 410 and the BCH encoder 430 in FIG. 14B. Can be placed in between.

Meanwhile, although the interleaver 470 and the demux 480 described in FIG. 13 are not shown in FIG. 13, an interleaver (not shown) disposed between the puncture unit 350 and the modulator 360 It may further include a demux (not shown).

Hereinafter, a receiving device that receives and processes a signal transmitted from the transmitting device 100 will be described.

The reception device 1500 receives and processes a signal from the transmission device 100. In this case, in the signal received from the transmission device 100, the first data and the second data are mapped to the OFDM symbol, the first data and the second data are mapped in the OFDM symbol, and the second data is additionally mapped to the remaining cells. It may be a signal.

Here, the second data may be composed of a plurality of second data blocks. However, this is only an example, and when the second data is not segmented, the second data may be composed of one data block.

Specifically, the signal received from the transmission device 100 is a signal in which first data and a plurality of second data blocks are mapped to cells in an OFDM symbol, and a part of each of the plurality of second data blocks is additionally mapped to the remaining cells. I can. Here, the length of the second data block additionally mapped to the remaining cells may be calculated based on the number of remaining cells and the number of second data blocks after the first data and the second data block are mapped to the ODFM symbol.

In addition, in the signal received from the transmitting device 100, one of the first data and the plurality of second data blocks is mapped to cells in the OFDM symbol, and a part of the mapped second data block is additionally mapped to the next cell. It could be a signal. In this case, the signal received from the transmission device 100 is mapped to a cell next to the cell to which some of the second data blocks are mapped, and the other one of the plurality of second data blocks is mapped, and a portion of the other mapped second data block. May be a signal additionally mapped to the next cell.

Meanwhile, a method of mapping the first data and the second data to the OFDM symbol in the transmission device 100 has been described above in the description of the transmission device 100.

Meanwhile, the reception device 1500 may process a signal received from the transmission device 100.

Specifically, the reception device 1500 may restore the first data from the received signal. In addition, the receiving device 1500 obtains length information for the second data from the restored first data and calculates the number of second data blocks by using it, and calculates the number of second data blocks and the calculated number of second data blocks within the OFDM symbol. A rule to which the second data is mapped may be obtained based on the number of cells remaining after the first data and the second data are mapped, and the second data may be restored based on the obtained rule.

To this end, the receiving device 1500 may include components such as those of FIGS. 15 to 17. Hereinafter, for convenience of explanation, it is assumed that the first data is L1 pre-signaling and the second data is L1 post-signaling. First, referring to FIG. 15, the receiving device 1500 includes a receiving unit 1510 and a demodulating unit. (1520).

The receiver 1510 receives a signal transmitted from the transmission device 100. To this end, the receiver 1510 may include an antenna (not shown) or the like, and may receive a frame including a preamble symbol to which the first data and the second data are mapped, through an allocated channel.

In this case, the frame may further include data symbols in addition to the preamble symbols. That is, the frame may include a data symbol to which data other than the first data and the second data is mapped, and the data symbol may be composed of a plurality of OFDM symbols. For example, when the first data is L1 pre-signaling and the second data is L1 post-signaling, broadcast data may be mapped to the data symbol.

The demodulation unit 1520 demodulates the signal transmitted by the transmission device 100. Specifically, the demodulator 1520 may generate a value corresponding to the LDPC codeword by demodulating the received signal.

Here, a value corresponding to the LDPC codeword may be expressed as a channel value. There may be various methods of determining a channel value, and for example, may be a method of determining a log likelihood ratio (LLR) value.

Specifically, the LLR value may be expressed as a value obtained by taking a log in the ratio of the probability that the bit transmitted from the transmission device 100 is 0 and the probability that it is 1. Alternatively, the LLR value may be a bit value itself determined according to a hard decision, and the LLR value is a representative value determined according to a section to which the probability that the bit transmitted from the transmitting device 100 is 0 or 1 belongs. It could be.

On the other hand, since the transmitting device 100 modulates each of the L1 pre-signaling and the L1 post-signaling, modulates it, maps the modulated symbol to cells in the preamble symbol, and transmits the signal, the signal received from the receiving device 1500 is L1. An LDPC codeword generated by encoding pre-signaling (ie, an L1 pre-FEC frame) and an LDPC codeword generated by encoding L1 post-signaling (ie, an L1 post-FEC frame) may be included.

Accordingly, the demodulator 1520 may determine LLR values for L1 pre-signaling and L1 post-signaling, respectively.

First, the demodulator 1520 may detect L1 pre-signaling within the OFDM symbol and determine an LLR value for the L1 pre-signaling. Here, the length of the L1 pre-signaling and the location of the cell to which the L1 pre-signaling is mapped may be predefined between the transmitting device 100 and the receiving device 1500.

Meanwhile, the reception device 1500 may restore L1 pre-signaling based on the LLR value for the L1 pre-signaling using the configuration shown in FIG. 16. To this end, the reception device 1500 inserts an LLR as shown in FIG. 16A. A unit 1621, a parity deinterleaver 1622, an LDPC decoder 1623, a BCH decoder 1624, and a depadding unit 1625 may be further included.

The LLR insertion unit 1621 adds a specific value to the output value of the demodulation unit 1610, and outputs this to the parity deinterleaver 1622. In this case, the demodulation unit 1610 may output an LLR value for L1 pre-signaling to the LLR insertion unit 1621.

Specifically, the LLR insertion unit 1621 is a component corresponding to the puncturing unit 350 of the transmission device 100 and performs an operation corresponding to the puncturing unit 350. That is, the LLR insertion unit 1621 may add the LLR values corresponding to the parity bits that have been punctured and the LLR values that have been shortened to the LLR values output from the demodulator 1610. Here, the LLR values corresponding to the punctured bits may be 0, and the LLR values corresponding to the shortened bits may be ∞ or -∞. However, ∞ or -∞ is a theoretical value, and may actually be the maximum or minimum value of the LLR value allowed in the receiving system.

To this end, the reception device 1500 may pre-store information on the number and position of bits that have been punctured by the transmission device 100 or may receive the information from the transmission device 100. In addition, the receiving device 1500 may pre-store information on the number, position, and bit value of bits that have been shortened by the transmitting device 100 or may be provided from the transmitting device 100.

The parity deinterleaver 1622 performs parity deinterleaving on the output value of the LLR insertion unit 1621 and outputs the parity deinterleaving to the LDPC decoder 1623.

Specifically, the parity deinterleaver 1622 is a component corresponding to the parity interleaver 340 of the transmission device 100 and performs an operation corresponding to the parity interleaver 340. That is, the parity deinterleaver 1622 reversely performs the interleaving operation performed by the parity interleaver 340 to deinterleave the LLR values corresponding to the LDPC parity bits among the LLR values output from the LLR inserter 1621. I can.

The LDPC decoder 1623 performs LDPC decoding based on the output value of the parity deinterleaver 1622, and outputs the decoding result value to the BCH decoder 1624.

Specifically, the LDPC decoder 1623 is a component corresponding to the LDPC encoder 330 of the transmission device 100 and performs an operation corresponding to the LDPC encoder 330. For example, the LDPC decoder 1623 performs LDPC decoding by using the LLR value output from the parity deinterleaver 1622 based on an iterative decoding based on a sum-product algorithm. Can be corrected.

Here, the summation algorithm exchanges messages (e.g., LLR values) through edges on the bipartite graph of the message passing algorithm, and calculates an output message from messages input to variable nodes or check nodes. And update algorithm.

The BCH decoder 1624 performs BCH decoding on the output value of the LDPC decoder 1623, and outputs the decoding result value to the depadding unit 1625.

Here, the output value of the LDPC decoder 1623 is composed of L1 pre-signaling bits, zero bits padded with L1 pre-signaling, and BCH parity bits, so that the BCH decoder 1624 uses BCH parity bits. The error may be corrected, and the L1 pre-signaling bits and the zero bits padded in the L1 pre-signaling may be output to the depadding unit 1625.

The depadding unit 1625 may remove zero bits from the output value of the BCH decoder 1624.

Specifically, the depadding unit 1625 is a component corresponding to the padding unit 310 of the transmission device 100 and may perform an operation corresponding to the padding unit 310. That is, the depadding unit 1625 may remove zero bits added by the padding unit 310 from among bits output from the BCH decoder 1624 and output L1 pre-signaling.

In this way, when the transmission device 100 processes and transmits the L1 pre-signaling using the components shown in FIG. 13A, the receiving device 1500 may process the L1 pre-signaling using the components shown in FIG. 16A. have.

However, when the transmission device 100 uses the components shown in FIG. 13B, the reception device 1500 may process L1 pre-signaling using the components shown in FIG. 16B. In this case, only the arrangement of the components is different from that described in FIG. 16A, and the operation performed by each component and parameters used are the same. Therefore, hereinafter, it will be described focusing on the above-described differences.

The LDPC decoder 1623 may output bits generated as a result of decoding to the depadding unit 1625. In this case, bits input to the depadding unit 1625 may include L1 pre-signaling, zero bits padded in the L1 pre-signaling, and BCH parity bits.

The depadding unit 1625 may remove zero bits from bits output from the LDPC decoder 1623 and output them to the BCH decoder 1624.

Accordingly, in that the bits input to the BCH decoder 1624 are composed of zero bits padded with L1 pre-signaling and L1 pre-signaling, the BCH decoder 1624 corrects an error using BCH parity bits, and L1 Pre-signaling can be output.

Meanwhile, when the transmission device 100 uses a scrambler (not shown), although not shown in FIG. 16, the reception device 1500 may further include a descrambler (not shown). The descrambler (not shown) may perform a function of de-randomizing input bits and outputting them. A descrambler (not shown) performing such a function may be disposed after the depadding unit 1625 in the case of FIG. 16A, and may be disposed after the BCH decoder 1624 in the case of FIG. 16B.

In this way, the reception device 1500 may restore L1 pre-signaling from the signal received from the transmission device 100.

Meanwhile, the reception device 1500 may further include an information acquisition unit (not shown) that acquires information on L1 post signaling from L1 pre-signaling.

For example, the information acquisition unit (not shown) may obtain length information for L1 post signaling from L1 pre-signaling, and calculate the number of L1 post FEC frames based thereon.

That is, as described above, the L1 post signaling is segmented to have a certain number of bits or less, and the L1 post FEC frame generated by processing each of the segmented L1 post signaling is transmitted to the receiving apparatus 1500. Accordingly, the information acquisition unit (not shown) may calculate the number of L1 post FEC frames according to the length of the L1 post signaling based on a segmentation rule predefined between the transmitting device 100 and the receiving device 1500. have.

In addition, the information acquisition unit (not shown) is based on the calculated number of L1 post-FEC frames and the number of remaining cells after L1 pre-signaling and L1 post-signaling are mapped within the OFDM symbol, and information on the rule to which the L1 post signaling is mapped. Can be obtained.

For example, the information on the rule to which the L1 post FEC frame is mapped is calculated by dividing the number of cells remaining after L1 pre-signaling and a plurality of L1 post FEC frames are mapped in the OFDM symbol by the number of L1 post FEC frames and the remainder. It may be determined, and may include information on the length and number of L1 post FEC frames additionally mapped to the remaining cells. Meanwhile, in connection with this, it has been described in detail in the description section related to the transmission device 100.

Meanwhile, the demodulator 1520 may determine an LLR value for L1 post signaling within an OFDM symbol based on information on a rule to which L1 post signaling is mapped.

In particular, as described above, the transmission device 100 additionally maps and transmits L1 post signaling to the remaining cells of the preamble symbol. Accordingly, the demodulator 1520 may determine the LLR value for the L1 post signaling by summing the LLR value determined for the L1 post signaling additionally mapped to the LLR value determined for the L1 post signaling.

For example, it is assumed that L1 post signaling is composed of first and second L1 post FEC frames.

In this case, the demodulator 1520 determines LLR values for bits constituting each of the modulation symbols included in the first L1 post FEC frame, and additionally determines each of the modulation symbols included in the mapped first L1 post FEC frame. LLR values for the constituent bits may be determined, and the LLR values for the first L1 post FEC frame may be determined by summing each of these LLR values. Further, the demodulator 1520 determines LLR values for bits constituting each of the modulation symbols included in the second L1 post FEC frame, and additionally configures each of the modulation symbols included in the mapped second L1 post FEC frame. LLR values for bits to be used may be determined, and the LLR values for the second L1 post FEC frame may be determined by summing each of these LLR values.

As described above, in the present invention, when the LLR value for L1 post signaling is determined, the additionally transmitted LLR values for L1 post signaling are added, so that the reliability of the bits constituting the corresponding modulation symbol can be improved.

Meanwhile, the reception device 1500 may restore the L1 post signaling based on the LLR value for the L1 post signaling using the configuration shown in FIG. 17. To this end, as shown in FIG. 17, the receiving device 1500 includes a mux 1631, a deinterleaver 1632, an LLR insertion unit 1633, a parity deinterleaver 1634, an LDPC decoder 1635, a BCH decoder 1636, and A depadding unit 1637 and a combiner 1638 may be further included.

The mux (or multiplexer) 1631 multiplexes the output value of the demodulator 1610 and outputs the multiplexed value to the deinterleaver 1632. In this case, the demodulator 1610 may output an LLR value for L1 post signaling to the mux 1631.

Specifically, the mux 1631 is a component corresponding to the demux 480 of the transmission device 100 and may perform an operation corresponding to the demux 480. That is, the mux 1631 may convert the output value of the demodulator 1610 cell-to-bit to output an LLR value in bit units.

The deinterleaver 1632 may deinterleave the output value of the mux 1631 and output it to the LLR insertion unit 1633.

Specifically, the deinterleaver 1632 is a component corresponding to the interleaver 470 of the transmission device 100 and may perform an operation corresponding to the interleaver 470. That is, the deinterleaver 1632 may deinterleave the output value of the mux 1631 by reversely performing the interleaved operation performed by the interleaver 470.

The LLR insertion unit 1633 adds a specific value to the output value of the deinterleaver 1632 and outputs this to the parity deinterleaver 1634.

Specifically, the LLR insertion unit 1633 is a component corresponding to the puncturing unit 460 of the transmission device 100 and performs an operation corresponding to the puncturing unit 460. That is, the LLR insertion unit 1633 may add the LLR values corresponding to the parity bits that have been punctured and the LLR values that have been shortened to the LLR values output from the deinterleaver 1632. Here, the LLR values corresponding to the punctured bits may be 0, and the LLR values corresponding to the shortened bits may be ∞ or -∞. However, ∞ or -∞ is a theoretical value, and may actually be the maximum or minimum value of the LLR value allowed in the receiving system.

To this end, the reception device 1500 may pre-store information on the number and position of bits that have been punctured by the transmission device 100 or may receive the information from the transmission device 100. In addition, the receiving device 1500 may pre-store information on the number, position, and bit value of bits that have been shortened by the transmitting device 100 or may be provided from the transmitting device 100.

The parity deinterleaver 1634 performs parity deinterleaving on the output value of the LLR insertion unit 1633 and outputs the parity deinterleaving to the LDPC decoder 1635.

Specifically, the parity deinterleaver 1634 is a component corresponding to the parity interleaver 450 of the transmission device 100 and performs an operation corresponding to the parity interleaver 450. That is, the parity deinterleaver 1634 reversely performs the interleaving operation performed by the parity interleaver 450 to deinterleave the LLR values corresponding to the LDPC parity bits among the LLR values output from the LLR insertion unit 1633. I can.

The LDPC decoder 1635 performs LDPC decoding based on the output value of the parity deinterleaver 1634, and outputs the decoding result value to the BCH decoder 1636.

Specifically, the LDPC decoder 1635 is a component corresponding to the LDPC encoder 440 of the transmission device 100 and performs an operation corresponding to the LDPC encoder 440. For example, the LDPC decoder 1635 may correct an error by performing LDPC decoding using an LLR value output from the parity deinterleaver 1634 based on an iterative decoding method based on a sum-multiplication algorithm.

The BCH decoder 1636 performs BCH decoding on the output value of the LDPC decoder 1635, and outputs the decoding result value to the depadding unit 1637.

Here, the output value of the LDPC decoder 1635 is composed of segmented L1 post signaling bits, zero bits padded in the segmented L1 post signaling, and BCH parity bits. The error may be corrected using the bits, and the segmented L1 post signaling bits and the zero bits padded in the segmented L1 post signaling may be output to the depadding unit 1637.

The depadding unit 1637 may remove zero bits from the output value of the BCH decoder 1636 and may output them to the combiner 1638.

Specifically, the depadding unit 1637 is a component corresponding to the padding unit 420 of the transmission device 100 and may perform an operation corresponding to the padding unit 420. That is, the depadding unit 1637 may remove zero bits added by the padding unit 420 from among bits output from the BCH decoder 1637 and output segmented L1 post signaling.

On the other hand, in that the LLR value for L1 post signaling corresponds to segmented L1 post signaling, the above-described configuration processes the LLR value for L1 post signaling multiple times (that is, as many as the number of segmented L1 post signaling). Accordingly, a plurality of L1 post signaling bit strings output from the depadding unit 1637 may correspond to a plurality of segmented L1 post signaling.

Accordingly, the combiner 1638 performs desegmentation on the output value of the depadding unit 1637.

Specifically, the combiner 1638 is a component corresponding to the segment unit 410 of the transmission device 100 and may perform an operation corresponding to the segment unit 410. That is, the combiner 1638 may de-segment the segmented L1 post signaling and output the L1 post signaling before segmentation.

Meanwhile, when the transmission device 100 processes and transmits the L1 post signaling using the components shown in FIG. 14A, the reception device 1500 may process the L1 pre-signaling using the components shown in FIG. 17A. .

However, when the transmission device 100 uses the components shown in FIG. 14B, the reception device 1600 may process L1 post signaling using the components shown in FIG. 17B. In this case, only the arrangement of the components is different from that described in FIG. 17A, and the operation performed by each component and parameters used are the same. Therefore, hereinafter, it will be described focusing on the above-described differences.

The LDPC decoder 1635 may output bits generated as a result of decoding to the depadding unit 1637. In this case, bits input to the depadding unit 1637 may include segmented L1 post signaling, zero bits padded to segmented L1 post signaling, and BCH parity bits.

The depadding unit 1637 may remove zero bits from bits output from the LDPC decoder 1635 and output them to the BCH decoder 1636.

Accordingly, in that the bits input to the BCH decoder 1636 are composed of segmented L1 post signaling and zero bits padded in the segmented L1 post signaling, the BCH decoder 1636 uses BCH parity bits to detect errors. It can correct and output segmented L1 post signaling.

Meanwhile, when the transmission device 100 uses a scrambler (not shown), although not shown in FIG. 17, the reception device 1500 may further include a descrambler (not shown). The descrambler (not shown) may perform a function of de-randomizing input bits and outputting them. A descrambler (not shown) performing such a function may be disposed between the depadding unit 1637 and the combiner 1638 in the case of FIG. 17A, and the BCH decoder 1636 and the combiner in FIG. 17B. Can be placed between (1638).

In this way, the reception device 1500 may restore L1 post signaling from a signal received from the transmission device 100.

18 is a flowchart illustrating a data mapping method of a transmission device according to an embodiment of the present invention.

The first data and the second data are mapped to a preamble or a data OFDM symbol (S1810).

Then, a frame including a preamble or data OFDM symbol is transmitted (S1820).

Meanwhile, in step S1810, the first data and the second data are mapped in the OFDM symbol, and the second data may be additionally mapped to the remaining cells. Here, the second data may be composed of a plurality of second data blocks.

Specifically, in step S1810, the first data and the plurality of second data blocks are mapped to cells in the OFDM symbol, the first data and the second data block are mapped to the ODFM symbol, and the number of remaining cells and the number of second data blocks The length of the second data block to be additionally mapped may be calculated based on and a part of each of the plurality of second data blocks may be additionally mapped to the remaining cells based on the calculated block length.

Further, in step S1810, one of the first data and the plurality of second data blocks may be mapped to cells in the OFDM symbol, and a part of the mapped second data block may be additionally mapped to the next cell. In this case, in step S1810, the other one of the plurality of second data blocks is mapped to a cell next to the cell to which some of the second data blocks are mapped, and a part of the other mapped second data block is additionally mapped to the next cell. can do.

Meanwhile, a method of mapping the first data and the second data has been described above together with the transmission device 100.

19 is a flowchart illustrating a signal processing method of a reception device according to an embodiment of the present invention.

Receives a signal from the transmission device 100 (S1910)

Then, the received signal is processed (S1920).

In this case, in the signal received from the transmitting device, the first data and L1 second data are mapped to a preamble or data OFDM symbol, the first data and second data are mapped in the OFDM symbol, and second data is additionally added to the remaining cells. It may be a mapped signal. Here, the second data may be composed of a plurality of second data blocks.

Specifically, the signal received from the transmission device may be a signal in which the first data and the plurality of second data blocks are mapped to cells in the OFDM symbol, and a part of each of the plurality of second data blocks is additionally mapped to the remaining cells. Here, the length of the additionally mapped second data block is a second data block that is additionally mapped based on the number of remaining cells and the number of second data blocks after the first data and the second data block are mapped to the ODFM symbol. The length of can be calculated.

In addition, the signal received from the transmission device may be a signal in which one of the first data and the plurality of second data blocks is mapped to cells in the OFDM symbol, and a part of the mapped second data block is additionally mapped to the next cell. In this case, the signal received from the transmission device 100 is mapped to a cell next to the cell to which some of the second data blocks are mapped, and the other one of the plurality of second data blocks is mapped, and a portion of the other mapped second data block. May be a signal additionally mapped to the next cell.

Meanwhile, a method of mapping the first data and the second data has been described above together with the transmission device 100, and the reception device 1500 that receives and processes such a signal has also been described above.

Meanwhile, a non-transitory computer readable medium in which a program for sequentially performing a data mapping method and a data processing method according to the present invention is stored may be provided.

The non-transitory readable medium refers to a medium that stores data semi-permanently and can be read by a device, rather than a medium that stores data for a short moment, such as a register, a cache, and a memory. Specifically, the above-described various applications or programs may be provided by being stored in a non-transitory readable medium such as a CD, DVD, hard disk, Blu-ray disk, USB, memory card, ROM, or the like.

In addition, although a bus is not shown in the above-described block diagram showing the transmitting device and the receiving device, communication between components in the transmitting device and the receiving device may be performed through a bus. In addition, each device may further include a processor such as a CPU or a microprocessor that performs the various steps described above.

In addition, although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the technical field to which the present invention belongs without departing from the gist of the present invention claimed in the claims. In addition, various modifications are possible by those of ordinary skill in the art, and these modifications should not be understood individually from the technical spirit or prospect of the present invention.

100: transmitting device 110: frame mapper
120: transmitter

Claims (22)

In the data mapping method,
Mapping a plurality of second data blocks generated by segmenting the first data and the second data onto an OFDM symbol; And
Transmitting a frame including the OFDM (Orthogonal Frequency Division Multiplexing) symbol; Including,
The mapping step,
And further mapping at least a portion of each of the plurality of second data blocks to cells remaining after the first data and the plurality of second data blocks are mapped in the OFDM symbol. delete The method of claim 1,
The mapping step,
The first data and the plurality of second data blocks are mapped to cells in the OFDM symbol, and the number of cells remaining after the first data and the plurality of second data blocks are mapped to the OFDM symbol, and the plurality of second data blocks are mapped to the OFDM symbol. 2 A length of a second data block to be additionally mapped is calculated based on the number of data blocks, and a part of each of the plurality of second data blocks is additionally mapped to remaining cells based on the calculated length. Data mapping method. The method of claim 1,
The mapping step,
And mapping one of the first data and the plurality of second data blocks to cells in the OFDM symbol, and further mapping a part of the mapped second data block to a next cell. The method of claim 4,
The mapping step,
Mapping another one of the plurality of second data blocks to a cell next to a cell to which the partial second data block is mapped, and additionally mapping a part of the other mapped second data block to a next cell. Data mapping method. In the transmission device,
A frame mapper for mapping a plurality of second data blocks generated by segmenting the first data and the second data onto OFDM symbols; And,
Includes; a transmitter for transmitting a frame including the OFDM symbol,
The frame mapper,
And further mapping at least a portion of each of the plurality of second data blocks to cells remaining after the first data and the plurality of second data blocks are mapped in the OFDM symbol. delete The method of claim 6,
The frame mapper,
The first data and the plurality of second data blocks are mapped to cells in the OFDM symbol, and the number of cells remaining after the first data and the second data block are mapped to the OFDM symbol and the number of the second data blocks are Transmission, characterized in that the length of the second data blocks to be additionally mapped based on the number is calculated, and a part of each of the plurality of second data blocks is additionally mapped to the remaining cells based on the calculated length of the block. Device. The method of claim 6,
The frame mapper,
And mapping one of the first data and the plurality of second data blocks to cells in the OFDM symbol, and further mapping a part of the mapped second data block to a next cell. The method of claim 9,
The frame mapper,
Mapping another one of the plurality of second data blocks to a cell next to a cell to which the partial second data block is mapped, and additionally mapping a part of the other mapped second data block to a next cell. Transmitting device. In the data processing method of the receiving device,
Receiving a signal from a transmitting device; And,
Including; processing the received signal;
The signal received from the transmitting device,
A plurality of second data blocks generated by segmenting the first data and second data are mapped to an OFDM symbol, and the first data and the plurality of second data blocks are mapped in the OFDM symbol, and the plurality of second data blocks are mapped to the remaining cells. A data processing method, wherein at least a portion of each of the second data blocks is an additionally mapped signal. delete The method of claim 11,
The signal received from the transmitting device,
The first data and the plurality of second data blocks are mapped to cells in the OFDM symbol, and a part of each of the plurality of second data blocks is a signal additionally mapped to remaining cells,
The length of the additionally mapped second data block,
And the first data and the second data block are mapped to the OFDM symbol and calculated based on the number of remaining cells and the number of second data blocks. The method of claim 11,
The signal received from the transmitting device,
One of the first data and the plurality of second data blocks is mapped to cells in the OFDM symbol, and a part of the mapped second data block is a signal additionally mapped to a next cell. . The method of claim 14,
The signal received from the transmitting device,
The other one of the plurality of second data blocks is a signal mapped to a cell next to the cell to which the partial second data block is mapped, and a part of the other mapped second data block is additionally mapped to the next cell. Data processing method, characterized in that. In the receiving device,
The receiving device receives and processes a signal from the transmitting device,
The signal received from the transmitting device,
A plurality of second data blocks generated by segmenting the first data and the second data are mapped to an OFDM symbol, and at least a portion of each of the first data and the plurality of second data blocks is mapped in the OFDM symbol, and the remaining cells The reception device, characterized in that the second data is a signal additionally mapped to. delete The method of claim 16,
The signal received from the transmitting device,
The first data and the plurality of second data blocks are mapped to cells in the OFDM symbol, and a part of each of the plurality of second data blocks is a signal additionally mapped to remaining cells,
The length of the additionally mapped second data block,
And the first data and the second data block are mapped to the OFDM symbol and are calculated based on the number of remaining cells and the number of the second data blocks. The method of claim 16,
The signal received from the transmitting device,
And one of the first data and the plurality of second data blocks is mapped to cells in the OFDM symbol, and a part of the mapped second data block is a signal further mapped to a next cell. The method of claim 19,
The signal received from the transmitting device,
The other one of the plurality of second data blocks is a signal mapped to a cell next to the cell to which the partial second data block is mapped, and a part of the other mapped second data block is additionally mapped to the next cell. Receiving device, characterized in that. The method of claim 1,
The mapping step,
When the number of remaining cells is an integer multiple of the number of the plurality of second data blocks, a data block is obtained from each of the plurality of second data blocks, and the obtained data blocks are additionally mapped to the remaining cells,
The data mapping method, characterized in that the lengths of the acquired data blocks are the same. The method of claim 1,
The mapping step,
When the number of remaining cells is not an integer multiple of the number of the plurality of second data blocks, a data block is obtained from each of the plurality of second data blocks, and the obtained data blocks are additionally mapped to the remaining cells. ,
The data mapping method, wherein the length of at least one data block among the acquired data blocks is different from the length of the other data blocks.

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