CN101034951A - Implementation method for in-Turbo code interweaver - Google Patents
Implementation method for in-Turbo code interweaver Download PDFInfo
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- CN101034951A CN101034951A CNA2007100911565A CN200710091156A CN101034951A CN 101034951 A CN101034951 A CN 101034951A CN A2007100911565 A CNA2007100911565 A CN A2007100911565A CN 200710091156 A CN200710091156 A CN 200710091156A CN 101034951 A CN101034951 A CN 101034951A
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Abstract
The invention discloses a Turbo code interleaver implementing method, firstly calculating interleave matrix parameters including number of rows, minimum rank, and number of columns of the interleave matrix and the primitive root corresponding to the minimum rank; making interleave matrix row-inside displacement; finally generating interleave address. And it simplifies the steps of interleaver implementation, and advances a blank-row pre-deleting technique and further saves the required storage resources, and it adopts a new row-inside replacement mode and mainly implements main operations in iterative computation or table-look-up mode. In hardware implementation, it avoids all modulus and multiply-divide operations so as to real-time implement interleave/ de-interleave address.
Description
Technical field
The present invention relates to channel coding-decoder technical field in the mobile communication system, relate in particular to a kind of Turbo code interleaver implementing method.
Background technology
Because superior error code of Turbo code and mistake piece performance, from 1993 by C.Berrou, A.Glavieux and P.Thitimajshiwa three people since proposing in the ICC international conference, have been subjected to global communication and information theory correlative study personnel's extensive concern first at once.At present, Turbo code is adopted by a plurality of communication standardization tissues, write among the related communication standard of its issue, wherein typical example is 3-G (Generation Three mobile communication system) 3GPP WCDMA and 3GPP2 cdma2000, both all adopt Turbo code as chnnel coding, to realize high-quality broadband signal transmission.
One code interleaver is arranged in the Turbo code, and this interleaver is the key point of Turbo code superior performance.Usually, interleaver roughly can be divided into two classes, and a class is a random interleaving, and another kind of then is that certainty interweaves.Random interleaving is meant that interleaving mode produces at random, the performance of random interleaving is optimum theoretically, but owing to whole interleaver information need be sent to decoder, could realize correct decoding, thereby taken system bandwidth, coding and efficiency of transmission have been reduced, not too suitable practical application.Interweaving property of certainty is meant that interleaving mode is deterministic, and receiving-transmitting sides all can be known interleaving scheme in advance, need not the mutual interleaving mode information of receiving-transmitting sides, thereby have higher coding and transfer efficient, be adapted at using in the mobile communication system.
The simplest certainty interleaving scheme is a block interleaving, and promptly usually said simple row is write row and read mode, though implement simple, degree uniformity coefficient deficiency at random, decoding effect is very poor.What 3GPP adopted is deterministic Interleaver, is referred to as the prime number interleaver, during this realizes with the weaving length scope of broad, divide several different sections, adopt a mother to interweave in each section, female interleaver difference of different sections, the sub-interleaver in the same section is produced by same female device of handing over.The uniformity coefficient of the degree at random deficiency that this implementation had both avoided certainty to interweave has also avoided random interleaving to waste the shortcoming of system bandwidth simultaneously, is particularly suitable for adopting in the mobile communication system.
Realize that the simplest way of Turbo code interleaver is, all interlace modes are stored among the ROM, this method needs a large amount of ROM, the hardware resource that takies is too much, 3-G (Generation Three mobile communication system) particularly, may need to support global roaming, WCDMA and all interlace modes of cdma2000 are all write among the ROM, can cause the huge waste of hardware resource undoubtedly.
Summary of the invention
The present invention proposes a kind of Turbo code interleaver implementing method, can under the situation of using less resource, generate the reconciliation interleaving address that interweaves in real time.
For this reason, the present invention has adopted following technical scheme:
A kind of Turbo code interleaver implementing method may further comprise the steps:
A, calculate the interleaver matrix parameter, described interleaver matrix parameter comprises the primitive root of the prime number correspondence of the columns of the line number of interleaver matrix, minimum prime number, interleaver matrix and described minimum;
B, carry out displacement in the ranks in the row of described interleaver matrix;
C, generation interleaving address.
Further, said method also can comprise: may further comprise the steps in the described steps A:
A1, according to the block of information length K, calculate the line number R of described interleaver matrix, if 40≤K≤159, R=5 then,
If 160≤K≤200 or 481≤K≤530, R=10,
Otherwise R=20;
A2, search minimum prime number p, wherein p satisfies formula K≤R * (p+1);
A3, according to the block of information length K, calculate the columns C of described interleaver matrix, if 481≤K≤530, C=p then,
Otherwise as K≤R * (p-1), C=p-1 then,
As R * (p-1)＜K≤R * p, C=p then,
As R * p＜K, then C=p+1;
A4, by tabling look-up, obtain the primitive root v of the prime number p correspondence of described minimum.
Further, said method also can comprise: may further comprise the steps among the described step B:
The basic sequence s (j) of displacement in B1, the structure row;
B2, structure prime number sequence q
i, wherein i is 0 to R-1 integer;
Displacement patterns V in B3, the generation row
i(j), if V
i(j-1)+w
i＜p-1, V
i(j)=V
i(j-1)+w
i,
If V
i(j-1)+w
i〉=p-1, V
i(j)=V
i(j-1)+w
i-p-1, wherein, w
i=q
iMod (p-1), V
i(0)=0, V
i(1)=w
i, i is 0 to R-1 integer, j is 1 to p-1 integer;
Displacement patterns U in B4, the calculating row
i(j), if C=p, then U
i(j)=s (V
i(j)), wherein j is 0 to p-2 integer, U
i(p-1)=0,
If C=p+1, then U
i(j)=s (V
i(j)), wherein j is 0 to p-2 integer, U
i(p-1)=0, U
i(p)=p, and work as K=RC, with U
0(p) and U
0(0) replaces;
If C=p-1, then U
i(j)=s (V
i(j))-1, wherein j is 0 to the integer of p-2.
Further, said method also can comprise: among the described step B1, the basic sequence s (j) of displacement can finish by real-time iterative computation in described structure was capable, s (j)=M (s (j-1)), and wherein j is 0 to p-2 integer,
If M (n-1)+v＜p, M (n)=M (n-1)+v then,
If M (n-1)+v 〉=p, M (n)=M (n-1)+v-p then, wherein n is 1 to p-1 integer,
s(0)＝1，M(0)＝0。
Further, said method also can comprise: among the described step B1, the basic sequence s (j) of displacement can finish by the structure look-up table in described structure was capable.
Further, said method also can comprise: among the described step B2, and described structure prime number sequence q
iBe from prime number primitive root table, select R-1 prime number successively, each prime number q
iSatisfy (p-1) modq
i≠ 0, wherein i is 1 to R-1 integer, and q
0=1.
Further, said method also can comprise: among the described step B2, and described structure prime number sequence q
iBe to satisfy (p-1) modq
i=0 (p, q
i) to making form, in conjunction with prime number primitive root table, finish by the method for tabling look-up.
Further, said method also can comprise: may further comprise the steps among the described step C:
C1, calculating row presumptive address, the initial baseline address a that i is capable
i=iC,, wherein i is 0 to R-1 integer;
The displacement in the ranks of C2, described capable presumptive address, in the ranks b is satisfied in the capable initial baseline address of i after the displacement
i=a
T (i), wherein i is 0 to R-1 integer;
If C3, generation interleaving address are b
i+ U
i(j)＜and K, the buffer zone address y of k the bit in back that interweave
k=b
i+ U
i(j), wherein k is 0 to the integer of K-1.
Adopted technical scheme of the present invention, simplified the performing step of interleaver, the pre-deleting technique of null has been proposed, further saved required storage resources, adopted displacement patterns in the new row, iterative computation is all adopted in main computing or the mode of tabling look-up realizes that hardware has been avoided all delivery and multiplication and division computings in realizing, reaches the real-time generation of interleaving/deinterleaving address.
Description of drawings
Fig. 1 is a software section process chart in this embodiment;
Fig. 2 is a hardware components process chart in this embodiment.
Embodiment
Below in conjunction with accompanying drawing, and technical scheme of the present invention is described further by embodiment.
The implementation method that the present invention adopts software and hardware to combine, under the situation of using less resource, generate in real time and interweave or the deinterleaving address, its core concept is with the code interleaver of length between the 40-5114 bit, at first be divided into female interleaver of several different lengths, construct corresponding sub-interleaver by the pre-deleting technique of null then, and, realize the Turbo code interleaver of given length on this basis by the unnecessary hemistich room of deletion.Interweave and de-interweaving method in the Turbo code of the present invention, its implement device is divided into software and hardware two parts and constitutes, software is mainly realized the calculating of disposable initiation parameter, and then in order to finish the arithmetic operation of repeatability, both realize the generation of interleaving address or deinterleaving address to hardware jointly.
This embodiment is an example with information code element length K=645, and 3GPP Turbo code interleaver technical scheme is described.
Fig. 1 is a software section process chart in this embodiment.As shown in Figure 1, may further comprise the steps:
According to the block of information length K, calculate the line number R of described interleaver matrix, if 40≤K≤159, R=5 then, if 160≤K≤200 or 481≤K≤530, R=10, otherwise R=20, in this embodiment because K=645, so R=20;
Search minimum prime number p, wherein p satisfies formula K≤R * (p+1), can obtain p=37 according to formula;
According to the block of information length K, calculate the columns C of described interleaver matrix, if 481≤K≤530, then C=p, otherwise as K≤R * (p-1), C=p-1 then is as R * (p-1)＜K≤R * p, then C=p, as R * p＜K, C=p+1 then, in this embodiment because K=645, so C=36;
By searching prime number primitive root table (seeing Table 1), obtain the primitive root v of the prime number p correspondence of described minimum, when p=37, v=2.
Table 1
| p | v | p | v | p | v | p | v | p | v |
| 7 | 3 | 47 | 5 | 101 | 2 | 157 | 5 | 223 | 3 |
| 11 | 2 | 53 | 2 | 103 | 5 | 163 | 2 | 227 | 2 |
| 13 | 2 | 59 | 2 | 107 | 2 | 167 | 5 | 229 | 6 |
| 17 | 3 | 61 | 2 | 109 | 6 | 173 | 2 | 233 | 3 |
| 19 | 2 | 67 | 2 | 113 | 3 | 179 | 2 | 239 | 7 |
| 23 | 5 | 71 | 7 | 127 | 3 | 181 | 2 | 241 | 7 |
| 29 | 2 | 73 | 5 | 131 | 2 | 191 | 19 | 251 | 6 |
| 31 | 3 | 79 | 3 | 137 | 3 | 193 | 5 | 257 | 3 |
| 37 | 2 | 83 | 2 | 139 | 2 | 197 | 2 | ||
| 41 | 6 | 89 | 3 | 149 | 2 | 199 | 3 | ||
| 43 | 3 | 97 | 5 | 151 | 6 | 211 | 2 |
Table 2
| q 0＝1 | q 5＝19 | q 10＝41 | q 15＝61 |
| q 1＝7 | q 6＝23 | q 11＝43 | q 16＝67 |
| q 2＝11 | q 7＝29 | q 12＝47 | q 17＝71 |
| q 3＝13 | q 8＝31 | q 13＝53 | q 18＝73 |
| q 4＝17 | q 9＝37 | q 14＝59 | q 19＝79 |
Table 3
| b 0＝684 | b 5＝72 | b 10＝360 | b 15＝36 |
| b 1＝324 | b 6＝180 | b 11＝288 | b 16＝576 |
| b 2＝504 | b 7＝252 | b 12＝468 | b 17＝216 |
| b 3＝144 | b 8＝432 | b 13＝612 | b 18＝540 |
| b 4＝0 | b 9＝648 | b 14＝108 | b 19＝396 |
By prime number sequence q
iCan get, after the deletion null, new sequence q '
iSee Table 4:
Table 4
| q′ 0＝7 | q′ 5＝23 | q′ 10＝47 | q′ 15＝71 |
| q′ 1＝11 | q′ 6＝29 | q′ 11＝53 | q′ 16＝73 |
| q′ 2＝13 | q′ 7＝31 | q′ 12＝59 | q′ 17＝79 |
| q′ 3＝17 | q′ 8＝41 | q′ 13＝61 | |
| q′ 4＝19 | q′ 9＝43 | q′ 14＝67 |
By row presumptive address b
i, after the deletion null, can get new sequence b '
iSee Table 5:
Table 5
| b′ 0＝324 | b′ 5＝180 | b′ 10＝468 | b′ 15＝216 |
| b′ 1＝504 | b′ 6＝252 | b′ 11＝612 | b′ 16＝540 |
| b′ 2＝144 | b′ 7＝432 | b′ 12＝108 | b′ 17＝796 |
| b′ 3＝0 | b′ 8＝360 | b′ 13＝36 | |
| b′ 4＝72 | b′ 9＝288 | b′ 14＝576 |
Table 6
| w 0＝7 | w 5＝23 | w 10＝11 | w 15＝35 |
| w 1＝11 | w 6＝29 | w 11＝17 | w 16＝1 |
| w 2＝13 | w 7＝31 | w 12＝23 | w 17＝7 |
| w 3＝17 | w 8＝5 | w 13＝25 | |
| w 4＝19 | w 9＝7 | w 14＝31 |
The basic sequence of displacement in step 106, the calculating row, basic sequence s (j) can finish by real-time iterative computation, s (j)=M (s (j-1)), wherein j is 0 to 35 integer, if M (n-1)+v＜p, if M (n)=M (n-1)+v then is M (n-1)+v 〉=p, M (n)=M (n-1)+v-p then, wherein n is 1 to p-1 integer, s (0)=1, M (0)=0, perhaps obtain according to look-up table in the 3GPP standard, basic sequence s (j) sees Table 7 in this embodiment:
Table 7
| s(0)＝1 | s(6)＝27 | s(12)＝26 | s(18)＝36 | s(24)＝10 | s(30)＝11 |
| s(1)＝2 | s(7)＝17 | s(13)＝15 | s(19)＝35 | s(25)＝20 | s(31)＝22 |
| s(2)＝4 | s(8)＝34 | s(14)＝30 | s(20)＝33 | s(26)＝3 | s(32)＝7 |
| s(3)＝8 | s(9)＝31 | s(15)＝23 | s(21)＝29 | s(27)＝6 | s(33)＝14 |
| s(4)＝16 | s(10)＝25 | s(16)＝9 | s(22)＝21 | s(28)＝12 | s(34)＝28 |
| s(5)＝32 | s(11)＝13 | s(17)＝18 | s(23)＝5 | s(29)＝24 | s(35)＝19 |
Hardware components is mainly used to realize the arithmetic operation of repeatability, will calculate the parameter of output according to software module, produces interleaving address in real time.Its handling process is operated below the concrete enforcement as shown in Figure 2: hardware is pressed the interior displacement patterns V of row of each row in the leu time calculated column
i(j) and U
i(j), U in fact
i(j) be address offset in the row, with the capable presumptive address b ' after the deletion null
iAfter the addition, if be not on the hemistich room, b ' then
i+ U
i(j) be the output of current effective interleaving address, and change the next effectively interleaving address of calculating over to.Owing to adopted the pre-deleting technique of null, on the diverse location of any adjacent two row, have only a room at most, therefore, hardware can avoid calculated address to be on the hemistich room in realizing easily.
Owing to interweave and deinterleaving can adopt same procedure to realize, so emphasis of the present invention is described the implementation method of interleaver, but its principle and algorithm are equally applicable to deinterleaver.The present invention is divided into software and hardware realization two parts with the realization of interleaver or deinterleaver; software carries out simple and necessary preliminary treatment; hardware generates fast in real time and interweaves or the deinterleaving address; hardware is avoided delivery or multiplication and division computing in realizing fully; what replace then is addition; table look-up and necessary logic; main sequence employing iteration or the mode of tabling look-up obtain; need not to calculate the displacement prime number sequence in the standard; adopt substitute mode in the new row; support that displacement is in the ranks carried out simultaneously in the row; displacement patterns iterative computation in the row proposes the pre-deleting technique of interleaver null.Comprehensive above characteristics, the present invention is under the situation of using less resource, and generation in real time interweaves or the deinterleaving address, has accelerated the data processing speed of system widely, and then has satisfied the requirement of high-speed data communication to system real time.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with the people of this technology in the disclosed technical scope of the present invention; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (8)
1, a kind of Turbo code interleaver implementing method is characterized in that, may further comprise the steps:
A, calculate the interleaver matrix parameter, described interleaver matrix parameter comprises the primitive root of the prime number correspondence of the columns of the line number of interleaver matrix, minimum prime number, interleaver matrix and described minimum;
B, carry out displacement in the ranks in the row of described interleaver matrix;
C, generation interleaving address.
2, a kind of Turbo code interleaver implementing method according to claim 1 is characterized in that steps A further may further comprise the steps:
A1, according to the block of information length K, calculate the line number R of described interleaver matrix, if 40≤K≤159, R=5 then,
If 160≤K≤200 or 481≤K≤530, R=10,
Otherwise R=20;
A2, search minimum prime number p, wherein p satisfies formula K≤R * (p+1);
A3, according to the block of information length K, calculate the columns C of described interleaver matrix, if 481≤K≤530, C=p then,
Otherwise as K≤R * (p-1), C=p-1 then,
As R * (p-1)＜K≤R * p, C=p then,
As R * p＜K, then C=p+1;
A4, by tabling look-up, obtain the primitive root v of the prime number p correspondence of described minimum.
3, a kind of Turbo code interleaver implementing method according to claim 1 is characterized in that step B further may further comprise the steps:
The basic sequence s (j) of displacement in B1, the structure row;
B2, structure prime number sequence q
i, wherein i is 0 to R-1 integer;
Displacement patterns V in B3, the generation row
i(j), if V
i(j-1)+w
i＜p-1, V
i(j)=V
i(j-1)+w
i,
If V
i(j-1)+w
i〉=p-1, V
i(j)=V
i(j-1)+w
i-p-1, wherein, w
i=q
iMod (p-1), V
i(0)=0, V
i(1)=w
i, i is 0 to R-1 integer, j is 1 to p-1 integer;
Displacement patterns U in B4, the calculating row
i(j), if C=p, then U
i(j)=s (V
i(j)), wherein j is 0 to p-2 integer, U
i(p-1)=0,
If C=p+1, then U
i(j)=s (V
i(j)), wherein j is 0 to p-2 integer, U
i(p-1)=0, U
i(p)=p, and work as K=RC, with U
0(p) and U
0(0) replaces;
If C=p-1, then U
i(j)=s (V
i(j))-1, wherein j is 0 to the integer of p-2.
4, a kind of Turbo code interleaver implementing method according to claim 3 is characterized in that, among the step B1, the basic sequence s (j) of displacement can finish by real-time iterative computation in described structure was capable, s (j)=M (s (j-1)), wherein j is 0 to p-2 integer
If M (n-1)+v＜p, M (n)=M (n-1)+v then,
If M (n-1)+v 〉=p, M (n)=M (n-1)+v-p then, wherein n is 1 to p-1 integer, s (0)=1, M (0)=0.
5, a kind of Turbo code interleaver implementing method according to claim 3 is characterized in that, among the step B1, the basic sequence s (j) of displacement can finish by the structure look-up table in described structure was capable.
6, a kind of Turbo code interleaver implementing method according to claim 3 is characterized in that, among the step B2, and described structure prime number sequence q
iBe from prime number primitive root table, select R-1 prime number successively, each prime number q
iSatisfy (p-1) mod q
i≠ 0, wherein i is 1 to R-1 integer, and q
0=1.
7, a kind of Turbo code interleaver implementing method according to claim 3 is characterized in that, among the step B2, and described structure prime number sequence q
iBe to satisfy (p-1) mod q
i=0 (p, q
i) to making form, in conjunction with prime number primitive root table, finish by the method for tabling look-up.
8, a kind of Turbo code interleaver implementing method according to claim 1 is characterized in that step C further may further comprise the steps:
C1, calculating row presumptive address, the initial baseline address a that i is capable
i=iC,, wherein i is 0 to R-1 integer;
The displacement in the ranks of C2, described capable presumptive address, in the ranks b is satisfied in the capable initial baseline address of i after the displacement
i=a
T (i), wherein i is 0 to R-1 integer;
If C3, generation interleaving address are b
i+ U
i(j)＜and K, the buffer zone address y of k the bit in back that interweave
k=b
i+ U
i(j), wherein k is 0 to the integer of K-1.
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