CN106063254B - Bit interleaver and bit deinterleaver - Google Patents
Bit interleaver and bit deinterleaver Download PDFInfo
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- CN106063254B CN106063254B CN201580009823.3A CN201580009823A CN106063254B CN 106063254 B CN106063254 B CN 106063254B CN 201580009823 A CN201580009823 A CN 201580009823A CN 106063254 B CN106063254 B CN 106063254B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/08—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division
- H04N7/0803—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division using frequency interleaving, e.g. with precision offset
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6356—Error control coding in combination with rate matching by repetition or insertion of dummy data, i.e. rate reduction
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6362—Error control coding in combination with rate matching by puncturing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0064—Concatenated codes
- H04L1/0065—Serial concatenated codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/003—Arrangements for allocating sub-channels of the transmission path
- H04L5/0044—Arrangements for allocating sub-channels of the transmission path allocation of payload
- H04L5/0046—Determination of how many bits are transmitted on different sub-channels
Abstract
Provide a kind of method for Bit Interleave.The described method includes: by the set of bita≡{ak: k=0,1,2 ... Npost- l } it is mapped to array B={ Bi,j: i=0,1,2 ... M-1；J=0,1,2 ... N-1 } so that bit akIt is mapped to [I], wherein mod indicates that modulus operator, [II] indicate floor operator, and M and N are constants；At least one of following replacement operator operation: the first replacement operator is executed, including replacing two or more bits in the first bit group of each of one or more first bit groups, wherein pass throughG (1) p={ BI, p: i=0,1,2 ... M-1；P ∈ { 0,1,2 ... N-1 } } define each first bit group；With the second replacement operator, including replacing two or more bits in the second bit group of each of one or more second bit groups, wherein pass throughG (2) q={ BQ, j: j=0,1,2 ... N-1；Q ∈ { 0,1,2 ... M-1 } } define each second bit group；And from B de-mapped bits, to obtain interleaving bits setb≡{bk: k=0,1,2 ... Npost- l } so that bit Bi,jBy demapping to bit bNi+j。
Description
Technical field
This patent disclosure relates generally to a kind of equipment for Bit Interleave and/or than deinterleave, system and or method.Example
Such as, the particular embodiment of the present invention provide a kind of digit broadcasting system for existing and future-generation to physical layer (L1)
Signaling carries out equipment, the system and or method of Bit Interleave, for example, by digital video broadcasting (DVB) project and/or advanced electricity
The system of the viewing system committee (ATSC) exploitation.
Background technique
Digital broadcast technologies allow various types of digital contents (for example, video and audio data) to be distributed to terminal use
Family.Many standards are formulated for this purpose, including the family of standards that ATSC is organized to set up, including 1.0 He of standard ATSC
ATSC 2.0.ATSC DTV (DTV) standard described in various documents (including A/52 and A/53, it may have access to http: //
Www.atsc.org/) by many national (including the U.S., Canada and South Korea) using in terrestrial broadcasting.
Recently, ATSC has begun formulation and is directed to real-time and non real-time television content and data to fixed and mobile device
Transmission method new standard, referred to as ATSC 3.0.As a part of this formulation, ATSC has issued motion collection (CFP)
Document (TG3-S2Doc.#023r20, " Call for Proposals For ATSC-3.0PHYSICAL LAYER, A
Terrestrial Broadcast Standard ", ATSC Technology Group 3 (ATSC 3.0), March 26 in 2013
Day), wherein hard objectives are the technologies for the new physical layer that determination can be merged to create 3.0 standard of ATSC.It is contemplated that ATSC
3.0 systems will be designed to have layer architecture, and propose the generalized hierarchical model for ATSC 3.0.Above-mentioned CFP
Range be not limited to the basal layer of the model, 3.0 physical layer of ATSC (its correspond to ISO/IEC 7498-1 model layer 1 and layer
2)。
Being intended that ATSC 3.0 will not need and existing broadcast system (including ATSC 1.0 and ATSC 2.0) backward compatibility.
However, CFP is pointed out, as long as feasible, standard should utilize and with reference to the existing mark for being found to be satisfactory effective solution
It is quasi-.
It include being formulated and being safeguarded by digital video broadcasting (DVB) project for other existing standards that broadcast digital content is formulated
And the open standard race issued by European Telecommunications Standards Institute (ETSI).One such standard be various documents (including
302 755V1.3.1 of ETSI EN, (" digital video broadcasting (DVB)；For second generation Digital Terrestrial Television Broadcast system (DVB-
T2 frame structure Channel Coding and Modulation) ") and 102 831V1.2.1 (" digital video broadcasting of technical specification ETSI TS
(DVB)；Implementation guide for second generation Digital Terrestrial Television Broadcast system (DVB-T2) ")) described in DVB-T2.
In DVB-T2, as described in Figure 1, data are sent with frame structure.In top layer, frame structure 100 is by superframe 101a-c structure
At, wherein superframe 101a-c is divided into multiple T2 frame 103a-d.Each T2 frame 103a-d, which is subdivided into OFDM symbol, (to be had
When referred to as cell), including multiple leading code signs 105,107a-c are multiple data symbol 109a-e later.In T2 frame
In 103a-d, leading code sign 105,107a-c include the leading code sign 105 of single P1, leading followed by one or more P2
Code sign 107a-c.
P1 symbol 105 positioned at the beginning of T2 frame 103a-d carries 7 bits for being used for signaling, including for identifying P2 symbol
The S1 signaling of the format of number 107a-c and S2 signaling for transmitting specific basic configured transmission with signal.Closely P1 symbol 105
P2 symbol 107a-c later is for fine frequency and Timing Synchronization and channel estimation.P2 symbol 107a-c carries L1 signaling letter
Breath, and can also carry data.L1 signaling is divided into before L1- signaling after signaling and L1-.Signaling includes about T2 frame before L1-
The essential information of structure 100, and signaling after L1- can be received the decode.Signaling provides enough information for receiver after L1-
Come to physical layer channel (PLP) decoding in the T2 frame 103a-d for carrying data.
Before bit is mapped to symbol (cell), bit stream (for example, signaling or data) generally goes through various types
Processing and coding.Usually the bit for carrying various types information (for example, before L1- after signaling, L1- signaling and data) is flowed into
Row different disposal.
Fig. 2 shows the bit-interleaved coded-modulation of the bit stream of signaling and modulation after sender side is used to handle and carries L1-
(BICM) example of chain.BICM chain 200 includes: sectionaliser 201, is K for bit stream to be segmented into sizesigBlock；Add
Device 203 is disturbed, for being scrambled (that is, displacement) to from the bit in each of output of sectionaliser 201 piece；And zero padding device
205, for zero padding from each of output of scrambler 203 piece to obtain size as Kbch(for example, Kbch=7032) filling
Block.
BICM chain 200 further include: Bose-Chaudhuri-Hocquenghem Code device 207, for carrying out BCH volume to from each of output of zero padding device 205 piece
Code, to obtain size as Nbch(it also is indicated as Kldcp(for example, Nbch=Kldcp=7200) Bose-Chaudhuri-Hocquenghem Code block)；LDPC encoder
209, for carrying out LDPC coding to from each of output of Bose-Chaudhuri-Hocquenghem Code device 207 piece, to obtain size as Nldpc(for example, Nldpc=
16200) LDPC encoding block.
BICM chain 200 further include: odd-even interleaver 211, for the LDPC from each of output of LDPC encoder 209 piece
Parity Check Bits are interleaved；And punch 213, for NpuncA LDPC Parity Check Bits are punched.In
In BICM chain 200 on this point, the bit of zero padding is also removed, obtain size be NpostBlock.
BICM chain 200 further include: bit interleaver 215, for carrying out bit friendship to from each of output of punch 213 piece
It knits, the size that Bit Interleave is passed through with acquisition is NpostBlock.
Finally, BICM chain 200 further include: demultiplexer 217, for each process exported from bit interleaver 215
The block of intertexture is demultiplexed；And QAM mapper 219, the bit by demultiplexing for will be exported from demultiplexer 217
It is mapped to qam symbol, wherein the qam symbol be used to generate the OFDM symbol (cell) being used for transmission.
The corresponding chain of receiver-side handles received symbol, to restore signaling bit after L1-.
Alternatively possible preamble structure include before only L1- after signaling and L1- signaling retain there is specific length
The single symbol (for example, OFDM symbol) of (for example, 8K).In this case, for example, being used for the coding of signaling after L1- and beating
Hole pattern can change according to the length of information after the L1- quantity of information bit (that is, after L1-).Code rate and puncturing schemes can quilts
Adjustment is suitable for filling entire single symbol for the input data of any length.
The operation of bit interleaver 215 shown in Fig. 2 is shown in FIG. 3.To include NcColumn and Npost/NcCapable block interleaving
The form of device provides bit interleaver 215.As shown in figure 3, bit is read into bit interleaver 215 by column, and line by line from than
Special interleaver 215 is read, to obtain the sequence to interweave.For example, NcValue can according to used modulation scheme and code rate and
Variation.For example, when using 16-QAM and 1/2 code rate, Nc=8, and when using 64-QAM and 1/2 code rate, NC=12.
Structure shown in Fig. 2 has the advantages that relatively easy.However, this structure has also suffered from performance in some cases
Relatively poor disadvantage.For example, in some cases, it can be possible to the performance loss of 3dB occurs.
It is handed over it is therefore desired to which one kind can mention the high performance bit that is used for while keeping relatively simple structure
It knits and/or the method than deinterleave, equipment and/or system.
Summary of the invention
The purpose of certain exemplary embodiments of the invention be at least be partially solved and/or mitigate it is associated with the prior art
At least one of the problem of connection and/or disadvantage, for example, at least one of the problem of being described herein and/or disadvantage.The present invention
The purposes of certain exemplary embodiments be to provide at least one advantage more than the prior art, for example, the advantages of being described herein
At least one of.
The present invention is limited in the independent claim.Advantageous characteristic is limited in the dependent claims.
An aspect of of the present present invention provides a kind of computer program including instruction or code, wherein described instruction or generation
Code is realized when executed according to the method for any aspect, claim and/or embodiment disclosed herein, system and/or is set
It is standby.Another aspect of the invention provides a kind of machine readable memory for storing this program.
It is other aspects of the present invention, excellent from the detailed description for disclosing exemplary embodiment of the present invention with reference to the accompanying drawing
Point and significant feature will become obvious those skilled in the art.
Detailed description of the invention
From the detailed description carried out with reference to the accompanying drawing, certain exemplary embodiments of the invention and many aspects it is upper
Stating will be more obvious with other aspect, feature and features, in the accompanying drawings:
Fig. 1 is shown used in the DVB-T2 for sending the frame structure of data；
Fig. 2 shows an examples of the BICM chain for handling bit stream
Fig. 3 shows the operation of bit interleaver shown in Fig. 2；
Fig. 4 shows the planisphere of the 64-QAM using Gray mapping scheme；
Fig. 5 shows the functional structure of the bit interleaver of an exemplary embodiment of the present invention；
Fig. 6 a is to FIG. 6d shows that the operations of bit interleaver shown in fig. 5；
Fig. 7 shows the functional structure of the bit deinterleaver of an exemplary embodiment of the present invention；
The system that Fig. 8 shows an exemplary embodiment of the present invention；
Fig. 9 a is the flow chart of the illustrative methods for Bit Interleave of an exemplary embodiment of the present invention；And
Fig. 9 b is the flow chart for the illustrative methods than deinterleave of an exemplary embodiment of the present invention.
Realize optimal mode of the invention
Specific embodiment
The description of exemplary embodiment of the present invention carried out with reference to the accompanying drawings is provided to help comprehensive understanding of the invention,
Wherein, the scope of the present invention is defined by the claims.The description includes various specific details to help the understanding, but these
It will be regarded as merely illustrative.Therefore, those skilled in the art are not it will be recognized that departing from the scope of the present invention
In the case where, it can be to embodiment described herein make various changes and modifications.
Although the same or similar component can be shown in different drawings, referred to by the same or similar label
Fixed the same or similar component.
For clarity and conciseness, technology as known in the art, feature, element, structure, construction, function, operation can be omitted
And/or the detailed description of processing, to avoid fuzzy subject of the present invention.
The term as used herein and word are not limited to literal or standard meaning, but are used only for so that having clearly to the present invention
Chu and consistent understanding.
In the claim of entire description and this specification, word " comprising ", "comprising" and its modification are (for example, " packet
Include ... " and " including ... ") refer to " including but not limited to ", and be not intended to (and not) exclude other feature, element,
Component, entirety, step, processing, operation, function, feature, property and/or their combination.
In the claim of entire description and this specification, term " substantially " refer to stated feature, parameter or
Value does not need accurately to be realized, but can be deviated or be changed with the amount for the effect for not interfering the feature to be intended to provide
(including such as tolerance, measurement error, measurement accuracy limitation and other factors known to those skilled in the art).
In the claim of entire description and this specification, unless the context otherwise requires, otherwise singular includes
Plural number.For example, referring to that " object " includes referring to one or more this objects.
In the claim of entire description and this specification, (wherein, Y is the language of the general type of " Y for X "
Some movements, processing, operation, function, activity or step, and X be for realizing the movement, processing, operation, function, activity or
Some devices of step) it is adapted to be, is configured to or is arranged as to be the device X of Y comprising special (but need not be and be exclusively used in).
In conjunction with certain aspects of the present disclosure, embodiment, example or claim description or disclosed feature, element, component,
Entirety, step, processing, operation, function, feature, property and/or their combination will be understood as being suitable for described herein
What his aspect, embodiment, example or claim, unless being compatible with.
The particular embodiment of the present invention is provided for Bit Interleave and/or than the various technologies of deinterleave (for example, square
Method, equipment and/or system).In a particular embodiment, technique described herein can be implemented in digit broadcasting system (including one
A or more existing and/or future-generation digit broadcasting system, for example, by digital video broadcasting (DVB) project and/or elder generation
Into the system (for example, 3.0 standard of ATSC) of television system committee (ATSC) exploitation) in.However, those skilled in the art will
It will be appreciated that various embodiments provide can be any suitable the present invention is not limited to be used in combination with any particular system or standard
Bit Interleave and/or the technology than deinterleave are used for used in the digit broadcasting system of type.
In a particular embodiment, technique described herein can be used for signaling data (for example, signaling or similar after L1-
The signaling of type) it carries out Bit Interleave and/or compares deinterleave.It will be understood by those skilled in the art, however, that the present invention is not limited to
It is used in combination with any certain types of data, various embodiments, which provide, to be made in the case where the data of any suitable type
It is used for Bit Interleave and/or the technology than deinterleave.
Additionally, this invention is not limited to use in the case where any certain types of data structure or preamble structure.Example
Such as, using preamble structure, preamble structure (single symbol including any suitable type of any suitable type
Or more symbolic constructions) can use in certain embodiments of the invention.
The embodiment of the present invention can be with the shape of any suitable method, system and/or equipment used in digital broadcasting
Formula is realized.For example, specific embodiment can be with mobile portable terminals (for example, mobile phone), handheld apparatus, individual
The form of computer, DTV and/or digital radio broadcasting transmitter and/or receiver apparatus, set-top box etc. is realized.
Any such method, system and/or equipment can be with any suitable existing or future digit broadcasting systems and/or standard
(for example, one or more digit broadcasting systems and/or standard for being mentioned herein) are compatible.
Specific embodiment can be realized in the form of including the system of sender side equipment and receiver-side equipment.It sends
Device side apparatus can be configured to execute the Bit Interleave (and any processing needed further exist for and/or coding) of data, and will
Signal corresponding with the data of Bit Interleave are passed through is sent to receiver-side equipment.Receiver-side equipment can be configured to receive letter
Number, and execute than deinterleave (and any processing and/or decoding needed further exist for).Specific embodiment can only include sending
Device side apparatus only includes receiver-side equipment, or includes the system comprising both sender side equipment and receiver-side equipment.
As described above, the structure shown in Fig. 2 disadvantage relatively poor by performance in some cases.Needle will now be described
To a reason of the disadvantage.
Fig. 4 shows the planisphere of 64-QAM, wherein the value of six bits is mapped to each constellation according to Gray mapping scheme
Point.Use mapping shown in Fig. 4, it can be seen that two most significant bits (MSB) (bit 0 and 1) of the value of six bits determine phase
Answer constellation point falls into which quadrant of constellation.Next two MSB (bit 2 and 3) determine that respective constellation point falls into quadrant
Which sub- quadrant.Finally, most latter two MSB (bit 4 and 5) determination forms which of four constellation points of sub- quadrant and phase
Answer constellation point consistent.
Therefore, the variation of a MSB in two MSB (bit 0 and 1) first corresponds to the position of respective constellation point
Relatively large variation (that is, variation of quadrant).The error of a bit in these bits is caused to need conversely speaking, opposite
High noise level.In contrast, the variation of a MSB in next two MSB (bit 2 and 3) corresponds to corresponding star
The small change (that is, variation of the sub- quadrant of quadrant) of the position of seat point, relatively small noise level can cause conversely speaking,
Error in these bits.Finally, the variation of a MSB in most latter two MSB (bit 4 and 5) corresponds to respective constellation point
Position relatively small change (that is, variation of the constellation point of sub- quadrant), relatively low noise level can cause this conversely speaking,
Error in a little bits.
Above-mentioned principle is also applied for different modulation schemes, QAM including not same order (for example, 16-QAM, 64-QAM,
256-QAM... or 22m- QAM (m=2,3,4 ...)).
It is mapped to 2nEach bit in the value of the n-bit of the constellation point of qam constellation can be considered as respective by n
One bit channel (one-bit channel).Since these respective bit channels are to some extent vulnerable to influence of noise (example
Such as, for the reasons mentioned above), therefore the error rate for given noise level and channel capacity thus can be directed to different letters
Road (that is, different bit) and it is different.Specifically, corresponding to the channel capacity of the channel compared with low order usually less than correspond to compared with
The channel capacity of the channel of high significance bit.For certain modulation schemes (for example, 22m- QAM), multipair channel can have identical or phase
As channel capacity correspond to the letter of multipair bit { 0,1 }, { 2,3 } and { 4,5 } for example, in the example of above-mentioned 64-QAM
Road.
Referring back to Fig. 3, usually from bit interleaver 215 mutually colleague read be mapped to single constellation point bit (for example,
The bit that dotted line frame in Fig. 3 indicates).For example, in the case where the 8 column bit interleaver described in 256-QAM and Fig. 3, from than
8 bits that the uniline of special interleaver 215 is read are generally mapped to single 256-QAM constellation point.It means that phase will be passed through
A same bit channel sends the bit in same column.Further, since bit is read into bit interleaver 215 by column, therefore
Multiple successive bits of incoming bit stream will occupy same column.Therefore, multiple successive bits of incoming bit stream will all pass through phase
Cochannel is sent.This may cause multiple successive bits and is sent by the channel of capacity difference, this is not desired.
The exemplary embodiment of the present invention provides a kind of bit interleavers that can avoid or mitigate the above problem, thus
It keeps improving performance while relatively easy structure.
Fig. 5 shows the functional structure of the bit interleaver of an exemplary embodiment of the present invention.Fig. 6 a to FIG. 6d shows that
The operation of bit interleaver shown in fig. 5.In a particular embodiment, bit interleaver can form a part of BICM chain, for example,
BICM chain shown in Fig. 2.The exemplary system including bit interleaver 500 shown in fig. 5 is shown in FIG. 8.Show in fig. 9 a
The illustrative methods that bit interleaver 500 as shown in Figure 5 executes out.
In following exemplary embodiment, bit interleaver is described according to block interleaver.However, the embodiment of the present invention
It is not limited to realize in the form of block interleaver.For example, in a particular embodiment, it can be with basis and illustrated blocks described herein
The identical whole intertexture mode of the whole intertexture mode of interleaver application executes the replaceable form of Bit Interleave to provide bit
Interleaver.In addition, the behaviour that the row and column of bit interleaver as described herein can be exchanged in alternative embodiments and executed thereon
Make.
In certain exemplary embodiments described herein, input bit sequence is first in a first direction (for example, with by column
Mode) be written in block interleaver.Then, according to one or more first displacement patterns (for example, column are reversed down
Set) one or more column (for example, odd column) of permutated bit interleaver and/or according to one or more second replacement dies
One or more rows of formula (for example, row is by cyclic shift) permutated bit interleaver.Finally, by second direction (for example,
In a manner of line by line) bit is read from bit interleaver obtains output bit sequence.
As shown in figure 5, the bit interleaver 500 of sender side includes interleaver array 501, mapper 503, column permutation device
505, line replacement device 507 and de-mapping device 509.Bit interleaver 500 further includes controller 511, for controlling interleaver array
501, mapper 503, column permutation device 505, line replacement device 507 and de-mapping device 509.
In the illustrated embodiment, column permutation device 505 and line replacement device 507 are illustrated as individual element.However, specific
In embodiment, column permutation device 505 and line replacement device 507 can be implemented as single displacer block.
In addition, the embodiment of the present invention is not limited to exemplary structure shown in fig. 5.For example, in a particular embodiment, than
Special interleaver can be realized in the form of chain structure, wherein bit sequence can pass sequentially through various pieces in chain, be reflected with executing
It penetrates, each operation of column permutation, line replacement and demapping.
In addition, array referred to herein is not necessarily to refer to physical array, but can also refer to mathematically, abstract upper or concept
On array.That is, can define two index variables for the purpose of more clearly or advantageously definition substitution operation,
For example, Bi,j.However, in a particular embodiment, being equivalent to the replacement operator of replacement operator described herein (that is, specific giving
Identical output is generated in the case where input) bit for only storing or handling in a linear fashion can be applied to.
Interleaver array 501 includes that M row and N are arranged, and the unit of M N array is consequently formed, wherein the i-th row jth of array
Column (i=0,1,2 ..., M-l and j=0,1,2 ..., N-l) unit can be represented as Bi,j.Mapper 503 receives input
Bit sequence { ak(k=0,1,2 ...), and by the bit map of input bit sequence to the unit of interleaver array 501.
For example, mapper 503 is in a manner of by column by input bit sequence { akWrite-in interleaver array 501, so that bit akIt is mapped to
Unit Bij, wherein i=k mod M, andWherein, mod indicates modulus operator,Indicate floor
(being rounded downwards) operator.This mapping is shown in Fig. 6 a.
Column permutation device 505 be configured as according to one of one or more displacement patterns displacement interleaver arrays 501 or
Two or more units of more column.For example, column permutation device 505 can be configured to replace all unit (examples of every pth column
Such as, the set of { j } is arranged) so that j mod p=q (wherein, p=1,2,3 ... and q=0,1,2 ..., p-1) it is fixed value.
In the illustrated embodiment, column permutation device 505 is configured as displacement odd column (for example, set of column { j }), so that j mod 2
=1.Unit in displacement pth column (p=0,1,2 ..., N-1) can be considered as displacement and be represented asG (1) p={ BI, pUnit
Unit in group, wherein i=0,1,2 ..., M-1.
The some column of identical displacement patterns displacement or all column and/or usable difference can be used to set for column permutation device 505
Change some column of schema replacement or all column.In the illustrated embodiment, each odd column is replaced using identical displacement patterns.
Any suitable displacement patterns can be used to carry out permutating column for column permutation device 505.For example, position BI, jBit can be set to
Change to position BΠ1(i)j, wherein π1(i) the first permutation function is indicated.For example, in the illustrated embodiment, as shown in Figure 6 b, column
Displacer 505 is configured as flipping upside down the jth column of interleaver array 501, so that in the front position B of column permutationI, jBit
The new position B being displaced to after column permutationI, j'=BM-i-1, j, that is, so that Π1(i)=M-i-1.
Unit that can in any other suitable manner in permutating column.For example, can unit in quasi- randomly permutating column.
As another example, column can be divided into two or more height column by (for example, impartial), and the unit of every height column can basis
Particular permutation mode (for example, being arranged by every height that flips upside down) is independently replaced.
Line replacement device 507 be configured as according to one of one or more displacement patterns displacement interleaver arrays 501 or
Two or more units of more rows.For example, position BI, jBit can be displaced to position BI, π 2 (i), wherein π2(j) table
Show the second permutation function.Replace the unit in q row (q=0,1,2 ..., M-1) can be considered as displacement be represented asG (2) q=
{BQ, jUnit group in unit, wherein j=0,1,2 ..., N-1.Identical displacement patterns can be used to replace for line replacement device 507
Some rows or all rows, and/or different displacement patterns can be used to replace some rows or all rows.
In a particular embodiment, displacement patterns may include displacement.For example, line replacement device 507 can be configured in certain party
All units of particular row are made to shift certain amount of unit upwards (for example, to the left or to the right).In the illustrated embodiment, such as
Shown in Fig. 6 c, row is by cyclic shift, so that the capable of lowest number is not shifted, one unit of next line right shift, next line
Two units of right shift, and so on.More commonly, in the case where using displacement as displacement patterns, line replacement device 507
It is configured as shifting row, so that the position B before line replacementI, jBit be displaced to the new position after line replacement
Bi,j'=Bi,(j+s(i))mod N(that is, making π2(j)=(j+s (i)) mod N), wherein s (i) indicates the letter for being defined as line number i
Several shift amounts (for example, as unit of unit).For example, in the illustrated embodiment, s (i)=i.In alternative embodiments,
Shift amount can be defined in other ways, for example, s (i)=2i or s (i)=- i.
By by above-mentioned columns and rows displacement be applied to interleaver array 501, it can be achieved that performance raising.For example, by making
With not going together (for example, by shifting not going together for intertexture array 501 not for different displacement patterns displacement interleaver arrays 501
Same amount), it can be seen that it is read into the original input bit sequence { a of the same column of interleaver array 501kSuccessive bits exist
It would tend to after line replacement throughout different lines.Therefore, input bit sequence { akSuccessive bits from bit interleaver 500
The bit of output would tend to occupy different bit positions when being mapped to constellation point.Therefore, successive bits would tend to pass through
A bit channel with different channels capacity is sent, so that reduce successive bits will be by holding with relatively low channel
The chance that the channel of amount is sent.
In addition, by the particular column (for example, passing through overturning odd column) of displacement interleaver array 501, such as due to following
Reason is, it can be achieved that further increasing in performance.
In the case where the row of interleaver array 501 shifts and the column of interleaver array 501 are not replaced, such as Fig. 6 d institute
Show, it can be seen that be expert at after being shifted, the bit value for occupying particular column includes that quantity is relatively high multipair with original bit sequence
Arrange { akIn be separated by the corresponding value of value of N-1 position.In addition, the bit value for occupying adjacent column includes after being expert at and being shifted
Quantity is relatively high multipair with original bit sequence { akIn successive value it is corresponding value and it is many to original bit sequence
{akIn be separated by the corresponding value of value of N and N-2 position.
For the above reasons, the bit for occupying same column will be by the identical bit channel with particular channel capacity
It is sent.In addition, for the above reasons, under specific circumstances, the bit for occupying adjacent column will be by with same or similar letter
A different bit channels for road capacity are sent.Therefore, with specific period (for example, with the duplicate original bit of period N)
Sequence { akIn occur data would tend to be sent by the bit channel with same or similar channel capacity.This can
It can will lead to and such data are sent by the channel with relatively low channel capacity, this is not desired.
However, by displacement particular column, for example, occupying the bit value of particular column in a manner of shown in Fig. 6 c and occupying
The bit value of adjacent column include less pair with original bit sequence { akIn consecutive value it is corresponding value and less pair with original
Beginning bit sequence { akIn be separated by the corresponding values of value of N, N-1 and N-2 positions.Therefore, original bit sequence { akIn occur
Cycle data is less likely to be sent by the channel with same or similar bit capacity, so that reducing such data will
The chance sent by the channel with relatively low channel capacity.It can see by comparing Fig. 6 c and Fig. 6 d, column do not have
The case where Fig. 6 d being replaced cause more pairs with original bit sequence { akIn be separated by the corresponding value (In of value of N number of position
Indicated in Fig. 6 d by dotted ellipse shape) it is sent by the channel with same or similar channel capacity.
De-mapping device 509 is configured as to the bit demapping from interleaver array 501, to generate output interleaving bits
Sequence { bk}.For example, de-mapping device, which can be configured to mode line by line, reads bit from interleaver array 501, so that from intertexture
Unit B i, the j demapping of device array 501 goes out to export the bit b of bit sequencek, wherein k=Ni+j.
Column permutation device 505 and line replacement device 507 can be configured in any order operate interleaver array 501.For example,
In some embodiments, column permutation device 505, which can be expert at before the row that displacer 507 replaces interleaver array 501, replaces interleaver
The column of array 501.Optionally, line replacement device 507 can be replaced before the column that column permutation device 505 replaces interleaver array 501 and be handed over
Knit the row of device array 501.In some embodiments, for example, column permutation device 505 and line replacement can be controlled by controller 511
The sequence that device 507 operates interleaver array 501.
A specific example of the Bit Interleave of an exemplary embodiment of the present invention will now be described.In the present embodiment
In, input data has length L-1 and the quantity of column is represented as C.Define the matrix that size is (R (row), C (column)), wherein
R=ceil (L-l/C).First Output matrix M is defined as M (r, c)=input (c*R+ (r-l)).First is shown in Fig. 6 a
One example of Output matrix.For (c mod2 0) the second matrix, is calculated from M according to A (r, c)=M ((R-r) mod R, c)
A.One example of the second Output matrix is shown in figure 6b.Third square is calculated from A according to B (r, c)=A (r, (c+r) mod C)
Battle array B.One example of third Output matrix is shown in fig. 6 c.
In a particular embodiment, one in column permutation device 505 and line replacement device can be only provided, so that only in row and column
One can be replaced.In other embodiments, it is possible to provide both column permutation device 505 and line replacement device 507, wherein alternative
One or both in ground activation and deactivation column permutation device 505 and line replacement device 507.This configuration allow bit interleaver according to
Many different mode operations, comprising: (i) mode that only row is replaced, (ii) only arranges the mode being replaced, (iii) row and column
The mode being all replaced, or the mode that (iv) row and column is not replaced.For example, can be by controller 511 according to any suitable
Condition or criterion select AD HOC.For example, in a particular embodiment, bit sequence { a can be based onkLength (it can quilt
Indicate Npost) carry out selection mode.
Used columns N during the operation that bit interleaver 500 can be configured to vary interleaver array 501.For example,
Mapper 503 and de-mapping device 509 can be configured to map bits to interleaver array 501 certain amount of column and from
The certain amount of column comparison particular solution mapping of interleaver array 501, wherein the certain amount of column can be all available columns
Or the subset of available column.
For example, the operation phase of interleaver array 501 can be selected by controller 511 according to any suitable condition or criterion
Between used columns N.For example, in a particular embodiment, bit sequence { a can be based onkLength NpostTo select columns.Example
Such as, for relatively high value Npost, columns can be equal to the bit number for being mapped to each constellation point (for example, being expressed as 2Nmod-
The N of QAMmod), and for relatively low value Npost, columns can be equal to be mapped to the bit number of each constellation point half (for example,
For 2NmodThe N of-QAMmod/ 2 column).In some embodiments, for particular constellation rank, columns can be independently of NpostValue.Example
Such as, for 16-QAM (Nmod=4), for NpostAll values, columns can be equal to Nmod(=4).
As described above, bit sequence { a can be based at least partially onkLength NpostIt is set to execute column permutation device 505 and row
The selective activation of parallel operation 507 and deactivation, and the selection to the columns used during the operation of interleaver array 501.In
In some embodiments, bit interleaver 500 can be stored comprising instruction for NpostEach value appropriately configured setting (for example,
The activation or deactivation of column permutation device 505 and/or line replacement device 507 and the columns of interleaver array 501) information table.
In some embodiments, for the N of a rangepostValue can be used same configuration setting, in this case, can pass through needle
To the value of each range rather than the setting of each individual value storage configuration simplifies table.In other embodiments, described suitably to match
Receiver-side can be transferred to signal by sender side by installing, for example, using column permutation device 505 and line replacement is corresponded respectively to
A pair of of activation marker of device 507, and indicate the field of the columns of interleaver array 501.
In receiver-side, the bit deinterleaver of the bit interleaver corresponding to sending side is provided.Bit deinterleaver
It is configured as that the bit sequence obtained by demodulation reception symbol sebolic addressing is carried out comparing deinterleave.Fig. 7 is shown according to this hair
The functional structure of the bit deinterleaver of bright exemplary embodiment.It is shown in FIG. 8 including bit deinterleaver shown in Fig. 7
700 exemplary system.The illustrative methods that bit deinterleaver 700 as shown in Figure 5 executes are shown in figure 9b.
As shown in fig. 7, being set than deinterleave 700 including deinterleaver array 701, mapper 703, column permutation device 705, row
Parallel operation 707 and de-mapping device 709.Bit deinterleaver further includes controller 711, for controlling deinterleaver array 701, mapping
Device 703, column permutation device 705, line replacement device 707 and de-mapping device 709.
Deinterleaver array 701 has similar form with the interleaver array 501 of sender side, and including forming M
The M row and N of the unit of × N array arrange.Mapper 703 executes the inverse operation of operation performed by the de-mapping device 509 of sending side.
For example, mapper 703 is configured as bit sequence bkDeinterleaver array 701 is written line by line.
Column permutation device 705 is configured as executing the inverse operation of the operation of the execution of column permutation device 505 of sender side.For example,
Column permutation device 705 is configured as according to the one or more of one or more displacement patterns displacement deinterleaver arrays 701
The unit of column, wherein the displacement patterns that column permutation device 705 uses are the displacement patterns that the column permutation device 505 of sender side uses
Reversing.For example, in the case where the column permutation device 505 of sender side overturns odd column, the column permutation device 705 of receiver-side
Odd column may be reversed.
Similarly, line replacement device 707 is configured as executing the inverse behaviour of the operation of the execution of line replacement device 507 of sender side
Make.For example, line replacement device 707 is configured as one according to one or more displacement patterns displacement deinterleaver arrays 701
Or more row unit, wherein the displacement patterns that line replacement device 707 uses are that the line replacement device 507 of sender side uses
The reversing of displacement patterns.For example, in the case where 50 pairs of line replacement device rows of sender side carry out cyclic shift, receiver-side
Line replacement device 707 can carry out cyclic shift to row, but along the phase of the cyclic shift executed with the line replacement device 507 of sender side
Opposite direction carries out.
The column permutation device 705 and line replacement device 707 of receiver-side according to sender side column permutation device 505 and line replacement device
507 opposite sequence operates deinterleaver array 701.
The inverse operation for the operation that the mapper 503 that de-mapping device 709 executes sender side executes.For example, de-mapping device 709
It is configured as reading bit sequence a by column from deinterleaver array 701k, to obtain the bit sequence by deinterleaving.
With with the similar fashion that is described above for sender side, the column permutation device 705 and line replacement device 707 of receiver-side
It can be configured to be selectively activated and deactivated, and deinterleaver array 701 can be configured to using certain amount of
Column are operated.For example, can be determined in the manner described above using table for configuring column permutation device 705, line replacement device 707 is conciliate
The configuration of interleaver array 701 is arranged, or can be transmitted by sender side signal for configuring column permutation device 705, line replacement
The configuration of device 707 and deinterleaver array 701 is arranged.
It will be understood that the particular embodiment of the present invention can by hardware, software or hardware and software it is any combination of in the form of
To realize.Any such software can be stored with volatibility or nonvolatile memory (for example, such as storage device of ROM)
(in spite of erasable or rewritable), or with memory (such as, such as RAM, storage chip, device or integrated circuit)
Form is stored, or is stored on optically or magnetically readable medium (such as, such as CD, DVD, disk or tape etc.).
It will be understood that storage device and storage medium are suitable for the machine that storage includes one or more programs of instruction
The embodiment of readable memory, wherein described instruction realizes the particular embodiment of the present invention when executed.Therefore, specific reality
Applying example and providing a kind of includes method, equipment or the system required in any one claim for realizing this specification
The program of code and the machine readable memory of this program of storage.It further, can be via any medium (for example, logical
Cross the signal of communication that wired or wireless connection carries) electronics transmits such program, and embodiment uitably includes these.
Although the present invention, the ordinary skill of this field has shown and described referring to the particular embodiment of the present invention
Personnel will be understood that, in the case where not departing from the scope of the present invention defined in the appended claims, can carry out in form and details
Various changes.
Claims (15)
1. a kind of method for Bit Interleave, which comprises
Receive the set of bita≡{ak: k=0,1,2 ... Npost-l}；
By the set of bita≡{ak: k=0,1,2 ... Npost- l } it is mapped to the array B={ B including M row and N columni,j: i=
0,1,2,...M-1；J=0,1,2 ... N-1 } so that bit akIt is mapped toWherein, mod indicates mould
Operator,Indicate floor operator, and M and N are constants；
Execute the operation of at least one of following replacement operator:
First replacement operator, including two in the first bit group of each of one or more first bit groups of displacement or more
Multiple bits, wherein pass throughG (1) p={ BI, p: i=0,1,2 ... M-1；P ∈ { 0,1,2 ... N-1 } } define each first
Bit group；With
Second replacement operator, including two in the second bit group of each of one or more second bit groups of displacement or more
Multiple bits, wherein pass throughG (2) q={ BQ, j: j=0,1,2 ... N-1；Q ∈ { 0,1,2 ... M-1 } } define each second
Bit group；
From B de-mapped bits, to obtain interleaving bits setb≡{bk: k=0,1,2 ... Npost- l } so that bit Bi,jIt is solved
It is mapped to bit bNi+j；And
Export bit setb≡{bk: k=0,1,2 ... Npost- l },
Wherein, the first replacement operator includes: the bit or replacement array B in each column in the odd column of replacement array B
The bit in each column in even column, and by the bit of one or more column to array B flip upside down come
Bit in one or more column of replacement array B,
Wherein, the second replacement operator includes: by replacing in one or more rows q row along line direction shift amount q
Bit.
2. according to the method described in claim 1, wherein, one or more the first bit group be first group setG (1) p: p mod g=h；g∈{1,2,3,...}；h∈{0,1,2,...g-l}}.
3. according to the method described in claim 2, wherein, g=2, h=0 or 1.
4. according to the method described in claim 1, wherein, the first replacement operator includes: by position Bi,pBit permutation to position
Bπl(i),p, wherein πlIt (i) include the first permutation function, wherein πl(i)=M-i-1.
5. according to the method described in claim 1, wherein, the second replacement operator includes: by position Bq,jBit permutation to position
Bq,π2(j), wherein π2It (j) include the second permutation function.
6. according to the method described in claim 5, wherein, π2(j)=(j+s (q)) mod N, wherein s (q) includes shift function,
Wherein, s (q)=q or s (q)=- q.
7. according to the method described in claim 1,
Wherein, the step of mapping includes the set in a manner of by column by bitaThe block interleaver that there is M row and N to arrange is written；
Wherein:
First replacement operator includes: two or more ratios in each column in one or more column for replace block interleaver
It is special；
Second replacement operator includes: two or more ratios in every a line in one or more rows for replace block interleaver
It is special；And
Wherein, the step of demapping includes reading interleaving bits set from block interleaver in a manner of line by lineb。
8. according to the method described in claim 7, wherein, the first replacement operator includes: the bit in the every g column of displacement, wherein
G=l, 2,3 ....
9. according to the method described in claim 8, wherein, the first replacement operator includes: each column or idol replaced in odd column
The bit in each column in ordered series of numbers.
10. according to the method described in claim 7, wherein, the first replacement operator includes: to replace one according to the first permutation function
Or more column in bit.
11. according to the method described in claim 10, wherein, the first permutation function includes: by the bit of one or more column
It flips upside down.
12. according to the method described in claim 7, wherein, the second replacement operator includes: to replace one according to the second permutation function
Or more row in bit.
13. according to the method for claim 12, wherein the second permutation function includes: to move to one or more rows
Position.
14. according to the method for claim 13, wherein the second permutation function includes: to make q row along specific direction shift amount
q。
15. a kind of bit interleaver, comprising:
Mapper, for receiving the set of bita≡{ak: k=0,1,2 ... Npost- l }, and by the set of bita≡{ak:k
=0,1,2 ... Npost- l } it is mapped to the array B={ B including M row and N columni,j: i=0,1,2 ... M-1；J=0,1,
2 ... N-1 }, so that bit akIt is mapped toWherein, mod indicates modulus operator,It indicates
Floor operator, and M and N are constants；
Displacer, for executing at least one of following operation operation:
First replacement operator, including two in the first bit group of each of one or more first bit groups of displacement or more
Multiple bits, wherein pass throughG (1) p={ BI, p: i=0,1,2 ... M-1；P ∈ { 0,1,2 ... N-1 } } define each first
Bit group；With
Second replacement operator, including two in the second bit group of each of one or more second bit groups of displacement or more
Multiple bits, wherein pass throughG (2) q={ BQ, j: j=0,1,2 ... N-1；Q ∈ { 0,1,2 ... M-1 } } define each second
Bit group；And
De-mapping device is used for from B de-mapped bits, to obtain interleaving bits setb≡{bk: k=0,1,2 ... Npost- l }, make
Obtain bit Bi,jBy demapping to bit bNi+j, and export bit setb≡{bk: k=0,1,2 ... Npost- l },
Wherein, the first replacement operator includes: the bit or replacement array B in each column in the odd column of replacement array B
The bit in each column in even column, and by the bit of one or more column to array B flip upside down come
Bit in one or more column of replacement array B,
Wherein, the second replacement operator includes: by replacing in one or more rows q row along line direction shift amount q
Bit.
Applications Claiming Priority (5)
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| GB1403121.5A GB2523363B (en) | 2014-02-21 | 2014-02-21 | Bit interleaver and bit de-interleaver |
| GB1403121.5 | 2014-02-21 | ||
| KR10-2015-0008107 | 2015-01-16 | ||
| KR1020150008107A KR102248750B1 (en) | 2014-02-21 | 2015-01-16 | Bit interleaver and bit de-interleaver |
| PCT/KR2015/001419 WO2015126096A1 (en) | 2014-02-21 | 2015-02-12 | Bit interleaver and bit de-interleaver |
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| CN106063254B true CN106063254B (en) | 2019-11-12 |
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| CN (1) | CN106063254B (en) |
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| KR102325951B1 (en) * | 2015-03-02 | 2021-11-12 | 삼성전자주식회사 | Transmitter and shortening method thereof |
| WO2017209418A2 (en) * | 2016-05-31 | 2017-12-07 | 한국전자통신연구원 | Method and apparatus for non-orthogonal based uplink transmission |
| KR102322497B1 (en) | 2016-05-31 | 2021-11-09 | 한국전자통신연구원 | Non-orthogonal based uplink transmission method and apparatus |
| CN108023663B (en) * | 2016-11-01 | 2021-04-13 | 武汉芯泰科技有限公司 | Deleting method and device based on configurable deleting table |
| US11258535B2 (en) | 2017-06-16 | 2022-02-22 | Lg Electronics Inc. | Method and apparatus for transmitting information |
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| CN101034951A (en) * | 2007-04-10 | 2007-09-12 | 中兴通讯股份有限公司 | Implementation method for in-Turbo code interweaver |
| WO2008156335A2 (en) * | 2007-06-20 | 2008-12-24 | Lg Electronics Inc. | Method of performing interleaving and data transmission apparatus |
| CN102387105A (en) * | 2010-08-30 | 2012-03-21 | 华为技术有限公司 | Modulating method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106063254A (en) | 2016-10-26 |
| GB201403121D0 (en) | 2014-04-09 |
| KR102248750B1 (en) | 2021-05-07 |
| KR20150099396A (en) | 2015-08-31 |
| GB2523363A (en) | 2015-08-26 |
| GB2523363B (en) | 2017-06-28 |
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