GB2523363A

GB2523363A - Bit interleaver and bit de-interleaver

Info

Publication number: GB2523363A
Application number: GB1403121.5A
Authority: GB
Inventors: Belkacem Mouhouche; Alain Mourad; Daniel Ansorregui Lobete; Hongsil Jeong
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2014-02-21
Filing date: 2014-02-21
Publication date: 2015-08-26
Anticipated expiration: 2034-02-21
Also published as: KR102248750B1; GB201403121D0; GB2523363B; CN106063254A; CN106063254B; KR20150099396A

Abstract

Methods for bit interleaving and bit de-interleaving, a bit interleaver, and a bit de-interleaver are described wherein one or more bits within a group (e.g. column or row) of bits in a bit array are permuted (e.g. flipped/shifted) in between the mapping and de-mapping stages to avoid all bits in the group of bits being sent down the same channel/carrier. A method for bit interleaving comprises mapping a set of bits a={ak: k= 0, 1, 2, Npost-1} to an array B={Bi,j: i=0, 1, 2, , M-1; j=0, 1, 2, , N-1} such that bit ak maps to Bk mod M, â””k/MË©, wherein mod denotes the modulo operator, â””Ë©denotes the floor operator, and M and N are constants. The method further comprises performing at least one of: (i) a first permutation operation comprising permuting two or more bits within each of one or more first groups of bits, wherein each first group of bits is defined by G(1)p={Bi,p: i=0, 1, 2, , M-1; pâ‚¬{0, 1, 2, , N-1}}; and (ii) a second permutation operation comprising permuting two or more bits within each of one or more second groups of bits, wherein each second group of bits is defined by G(2) q={Bq,j: j=0, 1, 2, , N-1; qâ‚¬{0, 1, 2, , M-1}}. The method further comprises de-mapping bits from B to obtain an interleaved set of bits b={bk: k= 0, 1, 2, Npost-1} such that bit Bi,j is de-mapped to bit bNi+j. In an embodiment, an input bit sequence is written into a block interleaver in a first direction (e.g. in a column-wise manner). Next, one or more columns (e.g. the odd-numbered columns) of the bit interleaver are permuted according to one or more first permutation patterns (e.g. the columns are flipped upside down) and/or one or more rows of the bit interleaver are permuted according to one or more second permutation patterns (e.g. the rows are cyclically shifted). An output bit sequence is obtained by reading bits from the bit interleaver in a second direction (e.g. in a row-wise manner).

Description

BIT INTERLEAVER AND BIT DE-INTERLEAVER

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates generally to an apparatus, system and/or method for bit interleaving and/or bit de-interleaving. For example, certain embodiments of the present invention provide an apparatus, system and/or method for bit interleaving physical layer (Li) signalling for existing and future generation digital broadcasting systems, for example systems developed by the Digital Video Broadcasting (DVB) Project and/or the Advanced Television Systems Committee (ATSC).

Description of the Related Art

Digital broadcasting techniques allow various types of digital content, for example video and audio data, to be distributed to end users. A number of standards have been developed for this purpose, including a family of standards developed by the ATSC organization, including standards ATSC 1.0 and AlSO 2.0. The ATSC Digital Television (DTV) Standard, described in various documents, including P152 and A/53, available at http://wwatsc.org/, have been adopted for use in terrestrial broadcasting by various countries, including the United States, Canada and South Korea.

Recently, ATSC has begun developing a new standard, known as AlSO 3.0, for a delivery method of real-time and non-real-time television content and data to fixed and mobile devices. As part of this development, ATSC has published a Call for Proposals (CFP) document (TG3-S2 Doc. #023r20, "Call for Proposals For ATSC-3.0 PHYSICAL LAYER, A Terrestrial Broadcast Standard", ATSC Technology Group 3 (ATSC 3.0), 26 March 2013), in which a stated goal is to identify technologies that could be combined to create a new physical layer of an ATSC 3.0 Standard. It is envisaged that the ATSC 3.0 system will be designed with a layered architecture and a generalized layering model for ATSC 3.0 has been proposed. The scope of the aforementioned CFP is limited to the base layer of this model, the ATSC 3.0 Physical Layer, which corresponds to Layers 1 and 2 of the ISO/lEO 7498-1 model.

It is intended that ATSC 3.0 will not require backward compatibility with existing broadcasting systems, including ATSC 1.0 and ATSC 2.0. However, the CFP states that, wherever practicable, the standard shall utilize and reference existing standards that are found to be effective solutions to meet the requirements.

Other existing standards developed for broadcasting digital content include a family of open standards developed and maintained by the Digital Video Broadcasting (DVB) Project and published by the European Telecommunications Standards Institute (ETSI). One such standard is DVB-T2, which is described in various documents, including ETSI EN 302 755 Vi.3.1, ("Digital Video Broadcasting (DVB); Frame structure channel coding and modulation for a second generation digital terrestrial television broadcasting system (DVB-T2)"), and Technical Specification ETSI TS 102 831 Vi.2.i ("Digital Video Broadcasting (DVB); Implementation guidelines for a second generation digital terrestrial television broadcasting system (DVB-T2)").

In DVB-T2, data is transmitted in a frame structure, as illustrated in Figure 1. At the top level, the frame structure 100 consists of super-frames 101 a-c, which are divided into a number of T2-frames 103a-d. Each T2-frame 103a-d is sub-divided into OFDM symbols (sometimes referred to as cells), including a number of preamble symbols 105, 107a-c followed by a number of data symbols 109a-e. In a T2-franie 103a-d, the preamble symbols 105, 107a-c comprise a single P1 preamble symbol 105, followed by one or more P2 preamble symbols 107a-c.

The P1 symbol 105, located at the beginning of a T2 frame 103a-d, carries 7 bits for signalling, including Si signalling used to identify the format of the P2 symbols 107a-c and 32 signalling used to signal certain basic transmission parameters. The P2 symbols 107a-c, immediately following the P1 symbol 105, are used for fine frequency and timing synchronisation and channel estimation. The P2 symbols 107a-c carry Li signalling information, and may also carry data. The Li signalling is divided into Li-pre signalling and Li-post signalling. The Li-pre signalling includes basic information about the T2 frame structure 100, and enables the reception and decoding of the Li-post signalling. The Li-post signalling provides sufficient information for the receiver to decode Physical Layer Pipes (PLP5) within the T2-frames iO3a-d, which carry data.

A bit stream (e.g. signalling or data) typically undergoes various types of processing and encoding before the bits are mapped to symbols (cells). Bit streams carrying different types of information (e.g. Li-pre signalling, Li-post signalling and data) are typically processed differently.

Figure 2 illustrates one example of a Bit Interleaved Coding and Modulation (BICM) chain at the transmitter side for processing a bit stream carrying Li-post signalling. The BICM chain comprises a segmenter 201 for segmenting the bit stream into blocks of size a scrambler 203 for scrambling (i.e. permuting) the bits within each block output from the segmenter 201, and a zero padder 205 for padding each block output from the scrambler 203 with zeros to obtain a padded block of size KbCh (e.g. Kb=7032).

The BICM chain 200 further comprises a BCH encoder 207 for BCH encoding each block output from the zero padder 205 to obtain a BCH encoded block of size Nbth, also denoted Kd (e.g. NbCh=KIdpC=7200), and an LDPC encoder 209 for LDPC encoding each block output from the BCH encoder 207 to obtain an LDPC encoded block of size NIdpC (e.g. NIdCp= 16200).

The BICM chain 200 further comprises a parity interleaver 211 for interleaving the LDPC parity bits of each block output from the LDPC encoder 209, and a puncturer 213 for puncturing of the LDPC parity bits. At this point in the 31CM chain 200, the zero padded bits are also removed, resulting in blocks of size N08.

The BICM chain 200 further comprises a bit interleaver 215 for bit interleaving each block output from the puncturer 213 to obtain bit interleaved blocks of size Finally, the BICM chain 200 further comprises a demultiplexer 217 for demultiplexing each interleaved block output from the bit interleaver 215, and a QAM mapper 219 for mapping the demultiplexed bits output from the demultiplexer 217 to QAM symbols, which are used to generate the OFDM symbols (cells) for transmission.

A corresponding chain at the receiver side processes received symbols to recover the Li-post signalling bits.

Another possible preamble structure comprises a single symbol (e.g. OFDM symbol) having a certain length (e.g. BK) reserved only for Li-pre and Li-post signalling. In this case, the coding and puncturing patterns used for the Li-post signalling may vary, for example depending on the length of the Li-post information (i.e. the number of Li-post information bits). The coding rate and puncturing scheme may be adapted in order to fill the entire single symbol for any length of input data.

Operation of the bit interleaver 215 shown in Figure 2 is illustrated in Figure 3. The bit interleaver 215 is provided in the form of a block interleaver comprising N0 columns and NPOM/NG rows. As illustrated in Figure 3, bits are read into the bit interleaver 215 column-wise and are read out from the bit interleaver 215 row-wise to obtain the interleaved sequence.

The value of N0 may vary, for example according to the modulation scheme and code rate used. For example, when using 16-QAM and a code rate of 1/2 then N0=B, and when using 64-QAM and a code rate of 1/2 then N0=i2.

The structure illustrated in Figure 2 has an advantage of being relatively simple. However, this structure also suffers a disadvantage of relatively poor performance in some cases. For example, a loss in performance of 3dB can occur in some cases.

Therefore, what is desired is a method, apparatus and/or system for bit interleaving and/or bit de-interleaving in which performance can be improved while maintaining a relatively simple structure.

SUMMARY OF THE INVENTION

It is an aim of certain exemplary embodiments of the present invention to address, solve and/or mitigate, at least partly, at least one of the problems and/or disadvantages associated with the related art, for example at least one of the problems and/or disadvantages described herein. It is an aim of certain exemplary embodiments of the present invention to provide at least one advantage over the related art, for example at least one of the advantages described herein.

The present invention is defined in the independent claims. Advantageous features are defined in the dependent claims.

An aspect of the present invention provides a computer program comprising instructions or code which, when executed, implement a method, system and/or apparatus in accordance with any aspect, claim and/or embodiment disclosed herein. A further aspect of the present invention provides a machine-readable storage storing such a program.

Other aspects, advantages, and salient features of the invention will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the annexed drawings, disclose exemplary embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, and features and advantages of certain exemplary embodiments and aspects of the present invention will be more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figure 1 illustrates a frame structure used in DVB-T2 for transmitting data; Figure 2 illustrates one example of a BICM chain for processing a bit stream; Figure 3 illustrates operation of the bit interleaver shown in Figure 2; Figure 4 illustrates a constellation diagram for 64-DAM using a Gray mapping scheme; Figure 5 illustrates the functional structure of a bit interleaver according to an exemplary embodiment of the present invention; Figures 6a-d illustrate operation of the bit interleaver shown in Figure 5; Figure 7 illustrates the functional structure of a bit de-interleaver according to an exemplary embodiment of the present invention; Figure 8 illustrates a system according to an exemplary embodiment of the present invention; Figure 9a is a flow chart of an exemplary method for bit interleaving according to an exemplary embodiment of the present invention; and Figure 9b is a flow chart of an exemplary method for bit de-interleaving according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE PRESENT

INVENTION

The following description of exemplary embodiments of the present invention, with reference to the accompanying drawings, is provided to assist in a comprehensive understanding of the present invention, the scope of which is defined by the claims. The description includes various specific details to assist in that understanding but these are to be regarded as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope of the invention.

The same or similar components may be designated by the same or similar reference numerals, although they may be illustrated in different drawings.

Detailed descriptions of techniques, features, elements, structures, constructions, functions, operations and/or processes known in the art may be omitted for clarity and conciseness, and to avoid obscuring the subject matter of the present invention.

The terms and words used herein are not limited to the bibliographical or standard meanings, but, are merely used to enable a clear and consistent understanding of the invention.

Throughout the description and claims of this specification, the words "comprise", "include" and "contain" and variations thereof, for example "comprising" and "comprises", mean "including but not limited to", and are not intended to (and do not) exclude other features, elements, components, integers, steps, processes, operations, functions, characteristics, properties and/or groups thereof.

Throughout the description and claims of this specification, the term "substantially" means that the recited characteristic, parameter, or value need not be achieved exactly, but that deviations or variations, including for example, tolerances, measurement error, measurement accuracy limitations and other factors known to those of skill in the art, may occur in amounts that do not preclude the effect the characteristic was intended to provide.

Throughout the description and claims of this specification, the singular form, for example "a", "an" and "the", encompasses the plural unless the context otherwise requires. For example, reference to "an object" includes reference to one or more of such objects.

Throughout the description and claims of this specification, language in the general form of "X for Y" (where Y is some action, process, operation, function, activity or step and X is some means for carrying out that action, process, operation, function, activity or step) encompasses means X adapted, configured or arranged specifically, but not necessarily exclusively, to do Y. Features, elements, components, integers, steps, processes, operations, functions, characteristics, properties and/or groups thereof described or disclosed in conjunction with a particular aspect, embodiment, example or claim of the present invention are to be understood to be applicable to any other aspect, embodiment, example or claim described herein unless incompatible therewith.

Certain embodiments of the present invention provide various techniques (e.g. methods, apparatus and/or systems) for bit interleaving and/or bit de-interleaving. In certain embodiments, the techniques described herein may be implemented within a digital broadcasting system, including one or more existing and/or future generation digital broadcasting systems, for example systems developed by the Digital Video Broadcasting (DVB) Project and/or the Advanced Television Systems Committee (ATSC) (e.g. the ATSC 3.0 Standard). However, the skilled person will appreciate that the present invention is not limited to use in connection with any particular system or standard, and that various embodiments provide techniques for bit interleaving and/or bit de-interleaving that may be used in any suitable type of digital broadcasting system.

In certain embodiments, the techniques described herein may be used to bit interleave and/or bit de-interleave signalling data, for example Li-post signalling or signalling of a similar type. However, the skilled person will appreciate that the present invention is not limited to use in connection with any particular type of data, and that various embodiments provide techniques for bit interleaving and/or bit de-interleaving that may be used with any suitable type of data.

Furthermore, the present invention is not limited to use with any particular type of data structure or preamble structure. For example, in cases where a preamble structure is used, any suitable type of preamble structure, including any suitable type of single symbol or multi-symbol structure, may be used in certain embodiments of the present invention.

Embodiments of the present invention may be implemented in the form of any suitable method, system and/or apparatus for use in digital broadcasting. For example, certain embodiments may be implemented in the form of a mobile/portable terminal (e.g. mobile telephone), hand-held device, personal computer, digital television andlor digital radio broadcast transmitter and/or receiver apparatus, set-top-box, etc. Any such method, system and/or apparatus may be compatible with any suitable existing or future digital broadcast system and/or standard, for example one or more of the digital broadcasting systems and/or standards referred to herein.

Certain embodiments may be implemented in the form of a system comprising a transmitter side apparatus and a receiver side apparatus. The transmitter side apparatus may be configured to perform bit interleaving of data (and any further required processing and/or encoding), and transmit, to the receiver side apparatus, a signal corresponding to the bit interleaved data. The receiver side apparatus may be configured to receive the signal, and perform bit de-interleaving (and any further required processing and/or decoding). Certain embodiments may comprise a transmitter side apparatus only, a receiver side apparatus only, or a system comprising both a transmitter side apparatus and a receiver side apparatus.

As described above, the structure illustrated in Figure 2 suffers a disadvantage of relatively poor performance in some cases. One reason for this will now be described.

Figure 4 illustrates a constellation diagram for 64-QAM in which six-bit values are mapped to respective constellation points according to a Gray mapping scheme. Using the mapping illustrated in Figure 4, it can be seem that the two most significant bits (MSBs) of a six-bit value (bits 0 and 1) determine which quadrant of the constellation the corresponding constellation point falls into. The next two MSBs (bits 2 and 3) determine which sub-quadrant of a quadrant the corresponding constellation point falls into. Finally, the last two MSBs (bits 4 and 5) determine which of the four constellation points forming a sub-quadrant coincides with the corresponding constellation point.

Accordingly, a change in one of the first two MSBs (bits 0 and 1) corresponds to a relatively large change in position (i.e. a change in quadrant) of the corresponding constellation point.

Conversely, a relatively high level of noise is lequired to cause an error in one of these bits.

In comparison, a change in one of the next two MSBs (bits 2 and 3) corresponds to a smaller change in position (i.e. a change in sub-quadrant of a quadrant) of the corresponding constellation point, and conversely, a smaller level of noise may cause an error in these bits.

Finally, a change in one of the last two MSBs (bits 4 and 5) corresponds to a relatively small change in position (i.e. a change in constellation point of a sub-quadrant) of the corresponding constellation point, and conversely, a relatively low level of noise may cause an error in these bits.

The principles described above also apply to different modulation schemes, including different orders of QAM, for example 16-QAM, 64-QAM, 256-QAM..., or 22-QAM (m=2, 3, 4, ...).

The individual bits of an n-bit value mapped to a constellation point of a 2-QAM constellation may be regarded as passing through n respective one-bit channels. Since these individual one-bit channels are susceptible to noise to different degrees, for example for the reasons described above, the error rate for a given level of noise, and hence the channel capacity, may be different for different channels (i.e. different bits). In particular, the channel capacity for channels corresponding to lower significant bits is typically lower than for channels corresponding to higher significant bits. For certain modulation schemes, for example 22mQAM, pairs of channels may have the same or similar channel capacity, for example channels corresponding to pairs of bits {0,1}, {2,3} and {4,5} in the 64-QAM example described above.

Referring back to Figure 3, the bits mapped to a single constellation point are typically read out from the same row of the bit interleaver 215 (for example, the bits indicated by the dotted box in Figure 3). For example, in the case of 256-QAM and the 8-column bit interleaver illustrated in Figure 3, the 8 bits read out from a single row of the bit interleaver 215 are typically mapped to a single 256-QAM constellation point. This means that bits within the same column will be transmitted through the same one-bit channel. Furthermore, since bits are read into the bit interleaver 215 column-wise, a number of consecutive bits of the input bit stream will occupy the same column. Therefore, a number of consecutive bits of the input bit stream will all be transmitted through the same channel. This may result in a number of consecutive bits being transmitted through a channel having a poor capacity, which is undesirable.

Exemplary embodiments of the present invention provide a bit-interleaver that can avoid or mitigate the problem described above, thereby improving performance, while maintaining a relatively simple structure.

Figure 5 illustrates the functional structure of a bit interleaver according to an exemplary embodiment of the present invention. Figures 6a-d illustrate operation of the bit interleaver shown in Figure 5. In certain embodiments, the bit interleaver may form part of a BICM chain, for example the BICM chain shown in Figure 2. An exemplary system comprising the bit interleaver 500 shown in Figure 5 is illustrated in Figure 8. An exemplary method performed by the bit interleaver 500 shown in Figure 5 is illustrated in Figure 9a.

In the following exemplary embodiments, the bit interleaver is described in terms of a block interleaver. However, embodiments of the present invention are not limited to implementation in the form of a block interleaver. For example, in certain embodiments, the bit interleaver may be provided in an alternative form that performs bit interleaving according to the same overall interleaving pattern as that applied by an exemplary block interleaver described herein. In addition, the rows and columns of a bit interleaver described herein, and operations performed thereon, may be interchanged in alternative embodiments.

In certain exemplary embodiments described herein, an input bit sequence is first written into a block interleaver in a first direction (e.g. in a column-wise manner). Next, one or more columns (e.g. the odd-numbered columns) of the bit interleaver are permuted according to one or more first permutation patterns (e.g. the columns are flipped upside down) and/or one or more rows of the bit interleaver are permuted according to one or more second permutation patterns (e.g. the rows are cyclically shifted). Finally, an output bit sequence is obtained by reading bits from the bit interleaver in a second direction (e.g. in a row-wise manner).

As shown in Figure 5, the bit interleaver 500 at the transmitter side comprises an interleaver array 501, a mapper 503, a column permuter 505, a row permuter 507 and a de-mapper 509. The bit interleaver 500 also comprises a controller 511 for controlling the interleaver array 501, the mapper 503, the column perrnuter 505, the row permuter 507 and the de-mapper 509.

In the illustrated embodiment, the column permuter 505 and the row permuter 507 are shown as separate elements. However, in certain embodiments, the column permuter 505 and the row permuter 507 may be implemented as a single permuter block.

Furthermore, embodiments of the present invention are not limited to the exemplary structure illustrated in Figure 5. For example, in certain embodiments, the bit interleaver may be implemented in the form of a chain structure, wherein a bit sequence may be passed sequentially through various block in the chain to perform respective operation of mapping, column permuting, row permuting and de-mapping.

In addition, the references herein to an array do not necessary refer to a physical array, but can also refer to an array in a mathematical, abstract or conceptual sense. That is, a two-index variable, for example may be defined for the purpose of more clearly or conveniently defining a permutation operation. However, in certain embodiments, a permutation operation that is equivalent to (i.e. produces the same output given a certain input) the permutation operations described herein may be applied to a bits stored or processed solely in a linear manner.

The interleaver array 501 comprises M rows and N columns, thereby forming an MxN array of cells, wherein a cell in the ith row and jth column of the array (i=0, 1, 2 M-1 and j=0, 1, 2 N-i) may be denoted The mapper 503 receives an input bit sequence {ad (k=0, 1, 2, ...) and maps bits of the input bit sequence to cells of the interleaver array 501. For example, the mapper 503 writes the input bit sequence {ak} into the interleaver array 501 in a column-wise manner such that bit a is mapped to cell where i=k mod M and j=[kIMJ, where mod denotes the modulo operator and Li denotes the floor operator. This mapping is illustrated in Figure 6a.

The column permuter 505 is configured for permuting two or more cells of one or more columns of the interleaver array 501 according to one or more permutation patterns. For example, the column permuter 505 may be configured to permute all cells of every pth column, for example the set of columns {j} such that j mod p=q, wherein p=i, 2, 3, ... and q=0, 1, 2 p-i are fixed values. In the illustrated embodiment, the column permuter 505 is configured to permute the odd-numbered columns, for example the set of columns {j} such thatj mod 2=1. Permuting cells within the pth column (p=0, 1, 2 N-i) may be regarded as permuting cells within a group of cells denoted G"={B,} where i=0, 1, 2 M-1. 11.

The column permuter 505 may permute some or all of the columns using the same permutation pattern, and/or may permute some or all of the columns using different permutation patterns. In the illustrated embodiment, the odd-numbered columns are each permuted using the same permutation pattern.

The column permuter 505 may permute a column using any suitable permutation pattern.

For example, a bit at position may be permuted to position Blo)J, where m1Ø) denotes a first permutation function. For example, in the illustrated embodiment, as shown in Figure 6b, the column permuter 505 is configured to flip the jth column of the interleaver array 501 upside down such that a bit at a position before column permutation is permuted to a new position B'jj=BM.j.l after column permutation, i.e. such that 7C1(i)=M-i-1.

The cells in a column may be permuted in any other suitable way. For example, the cells in a column may be permuted quasi-randomly. As another example, a column may be divided (e.g. equally) into two or more sub-columns and the cells of each sub-column may be independently permuted according to a certain permutation pattern (e.g. by flipping each sub-column upside down).

The row permuter 507 is configured for permuting two or more cells of one or more rows of the interleaver array 501 according to one or more permutation patterns. For example, a bit at position may be permuted to position B-g), where m2(j) denotes a second permutation function. Permuting cells within the qth row (q=0, 1, 2 M-1) may be regarded as permuting cells within a group of cells denoted G2q{Bq,j} where j=0, 1, 2 N-i. The row permuter 507 may permute some or all of the rows using the same permutation pattern, and/or may permute some or all of the rows using different permutation patterns.

In certain embodiments, a permutation pattern may comprise a shift. For example, the row permuter 507 may be configured to shift all cells of a certain row by a certain number of cells in a certain direction (e.g. leftwards or rightwards). In the illustrated embodiment, as shown in Figure 6c, the rows are cyclically shifted such that the lowest numbered row is not shifted, the next row is shifted to the right by one cell, the next row is shifted to the right by two cells, and so on. More generally, in the case of using shifting as the permutation patterns, the row permuter 507 is configured to shift rows such that a bit at a position before row permutation is permuted to a new position B'jj=Bja+so)) mod N (i.e. such that 2r2(j)=(j+s(i)) mod N) after row permutation, where s(i) denotes a shift amount (e.g. in units of cells) defined as a function of the row number i. For example, in the illustrated embodiment, s(i)=i. In alternative embodiments, the shift amount may be defined in other ways, for example sU)=2i or s(i)=-i.

By applying the column and row permutations described above to the interleaver array 501, an improvement in performance may be achieved. For example, by permuting different rows of the interleaver array 501 using different permutation patterns (e.g. by shifting different rows of the interleaver array 501 by different amounts), it can be seen that consecutive bits of the original input bit sequence {ak} that are read into the same column of the interleaver array 501 will tend to become spread over different columns following permutation of the rows. Consequently, consecutive bits of the input bit sequence {ak} will tend to occupy different bit positions when bits output from the bit interleaver 500 are mapped to constellation points. Hence, consecutive bits will tend to be transmitted through one-bit channels having different channel capacities, thereby reducing the chances that consecutive bits will be transmitted through a channel having a relatively low channel capacity.

In addition, by permuting certain columns of the interleaver array 501 (e.g. by flipping odd-numbered columns), a further improvement in performance may be achieved, for example for the following reason.

In the case that rows of the interleaver array 501 are shifted without the columns of the interleaver array 501 also being permuted, then as illustrated in Figure Sd it can be seen that after the rows are shifted, the bit values occupying a particular column contain a relatively high number of pairs of values corresponding to values that are N-i positions apart in the original bit sequence {ak}. Furthermore, after the rows are shifted, the bit values occupying adjacent columns contain a relatively high number of pairs of values corresponding to consecutive values in the original bit sequence {ak} and many pairs of values corresponding to values that are N and N-2 positions apart in the original bit sequence {ak}.

For the reasons mentioned above, bits occupying the same column will be transmitted through the same one-bit channel having a certain channel capacity. Furthermore, for the reasons mentioned above, in some cases, bits occupying adjacent columns will be transmitted through different one-bit channels having the same or similar channel capacity.

Therefore, data occurring within the original bit sequence {aJ that repeats with certain periodicity (e.g. with period N), will tend to be transmitted through one-bit channels having the same or similar channel capacity. This may lead to such data being transmitted through channels having a relatively low channel capacity, which is undesirable.

However, by permuting certain columns, for example in the manner shown in Figure 6c, the bit values occupying a particular column, and bit values occupying adjacent columns contain fewer pairs of values corresponding to adjacent values in the original bit sequence {ak} and fewer pairs of values corresponding to values that are N, N-i and N-2 positions apart in the original bit sequence {aJ. Hence, periodic data occurring in the original bit sequence {aJ is less likely to be transmitted through channels having the same or similar bit capacity, thereby reducing the chance that such data will be transmitted through channels having relatively low channel capacities. As can be seen by comparing Figures 6c and 6d, the case of Figure 6d in which columns are not permuted results in many more pairs of values corresponding to values that are N positions apart in the original bit sequence (indicated in Figure 6d by the dotted ovals) being transmitted through channels with the same or similar channel capacity.

The de-mapper 509 is configured to de-map bits from the interleaver array 501 to generate an output interleaved bit sequence {bk}. For example, the de-mapper may be configured to read bits from the interleaver array 50i in a row-wise manner such that bit bk of the output bit sequence is de-mapped from cell of the interleaver array 501, where k=Ni+j.

The column permuter 505 and the row permuter 507 may be configured to operate on the interleaver array 501 in any order. For example, in some embodiments, the column permuter 505 may permute columns of the interleaver array 501 before the row permuter 507 permutes rows of the interleaver array 501. Alternatively, the row permuter 507 may permute rows of the interleaver array 501 before the column permuter 505 permutes columns of the interleaver array 501. In some embodiments, the order in which the column permuter 505 and the row permuter 507 operate on the interleaver array 501 may be controlled, for example by the controller 511.

One specific example of bit-interleaving according to an exemplary embodiment of the present invention will now be described. In this example, the input data has a length L-i and the number of columns is denoted C. Matrices of size (R(rows), C(columns)) are defined where R=ceil(L-i/C). A first matrix output, M, is defined as M(r,c)=input(c*R+(ri)). One example of the first matrix output is illustrated in Figure 6a. A second matrix, A, is computed from M according to A(r,c)=M((R-r) mod R,c) for (c mod 20). One example of the second matrix output is illustrated in Figure 6b. A third matrix, B, is computed from A according to B(r,c)=A(r, (c+r) mod C). One example of the third matrix output is illustrated in Figure 6c.

In certain embodiments, only one of the column permuter 505 and the row permuter may be provided, such that only one of columns and rows may be permuted. In other embodiments, both the column permuter 505 and the row permuter 507 may be provided, where one or both of the column permuter 505 and the row permuter 507 may be selectively activated and deactivated. This configuration allows the bit interleaver to operate according to a number of different modes, including (i) a mode in which only rows are permuted, (ii) a mode in which only columns are permuted, (iii) a mode in which both rows and columns are permuted, or (iv) a mode in which neither rows nor columns are permuted. A particular mode may be selected, for example by the controller 511, according to any suitable conditions or criteria.

For example, in certain embodiments, a mode may be selected based on the length of the bit sequence {ad, which may be denoted The bit interleaver 500 may be configured to vary the number of columns, N, used during operation of the interleaver array 501. For example, the mapper 503 and the de-mapper 509 may be configured to map and de-map bits to and from a certain number of columns of the interleaver array 501, which may be all available columns or a subset of the available columns.

The number of columns, N, used during operation of the interleaver array 501 may be selected, for example by the controller 511, according to any suitable conditions or criteria.

For example, in certain embodiments, the number of columns may be selected based on the length, of the bit sequence {ak}. For example, for relatively high values of the number of columns may be equal to the number of bits that are mapped to each constellation point (e.g. denoted Nmod for 2NmodQAM) whereas for relatively low values of the number of columns may be equal to half the number of bits that are mapped to each constellation point (e.g. Nmod/2 columns for 2Nnhbod..QAM) In some embodiments, the number of columns may be independent of the value of N01 for certain constellation orders.

For example, for 16QAM (NmoF4), the number of columns may be equal to Nmod(4) for all values of N01.

As described above, the selective activation and deactivation of the column permuter 505 and the row permuter 507, and the selection of the number of columns used during operation of the interleaver array 501 may be performed based, at least partly, on the length, N01, of the bit sequence {ak}. In some embodiments, the bit interleaver 500 may store a table containing information indicating appropriate configuration settings (e.g. activation or deactivation of the column permuter 505 and/or the row permuter 507, and the number of interleaver array 501 columns) for each value of N091. In some embodiments the same configuration settings may be used for a range of values of N01, in which case the table may be simplified by storing the configuration settings for each range of values, rather than for each individual value. In other embodiments, the appropriate configuration settings may be signalled by the transmitter side to the receiver side, for example using a pair of activation flags corresponding respectively to the column permuter 505 and the row permuter 507, and a field indicating the number of interleaver array 501 columns.

At the receiver side, a bit de-interleaver corresponding to the bit interleaver at the transmitter side is provided. The bit de-interleaver is configured to bit de-interleave a bit sequence obtained by demodulating a sequence of received symbols. Figure 7 illustrates the functional structure of a bit de-interleaver according to an exemplary embodiment of the present invention. An exemplary system comprising the bit de-interleaver 700 shown in Figure 7 is illustrated in Figure 8. An exemplary method performed by the bit de-interleaver 700 shown in Figure 5 is illustrated in Figure 9b.

As shown in Figure 7, the bit de-interleaver 700 comprises a de-interleaver array 701, a mapper 703, a column permuter 705, a row permuter 707, and a de-mapper 709. The bit de-interleaver also comprises a controller 711 for controlling the de-interleaver array 701, mapper 703, column permuter 705, row permuter 707 and de-mapper 709.

The de-interleaver array 701 has a similar form to the interleaver array 501 at the transmitter side, and comprises M rows and N columns forming an MxN array of cells. The mapper 703 performs the inverse operation of the operation performed by the de-mapper 509 at the transmitter side. For example, the mapper 703 is configured to write a bit sequence bk row-wise into the de-interleaver array 701.

The column permuter 705 is configured to perform the inverse operation of the operation performed by the column permuter 505 at the transmitter side. For example, the column permuter 705 is configured to permute the cells of one or more columns of the de-interleaver array 701 according to one or more permutation patterns, where the permutation patterns used by the column permuter 705 are the inverses of the permutation patterns used by the column permuter 505 at the transmitter side. For example, in the case that the column permuter 505 of the transmitter side flips odd-numbered columns, the column permuter 705 of the receiver side may also flip odd-numbered columns.

Similarly, the row permuter 707 is configured to perform the inverse operation of the operation performed by the row permuter 507 at the transmitter side. For example, the row permuter 707 is configured to permute the cells of one or more rows of the de-interleaver array 701 according to one or more permutation patterns, where the permutation patterns used by the row permuter 707 are the inverses of the permutation patterns used by the row permuter 507 at the transmitter side. For example, in the case that the row permuter 507 of the transmitter side cyclically shifts the rows, the row permuter 707 of the receiver side may cyclically shift the rows, but in the opposite direction to the cyclic shifting performed by the row permuter 507 at the transmitter side.

The column permuter 705 and the row permuter 707 at the receiver side operate on the de-interleaver array 701 in the reverse order to the column permuter 505 and the row permuter 507 at the transmitter side.

The de-mapper 709 performs the inverse operation of the operation performed by the mapper 503 at the transmitter side. For example, the de-mapper 709 is configured to read a bit sequence a column-wise from the de-interleaver array 701 to obtain the de-interleaved bit sequence.

In a similar manner described above in relation to the transmitter side, the column permuter 705 and the row permuter 707 at the receiver side may be configured to be selectively activated and deactivated, and the de-interleaver array 701 may be configured to operate using a certain number of columns. For example, the configuration settings for configuring the column permuter 705, the row permuter 707 and the de-interleaver array 701 may be determined using a table in a manner described above, or may be signalled by the transmitter side.

It will be appreciated that certain embodiments of the present invention may be implemented in the form of hardware, software or any combination of hardware and software. Any such software may be stored in the form of volatile or non-volatile storage, for example a storage device like a ROM, whether erasable or rewritable or not, or in the form of memory such as, for example, RAM, memory chips, device or integrated circuits or on an optically or magnetically readable medium such as, for example, a CD, DVD, magnetic disk or magnetic tape or the like.

It will be appreciated that the storage devices and storage media are embodiments of machine-readable storage that are suitable for storing a program or programs comprising instructions that, when executed, implement certain embodiments of the present invention.

Accordingly, certain embodiments provide a program comprising code for implementing a method, apparatus or system as claimed in any one of the claims of this specification, and a machine-readable storage storing such a program. Still further, such programs may be conveyed electronically via any medium, for example a communication signal carried over a wired or wireless connection, and embodiments suitably encompass the same.

While the invention has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention, as defined by the appended claims.

Claims

Claims 1. A method for bit interleaving, the method comprising: -mapping a set of bits a{ak: k 0, 1, 2, ... Nposrl}tO an array B{B1: i=0, 1, 2 M-1; j=O, 1,2 N-1} such that bitak maps to BkmOdM UML wherein mod denotes the modulo operator, Li denotes the floor operator, and M and N are constants; -performing at least one of: a a first permutation operation comprising permuting two or more bits within each of one or more first groups of bits, wherein each first group of bits is defined i=O, 1,2 M-1; pc{0, 1,2 N-1}}; and o a second permutation operation comprising permuting two or more bits within each of one or more second groups of bits, wherein each second group of bits is defined by Q2q={Bq,j: j=0, 1, 2 N-i; qe{0, 1, 2 M-1}}; and -de-mapping bits from B to obtain an interleaved set of bits b{bk: k= 0, 1, 2, Nposri} such that bit is de-mapped to bit bN+.
2. A method according to claim 1, wherein the one or more first groups of bits are the set of first groups {: p mod g=h; ge{1, 2, 3, ...}; he{0, 1, 2 g-1}}.
3. A method according to claim 2, wherein g=2 and h=0 or 1
4. A method according to claim 1, 2 or 3, wherein the first permutation operation comprises permuting a bit at position to position Bi®.p, wherein 7c1(i) comprises a first permutation function.
5. A method according to claim 4, wherein 7r1(i)=M-i-i.
6. A method according to any preceding claim, wherein second permutation operation comprises permuting a bit at position Bqj to position Bq,,q), wherein c2(j) comprises a second permutation function.
7. A method according to claim 6, wherein m2(j)=(j+s(q)) mod N, wherein s(q) comprises a shift function.
8. A method according to claim 7, wherein s(q)=q or s(q)=-q.
9. A method according to claim 1, -wherein the step of mapping comprises writing the set of bits to a block interleaver having M rows and N columns in a column-wise manner; -wherein: o the first permutation operation comprises permuting two or more bits within each of one or more columns of the block interleaver; and o the second permutation operation comprises permuting two or more bits within each of one or more rows of the block interleaver; and -wherein the step of de-mapping comprises reading the set of interleaved bits b from the block interleaver in a row-wise manner.
10. A method according to claim 9, wherein the first permutation operation comprises permuting bits within every gth column.
11. A method according to claim 10, wherein the first permutation operation comprises permuting bits within each of the odd-numbered columns or each of the even-numbered columns.
12. A method according to claim 9, 10 or 11, wherein the first permutation operation comprises permuting the bits within one or more columns according to a first permutation function.
13. A method according to claim 12, wherein the first permutation function comprises flipping the bits of one or more columns upside down.
14. A method according to any of claims 9 to 13, wherein the second permutation operation comprises permuting the bits within one or more rows according to a second permutation functions.
15. A method according to claim 14, wherein the second permutation function comprises shifting one or more rows.
16. A method according to claim 15, wherein the second permutation function comprises shifting the pth row by an amount p in a certain direction
17. A method according to any preceding claim, comprising the further step of selecting a value of N.
18. A method according to claim 17, wherein the value of N is selected based on the value of
19. A method according to claim 18, wherein, if the value of N0 exceeds a threshold then the value of N is selected as Nfl0d, and if the value of N01 does not exceed the threshold then the value of N is selected as NmodI2, wherein Nmod is related to the order of a modulation scheme used to transmit the interleaved set of bits.
20. A method according to claim 18 or 19, wherein the step of selecting a value of N comprises the step of obtaining a value of N using a table that stores information indicating values of N associated with values of or ranges of values of N05.
21. A method according to any of claims 17 to 20, comprising the further step of signalling the selected value of N.
22. A method according to any preceding claim, comprising the further step of selecting one or both of the first and second permutation operation to apply in the bit interleaving method.
23. A method according to any preceding claim, comprising the further step of signalling which of the first and second permutation operations is applied in the bit interleaving method.
24. A bit interleaver comprising: -a mapper for mapping a set of bits a{ak: k= 0, 1, 2, ... Nposrl}to an array B={B,: i=0, 1, 2 M-1; j=0, 1, 2 N-1} such that bit a maps to Bk mod M. k/Mi, wherein mod denotes the modulo operator, Li denotes the floor operator, and M and N are constants; -a permuter for performing at least one of: o a first permutation operation comprising permuting two or more bits within each of one or more first groups of bits, wherein each first group of bits is defined i=0, 1,2 M-1; pe{0, 1,2 N-1}}; and o a second permutation operation comprising permuting two or more bits within each of one or more second groups of bits, wherein each second group of bits is defined by G2q={Bqj: j=0, 1, 2 N-i; qe{0, 1, 2 M-1}}; and 21.-a de-mapper for de-mapping bits from to obtain an interleaved set of bits b{bk: k= 0, 1, 2, ... Nposrl} such that bit is de-mapped to bit bNj+j.
25. A bit interleaver according to claim 24, wherein the one or more first groups of bits are the set of first groups {1: p mod g=h; ge{l, 2,3, ...}; he{0, 1,2 g-1}}.
26. A bit interleaver according to claim 25, wherein g=2 and h=O or 1
27. A bit interleaver according to claim 24, 25 or 26, wherein the first permutation operation comprises permuting a bit at position to position wherein m1(i) comprises a first permutation function.
28. A bit interleaver according to claim 27, wherein it1 (D=M-i-1.
29. A bit interleaver according to any of claims 24 to 28, wherein second permutation operation comprises permuting a bit at position to position B2@, wherein m2(j) comprises a second permutation function.
30. A bit interleaver according to claim 29, wherein ic2(j)=(j+s(q)) mod N, wherein s(q) comprises a shift function.
31. A bit interleaver according to claim 30, wherein s(q)=q or s(q)=-q.
32. A bit interleaver according to claim 24, -wherein the mapper is configured for writing the set of bits a to a block interleaver having M rows and N columns in a column-wise manner; -wherein: o the first permutation operation comprises permuting two or more bits within each of one or more columns of the block interleaver; and o the second permutation operation comprises permuting two or more bits within each of one or more rows of the block interleaver; and -wherein the de-mapper is configured for reading the set of interleaved bits b from the block interleaver in a row-wise manner.
33. A bit interleaver according to claim 32, wherein the first permutation operation comprises permuting bits within every gth column.
34. A bit interleaver according to claim 33, wherein the first permutation operation comprises permuting bits within each of the odd-numbered columns or each of the even-numbered columns.
35. A bit interleaver according to claim 32, 33 or 34, wherein the first permutation operation comprises permuting the bits within one or more columns according to a first permutation function.
36. A bit interleaver according to claim 35, wherein the first permutation function comprises flipping the bits of one or more columns upside down.
37. A bit interleaver according to any of claims 32 to 36, wherein the second permutation operation comprises permuting the bits within one or more rows according to a second permutation functions.
38. A bit interleaver according to claim 37, wherein the second permutation function comprises shifting one or more rows.
39. A bit interleaver according to claim 38, wherein the second permutation function comprises shifting the pth row by an amount p in a certain direction
40. A bit interleaver according to any of claims 24 to 39, further comprising a controller for selecting a value of N.
41. A bit interleaver according to claim 40, wherein the value of N is selected based on the value of
42. A bit interleaver according to claim 41, wherein, if the value of N0 exceeds a threshold then the value of N is selected as Nifiod, and if the value of does not exceed the threshold then the value of N is selected as Nmod/2, wherein Nifiod is related to the order of a modulation scheme used to transmit the interleaved set of bits.
43. A bit interleaver according to claim 41 or 42, wherein the controller is configured for obtaining a value of N using a table that stores information indicating values of N associated with values of or ranges of values of
44. A bit interleaver according to any of claims 40 to 43, wherein the controller is configured for controlling signalling the selected value of N.
45. A bit interleaver according to any preceding claim, wherein the controller is configured for selecting one or both of the first and second permutation operation to apply in the bit interleaving method.
46. A bit interleaver according to any of claims 24 to 45, wherein the controller is configured for controlling signalling which of the first and second permutation operations is applied in the bit interleaving method.
47. A method for bit de-interleaving, the method comprising: -mapping a set of bits b{bk: k= 0, 1, 2, ... N0i}to an array B={B: i=0, 1, 2 M-1; j=0, 1, 2 N-l} such that bit is mapped from bit bNj+j. wherein M and N are constants; -performing at least one of: o a first permutation operation comprising permuting two or more bits within each of one or more first groups of bits, wherein each first group of bits is defined byG"={B: i=0, 1,2 M-1; pe{0, 1,2 N-1}}; and o a second permutation operation comprising permuting two or more bits within each of one or more second groups of bits, wherein each second group of bits is defined by G2q={Bq,j: j=0, 1, 2 N-i; qe{0, 1, 2 M-1}}; and -de-mapping bits from B to obtain a de-interleaved set of bits a{ak: k= 0, 1, 2, N031-1} such that bit ak is de-mapped from BkmOdM,Lk!MJ, wherein mod denotes the modulo operator and Li denotes the floor operator.
48. A bit de-interleaver comprising: -a mapper for mapping a set of bits b{bk: k= 0, 1, 2, ... Nposrl} to an array B={B: i=0, i, 2 M-1; j=0, 1, 2 N-i} such that bit is mapped from bit bNjtj.wherein M and N are constants; -a permuter for performing at least one of: o a first permutation operation comprising permuting two or more bits within each of one or more first groups of bits, wherein each first group of bits is defined i=0, 1,2 M-i; pe{0, 1,2 N-i}}; and o a second permutation operation comprising permuting two or more bits within each of one or more second groups of bits, wherein each second group of bits is defined by 2q{Bq,j: j=O, 1, 2. N-i; qe{O, i, 2. M-i}}; and de-mapping bits from to obtain a de-interleaved set of bits a{ak: k= 0, i, 2, Nposri} such that bit ak is de-mapped from 3kmodMLk/MJ, wherein mod denotes the modulo operator and Li denotes the floor operator.